1 /* drivers/i2c/busses/i2c-rk30-adapter.c
3 * Copyright (C) 2012 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 /* Control register */
19 #define I2C_CON_EN (1 << 0)
20 #define I2C_CON_MOD(mod) ((mod) << 1)
21 #define I2C_CON_MASK (3 << 1)
28 #define I2C_CON_START (1 << 3)
29 #define I2C_CON_STOP (1 << 4)
30 #define I2C_CON_LASTACK (1 << 5)
31 #define I2C_CON_ACTACK (1 << 6)
33 /* Clock dividor register */
34 #define I2C_CLKDIV 0x004
35 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
37 /* the slave address accessed for master rx mode */
38 #define I2C_MRXADDR 0x008
39 #define I2C_MRXADDR_LOW (1 << 24)
40 #define I2C_MRXADDR_MID (1 << 25)
41 #define I2C_MRXADDR_HIGH (1 << 26)
43 /* the slave register address accessed for master rx mode */
44 #define I2C_MRXRADDR 0x00c
45 #define I2C_MRXRADDR_LOW (1 << 24)
46 #define I2C_MRXRADDR_MID (1 << 25)
47 #define I2C_MRXRADDR_HIGH (1 << 26)
50 #define I2C_MTXCNT 0x010
53 #define I2C_MRXCNT 0x014
55 /* interrupt enable register */
57 #define I2C_BTFIEN (1 << 0)
58 #define I2C_BRFIEN (1 << 1)
59 #define I2C_MBTFIEN (1 << 2)
60 #define I2C_MBRFIEN (1 << 3)
61 #define I2C_STARTIEN (1 << 4)
62 #define I2C_STOPIEN (1 << 5)
63 #define I2C_NAKRCVIEN (1 << 6)
64 #define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
65 #define IRQ_ALL_DISABLE 0
67 /* interrupt pending register */
69 #define I2C_BTFIPD (1 << 0)
70 #define I2C_BRFIPD (1 << 1)
71 #define I2C_MBTFIPD (1 << 2)
72 #define I2C_MBRFIPD (1 << 3)
73 #define I2C_STARTIPD (1 << 4)
74 #define I2C_STOPIPD (1 << 5)
75 #define I2C_NAKRCVIPD (1 << 6)
76 #define I2C_IPD_ALL_CLEAN 0x7f
79 #define I2C_FCNT 0x020
81 /* I2C tx data register */
82 #define I2C_TXDATA_BASE 0X100
84 /* I2C rx data register */
85 #define I2C_RXDATA_BASE 0x200
88 static void rk30_show_regs(struct rk30_i2c *i2c)
91 i2c_dbg(i2c->dev, "i2c->start = %d\n", i2c->state);
92 i2c_dbg(i2c->dev, "I2C_CON: 0x%08x\n", i2c_readl(i2c->regs + I2C_CON));
93 i2c_dbg(i2c->dev, "I2C_CLKDIV: 0x%08x\n", i2c_readl(i2c->regs + I2C_CLKDIV));
94 i2c_dbg(i2c->dev, "I2C_MRXADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXADDR));
95 i2c_dbg(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXRADDR));
96 i2c_dbg(i2c->dev, "I2C_MTXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MTXCNT));
97 i2c_dbg(i2c->dev, "I2C_MRXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXCNT));
98 i2c_dbg(i2c->dev, "I2C_IEN: 0x%08x\n", i2c_readl(i2c->regs + I2C_IEN));
99 i2c_dbg(i2c->dev, "I2C_IPD: 0x%08x\n", i2c_readl(i2c->regs + I2C_IPD));
100 i2c_dbg(i2c->dev, "I2C_FCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_FCNT));
101 for( i = 0; i < 8; i ++)
102 i2c_dbg(i2c->dev, "I2C_TXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_TXDATA_BASE + i * 4));
103 for( i = 0; i < 8; i ++)
104 i2c_dbg(i2c->dev, "I2C_RXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_RXDATA_BASE + i * 4));
106 static inline void rk30_i2c_enable(struct rk30_i2c *i2c, unsigned int lastnak)
108 unsigned int con = 0;
111 con |= I2C_CON_MOD(i2c->mode);
113 con |= I2C_CON_LASTACK;
114 con |= I2C_CON_START;
115 i2c_writel(con, i2c->regs + I2C_CON);
117 static inline void rk30_i2c_disable(struct rk30_i2c *i2c)
119 i2c_writel( 0, i2c->regs + I2C_CON);
122 static inline void rk30_i2c_clean_start(struct rk30_i2c *i2c)
124 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
126 con &= ~I2C_CON_START;
127 i2c_writel(con, i2c->regs + I2C_CON);
129 static inline void rk30_i2c_send_start(struct rk30_i2c *i2c)
131 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
133 con |= I2C_CON_START;
134 if(con & I2C_CON_STOP)
135 dev_warn(i2c->dev, "I2C_CON: stop bit is set\n");
137 i2c_writel(con, i2c->regs + I2C_CON);
139 static inline void rk30_i2c_send_stop(struct rk30_i2c *i2c)
141 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
144 if(con & I2C_CON_START)
145 dev_warn(i2c->dev, "I2C_CON: start bit is set\n");
147 i2c_writel(con, i2c->regs + I2C_CON);
149 static inline void rk30_i2c_clean_stop(struct rk30_i2c *i2c)
151 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
153 con &= ~I2C_CON_STOP;
154 i2c_writel(con, i2c->regs + I2C_CON);
157 static inline void rk30_i2c_disable_irq(struct rk30_i2c *i2c)
159 i2c_writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
162 static inline void rk30_i2c_enable_irq(struct rk30_i2c *i2c)
164 i2c_writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
167 /* SCL Divisor = 8 * (CLKDIVL + CLKDIVH)
168 * SCL = i2c_rate/ SCLK Divisor
170 static void rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
172 unsigned long i2c_rate = clk_get_rate(i2c->clk);
174 unsigned int div, divl, divh;
176 if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
178 i2c->i2c_rate = i2c_rate;
179 i2c->scl_rate = scl_rate;
180 div = rk30_ceil(i2c_rate, scl_rate * 8);
181 divh = divl = rk30_ceil(div, 2);
182 i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
183 i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV));
186 static void rk30_i2c_init_hw(struct rk30_i2c *i2c, unsigned long scl_rate)
189 rk30_i2c_set_clk(i2c, scl_rate);
192 /* returns TRUE if we this is the last byte in the current message */
193 static inline int is_msglast(struct rk30_i2c *i2c)
195 return i2c->msg_ptr == i2c->msg->len-1;
198 /* returns TRUE if we reached the end of the current message */
199 static inline int is_msgend(struct rk30_i2c *i2c)
201 return i2c->msg_ptr >= i2c->msg->len;
204 static void rk30_i2c_stop(struct rk30_i2c *i2c, int ret)
210 i2c->state = STATE_IDLE;
216 i2c_writel(I2C_STOPIEN, i2c->regs + I2C_IEN);
217 i2c->state = STATE_STOP;
218 rk30_i2c_send_stop(i2c);
221 static inline void rk30_set_rx_mode(struct rk30_i2c *i2c, unsigned int lastnak)
223 unsigned long con = i2c_readl(i2c->regs + I2C_CON);
225 con &= (~I2C_CON_MASK);
226 con |= (I2C_CON_MOD_RX << 1);
228 con |= I2C_CON_LASTACK;
229 i2c_writel(con, i2c->regs + I2C_CON);
231 static void rk30_irq_read_prepare(struct rk30_i2c *i2c)
233 unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
235 if(len <= 32 && i2c->msg_ptr != 0)
236 rk30_set_rx_mode(i2c, 1);
237 else if(i2c->msg_ptr != 0)
238 rk30_set_rx_mode(i2c, 0);
241 rk30_i2c_stop(i2c, i2c->error);
248 i2c_writel(cnt, i2c->regs + I2C_MRXCNT);
250 static void rk30_irq_read_get_data(struct rk30_i2c *i2c)
252 unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
255 len = (len >= 32)?32:len;
257 for(i = 0; i < len; i++){
259 p = i2c_readl(i2c->regs + I2C_RXDATA_BASE + (i/4) * 4);
260 i2c->msg->buf[i2c->msg_ptr++] = (p >>((i%4) * 8)) & 0xff;
265 static void rk30_irq_write_prepare(struct rk30_i2c *i2c)
267 unsigned int data = 0, cnt = 0, i, j;
271 rk30_i2c_stop(i2c, i2c->error);
274 for(i = 0; i < 8; i++){
276 for(j = 0; j < 4; j++) {
279 if(i2c->msg_ptr == 0 && cnt == 0)
280 byte = (i2c->addr & 0x7f) << 1;
282 byte = i2c->msg->buf[i2c->msg_ptr++];
284 data |= (byte << (j * 8));
286 i2c_writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
290 i2c_writel(cnt, i2c->regs + I2C_MTXCNT);
292 static void rk30_i2c_irq_nextblock(struct rk30_i2c *i2c, unsigned int ipd)
294 switch (i2c->state) {
296 if(!(ipd & I2C_STARTIPD)){
297 rk30_i2c_stop(i2c, -ENXIO);
298 dev_err(i2c->dev, "Addr[0x%02x] no start irq in STATE_START\n", i2c->addr);
300 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
304 i2c_writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
305 rk30_i2c_clean_start(i2c);
306 if(i2c->mode == I2C_CON_MOD_TX){
307 i2c_writel(I2C_MBTFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
308 i2c->state = STATE_WRITE;
311 i2c_writel(I2C_MBRFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
312 i2c->state = STATE_READ;
316 if(!(ipd & I2C_MBTFIPD)){
317 rk30_i2c_stop(i2c, -ENXIO);
318 dev_err(i2c->dev, "Addr[0x%02x] no mbtf irq in STATE_WRITE\n", i2c->addr);
320 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
323 i2c_writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
325 rk30_irq_write_prepare(i2c);
328 if(!(ipd & I2C_MBRFIPD)){
329 rk30_i2c_stop(i2c, -ENXIO);
330 dev_err(i2c->dev, "Addr[0x%02x] no mbrf irq in STATE_READ, ipd = 0x%x\n", i2c->addr, ipd);
332 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
335 i2c_writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
336 rk30_irq_read_get_data(i2c);
338 rk30_irq_read_prepare(i2c);
341 if(!(ipd & I2C_STOPIPD)){
342 rk30_i2c_stop(i2c, -ENXIO);
343 dev_err(i2c->dev, "Addr[0x%02x] no stop irq in STATE_STOP\n", i2c->addr);
345 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
348 rk30_i2c_clean_stop(i2c);
349 i2c_writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
350 i2c->state = STATE_IDLE;
360 static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
362 struct rk30_i2c *i2c = dev_id;
365 spin_lock(&i2c->lock);
366 ipd = i2c_readl(i2c->regs + I2C_IPD);
367 if(i2c->state == STATE_IDLE){
368 dev_info(i2c->dev, "Addr[0x%02x] irq in STATE_IDLE, ipd = 0x%x\n", i2c->addr, ipd);
369 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
373 if(ipd & I2C_NAKRCVIPD){
374 i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
375 i2c->error = -EAGAIN;
378 rk30_i2c_irq_nextblock(i2c, ipd);
380 spin_unlock(&i2c->lock);
385 static int rk30_i2c_set_master(struct rk30_i2c *i2c, struct i2c_msg *msgs, int num)
387 unsigned int addr = (msgs[0].addr & 0x7f) << 1;
388 unsigned int reg_valid_bits = 0;
389 unsigned int reg_addr = 0;
392 i2c->count = msgs[0].len;
393 if(!(msgs[0].flags & I2C_M_RD)){
395 i2c->mode = I2C_CON_MOD_TX;
400 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
401 i2c_writel(0, i2c->regs + I2C_MRXRADDR);
402 i2c->mode = I2C_CON_MOD_TRX;
403 //i2c->mode = I2C_CON_MOD_RX;
407 i2c->count = msgs[1].len;
410 reg_addr = msgs[0].buf[0];
411 reg_valid_bits |= I2C_MRXADDR_LOW;
414 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
415 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
418 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
419 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
424 if((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
427 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
428 i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
429 i2c->mode = I2C_CON_MOD_RRX;
431 else if(!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
433 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
434 i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
435 i2c->mode = I2C_CON_MOD_TRX;
441 dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
449 * this starts an i2c transfer
451 static int rk30_i2c_doxfer(struct rk30_i2c *i2c,
452 struct i2c_msg *msgs, int num)
454 unsigned long timeout, flags;
459 spin_lock_irqsave(&i2c->lock, flags);
460 if(rk30_i2c_set_master(i2c, msgs, num) < 0){
461 spin_unlock_irqrestore(&i2c->lock, flags);
462 dev_err(i2c->dev, "addr[0x%02x] set master error\n", msgs[0].addr);
465 i2c->addr = msgs[0].addr;
469 i2c->state = STATE_START;
470 i2c_writel(I2C_STARTIEN, i2c->regs + I2C_IEN);
471 spin_unlock_irqrestore(&i2c->lock, flags);
473 rk30_i2c_enable(i2c, (i2c->count > 32)?0:1); //if count > 32, byte(32) send ack
475 timeout = wait_event_timeout(i2c->wait, (i2c->is_busy == 0), msecs_to_jiffies(I2C_WAIT_TIMEOUT));
477 spin_lock_irqsave(&i2c->lock, flags);
478 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
479 spin_unlock_irqrestore(&i2c->lock, flags);
482 i2c->state = STATE_IDLE;
483 if(i2c->error < 0) i2c->error = -ETIMEDOUT;
484 rk30_i2c_send_stop(i2c);
485 dev_err(i2c->dev, "addr[0x%02x] wait event timeout, state: %d, is_busy: %d, error: %d\n",
486 msgs[0].addr, i2c->state, i2c->is_busy, i2c->error);
489 rk30_i2c_disable_irq(i2c);
490 rk30_i2c_disable(i2c);
492 if(i2c->error == -EAGAIN)
493 dev_err(i2c->dev, "No ack(retry %d), Maybe slave(addr: 0x%02x) not exist or abnormal power-on\n",
494 i2c->adap.retries + 1, i2c->addr);
500 * first port of call from the i2c bus code when an message needs
501 * transferring across the i2c bus.
504 static int rk30_i2c_xfer(struct i2c_adapter *adap,
505 struct i2c_msg *msgs, int num)
508 unsigned long scl_rate;
509 struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
511 if(msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
512 scl_rate = msgs[0].scl_rate;
513 else if(msgs[0].scl_rate > 400000){
514 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too high!",
515 msgs[0].addr, msgs[0].scl_rate/1000);
519 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too low!",
520 msgs[0].addr, msgs[0].scl_rate/1000);
523 if(i2c->is_div_from_arm[i2c->adap.nr]){
524 mutex_lock(&i2c->m_lock);
525 wake_lock(&i2c->idlelock[i2c->adap.nr]);
528 rk30_i2c_set_clk(i2c, scl_rate);
529 i2c_dbg(i2c->dev, "i2c transfer start: addr: 0x%x, scl_reate: %ldKhz, len: %d\n", msgs[0].addr, scl_rate/1000, num);
530 ret = rk30_i2c_doxfer(i2c, msgs, num);
531 i2c_dbg(i2c->dev, "i2c transfer stop: addr: 0x%x, state: %d, ret: %d\n", msgs[0].addr, ret, i2c->state);
533 if(i2c->is_div_from_arm[i2c->adap.nr]){
534 wake_unlock(&i2c->idlelock[i2c->adap.nr]);
535 mutex_unlock(&i2c->m_lock);
537 return (ret < 0)?ret:num;
540 /* declare our i2c functionality */
541 static u32 rk30_i2c_func(struct i2c_adapter *adap)
543 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
546 /* i2c bus registration info */
548 static const struct i2c_algorithm rk30_i2c_algorithm = {
549 .master_xfer = rk30_i2c_xfer,
550 .functionality = rk30_i2c_func,
553 int i2c_add_rk30_adapter(struct i2c_adapter *adap)
556 struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
558 adap->algo = &rk30_i2c_algorithm;
560 i2c->i2c_init_hw = &rk30_i2c_init_hw;
561 i2c->i2c_set_clk = &rk30_i2c_set_clk;
562 i2c->i2c_irq = &rk30_i2c_irq;
564 ret = i2c_add_numbered_adapter(adap);