drivers/i2c/busses/i2c-rk30-adapter.c

   1 /* drivers/i2c/busses/i2c-rk30-adapter.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include "i2c-rk30.h"
  16
  17 /* Control register */
  18 #define I2C_CON                 0x000
  19 #define I2C_CON_EN              (1 << 0)
  20 #define I2C_CON_MOD(mod)        ((mod) << 1)
  21 #define I2C_CON_MASK            (3 << 1)
  22 enum{
  23     I2C_CON_MOD_TX = 0,
  24     I2C_CON_MOD_TRX,
  25     I2C_CON_MOD_RX,
  26     I2C_CON_MOD_RRX,
  27 };
  28 #define I2C_CON_START           (1 << 3)
  29 #define I2C_CON_STOP            (1 << 4)
  30 #define I2C_CON_LASTACK         (1 << 5)
  31 #define I2C_CON_ACTACK          (1 << 6)
  32
  33 /* Clock dividor register */
  34 #define I2C_CLKDIV              0x004
  35 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
  36
  37 /* the slave address accessed  for master rx mode */
  38 #define I2C_MRXADDR             0x008
  39 #define I2C_MRXADDR_LOW         (1 << 24)
  40 #define I2C_MRXADDR_MID         (1 << 25)
  41 #define I2C_MRXADDR_HIGH        (1 << 26)
  42
  43 /* the slave register address accessed  for master rx mode */
  44 #define I2C_MRXRADDR            0x00c
  45 #define I2C_MRXRADDR_LOW        (1 << 24)
  46 #define I2C_MRXRADDR_MID        (1 << 25)
  47 #define I2C_MRXRADDR_HIGH       (1 << 26)
  48
  49 /* master tx count */
  50 #define I2C_MTXCNT              0x010
  51
  52 /* master rx count */
  53 #define I2C_MRXCNT              0x014
  54
  55 /* interrupt enable register */
  56 #define I2C_IEN                 0x018
  57 #define I2C_BTFIEN              (1 << 0)
  58 #define I2C_BRFIEN              (1 << 1)
  59 #define I2C_MBTFIEN             (1 << 2)
  60 #define I2C_MBRFIEN             (1 << 3)
  61 #define I2C_STARTIEN            (1 << 4)
  62 #define I2C_STOPIEN             (1 << 5)
  63 #define I2C_NAKRCVIEN           (1 << 6)
  64 #define IRQ_MST_ENABLE          (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
  65 #define IRQ_ALL_DISABLE         0
  66
  67 /* interrupt pending register */
  68 #define I2C_IPD                 0x01c
  69 #define I2C_BTFIPD              (1 << 0)
  70 #define I2C_BRFIPD              (1 << 1)
  71 #define I2C_MBTFIPD             (1 << 2)
  72 #define I2C_MBRFIPD             (1 << 3)
  73 #define I2C_STARTIPD            (1 << 4)
  74 #define I2C_STOPIPD             (1 << 5)
  75 #define I2C_NAKRCVIPD           (1 << 6)
  76 #define I2C_IPD_ALL_CLEAN       0x7f
  77
  78 /* finished count */
  79 #define I2C_FCNT                0x020
  80
  81 /* I2C tx data register */
  82 #define I2C_TXDATA_BASE         0X100
  83
  84 /* I2C rx data register */
  85 #define I2C_RXDATA_BASE         0x200
  86
  87
  88 static void rk30_show_regs(struct rk30_i2c *i2c)
  89 {
  90         int i;
  91         i2c_dbg(i2c->dev, "i2c->start = %d\n", i2c->state);
  92         i2c_dbg(i2c->dev, "I2C_CON: 0x%08x\n", i2c_readl(i2c->regs + I2C_CON));
  93         i2c_dbg(i2c->dev, "I2C_CLKDIV: 0x%08x\n", i2c_readl(i2c->regs + I2C_CLKDIV));
  94         i2c_dbg(i2c->dev, "I2C_MRXADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXADDR));
  95         i2c_dbg(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXRADDR));
  96         i2c_dbg(i2c->dev, "I2C_MTXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MTXCNT));
  97         i2c_dbg(i2c->dev, "I2C_MRXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXCNT));
  98         i2c_dbg(i2c->dev, "I2C_IEN: 0x%08x\n", i2c_readl(i2c->regs + I2C_IEN));
  99         i2c_dbg(i2c->dev, "I2C_IPD: 0x%08x\n", i2c_readl(i2c->regs + I2C_IPD));
 100         i2c_dbg(i2c->dev, "I2C_FCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_FCNT));
 101         for( i = 0; i < 8; i ++)
 102                 i2c_dbg(i2c->dev, "I2C_TXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_TXDATA_BASE + i * 4));
 103         for( i = 0; i < 8; i ++)
 104                 i2c_dbg(i2c->dev, "I2C_RXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_RXDATA_BASE + i * 4));
 105 }
 106 static inline void rk30_i2c_enable(struct rk30_i2c *i2c, unsigned int lastnak)
 107 {
 108         unsigned int con = 0;
 109
 110         con |= I2C_CON_EN;
 111         con |= I2C_CON_MOD(i2c->mode);
 112         if(lastnak)
 113                 con |= I2C_CON_LASTACK;
 114         con |= I2C_CON_START;
 115         i2c_writel(con, i2c->regs + I2C_CON);
 116 }
 117 static inline void rk30_i2c_disable(struct rk30_i2c *i2c)
 118 {
 119         i2c_writel( 0, i2c->regs + I2C_CON);
 120 }
 121
 122 static inline void rk30_i2c_clean_start(struct rk30_i2c *i2c)
 123 {
 124         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 125
 126         con &= ~I2C_CON_START;
 127         i2c_writel(con, i2c->regs + I2C_CON);
 128 }
 129 static inline void rk30_i2c_send_start(struct rk30_i2c *i2c)
 130 {
 131         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 132
 133         con |= I2C_CON_START;
 134         if(con & I2C_CON_STOP)
 135                 dev_warn(i2c->dev, "I2C_CON: stop bit is set\n");
 136
 137         i2c_writel(con, i2c->regs + I2C_CON);
 138 }
 139 static inline void rk30_i2c_send_stop(struct rk30_i2c *i2c)
 140 {
 141         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 142
 143         con |= I2C_CON_STOP;
 144         if(con & I2C_CON_START)
 145                 dev_warn(i2c->dev, "I2C_CON: start bit is set\n");
 146
 147         i2c_writel(con, i2c->regs + I2C_CON);
 148 }
 149 static inline void rk30_i2c_clean_stop(struct rk30_i2c *i2c)
 150 {
 151         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 152
 153         con &= ~I2C_CON_STOP;
 154         i2c_writel(con, i2c->regs + I2C_CON);
 155 }
 156
 157 static inline void rk30_i2c_disable_irq(struct rk30_i2c *i2c)
 158 {
 159         i2c_writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
 160 }
 161
 162 static inline void rk30_i2c_enable_irq(struct rk30_i2c *i2c)
 163 {
 164         i2c_writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
 165 }
 166
 167 /* SCL Divisor = 8 * (CLKDIVL + CLKDIVH)
 168  * SCL = i2c_rate/ SCLK Divisor
 169 */
 170 static void  rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
 171 {
 172         unsigned long i2c_rate = clk_get_rate(i2c->clk);
 173
 174         unsigned int div, divl, divh;
 175
 176         if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
 177                 return;
 178         i2c->i2c_rate = i2c_rate;
 179         i2c->scl_rate = scl_rate;
 180         div = rk30_ceil(i2c_rate, scl_rate * 8);
 181         divh = divl = rk30_ceil(div, 2);
 182         i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
 183         i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV));
 184         return;
 185 }
 186 static void rk30_i2c_init_hw(struct rk30_i2c *i2c, unsigned long scl_rate)
 187 {
 188         i2c->scl_rate = 0;
 189         rk30_i2c_set_clk(i2c, scl_rate);
 190         return;
 191 }
 192 /* returns TRUE if we this is the last byte in the current message */
 193 static inline int is_msglast(struct rk30_i2c *i2c)
 194 {
 195         return i2c->msg_ptr == i2c->msg->len-1;
 196 }
 197
 198 /* returns TRUE if we reached the end of the current message */
 199 static inline int is_msgend(struct rk30_i2c *i2c)
 200 {
 201         return i2c->msg_ptr >= i2c->msg->len;
 202 }
 203
 204 static void rk30_i2c_stop(struct rk30_i2c *i2c, int ret)
 205 {
 206
 207     i2c->msg_ptr = 0;
 208         i2c->msg = NULL;
 209         i2c->msg_num = 0;
 210         if (ret)
 211                 i2c->msg_idx = ret;
 212         i2c_writel(I2C_STOPIEN, i2c->regs + I2C_IEN);
 213         i2c->state = STATE_STOP;
 214         rk30_i2c_send_stop(i2c);
 215 }
 216 static inline void rk30_set_rx_mode(struct rk30_i2c *i2c, unsigned int lastnak)
 217 {
 218         unsigned long con = i2c_readl(i2c->regs + I2C_CON);
 219
 220         con &= (~I2C_CON_MASK);
 221         con |= (I2C_CON_MOD_RX << 1);
 222         if(lastnak)
 223                 con |= I2C_CON_LASTACK;
 224         i2c_writel(con, i2c->regs + I2C_CON);
 225 }
 226 static void rk30_irq_read_prepare(struct rk30_i2c *i2c)
 227 {
 228     unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
 229
 230     if(len <= 32 && i2c->msg_ptr != 0)
 231             rk30_set_rx_mode(i2c, 1);
 232     else if(i2c->msg_ptr != 0)
 233             rk30_set_rx_mode(i2c, 0);
 234
 235     if(is_msgend(i2c)) {
 236         rk30_i2c_stop(i2c, 0);
 237         return;
 238     }
 239     if(len > 32)
 240         cnt = 32;
 241     else
 242         cnt = len;
 243     i2c_writel(cnt, i2c->regs + I2C_MRXCNT);
 244 }
 245 static void rk30_irq_read_get_data(struct rk30_i2c *i2c)
 246 {
 247      unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
 248      unsigned int p;
 249
 250      len = (len >= 32)?32:len;
 251
 252      for(i = 0; i < len; i++){
 253          if(i%4 == 0)
 254              p = i2c_readl(i2c->regs + I2C_RXDATA_BASE +  (i/4) * 4);
 255          i2c->msg->buf[i2c->msg_ptr++] = (p >>((i%4) * 8)) & 0xff;
 256     }
 257
 258      return;
 259 }
 260 static void rk30_irq_write_prepare(struct rk30_i2c *i2c)
 261 {
 262     unsigned int data = 0, cnt = 0, i, j;
 263     unsigned char byte;
 264
 265     if(is_msgend(i2c)) {
 266         rk30_i2c_stop(i2c, 0);
 267         return;
 268     }
 269     for(i = 0; i < 8; i++){
 270         data = 0;
 271         for(j = 0; j < 4; j++) {
 272             if(is_msgend(i2c))
 273                 break;
 274             if(i2c->msg_ptr == 0 && cnt == 0)
 275                 byte = (i2c->addr & 0x7f) << 1;
 276             else
 277                 byte =  i2c->msg->buf[i2c->msg_ptr++];
 278             cnt++;
 279             data |= (byte << (j * 8));
 280         }
 281         i2c_writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
 282         if(is_msgend(i2c))
 283             break;
 284     }
 285     i2c_writel(cnt, i2c->regs + I2C_MTXCNT);
 286 }
 287 static void rk30_i2c_irq_nextblock(struct rk30_i2c *i2c, unsigned int ipd)
 288 {
 289         switch (i2c->state) {
 290         case STATE_IDLE:
 291                 dev_err(i2c->dev, "Addr[0x%02x] called in STATE_IDLE\n", i2c->addr);
 292                 rk30_show_regs(i2c);
 293                 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 294                 goto out;
 295         case STATE_START:
 296                 if(!(ipd & I2C_STARTIPD)){
 297                         rk30_i2c_stop(i2c, -ENXIO);
 298                         dev_err(i2c->dev, "Addr[0x%02x] no start irq in STATE_START\n", i2c->addr);
 299                         rk30_show_regs(i2c);
 300                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 301                         goto out;
 302                 }
 303
 304                 i2c_writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
 305                 rk30_i2c_clean_start(i2c);
 306                 if(i2c->mode ==  I2C_CON_MOD_TX){
 307                         i2c_writel(I2C_MBTFIEN  | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
 308                         i2c->state = STATE_WRITE;
 309                         goto prepare_write;
 310                 } else {
 311                         i2c_writel(I2C_MBRFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
 312                         i2c->state = STATE_READ;
 313                         goto prepare_read;
 314                 }
 315         case STATE_WRITE:
 316                 if(!(ipd & I2C_MBTFIPD)){
 317                         rk30_i2c_stop(i2c, -ENXIO);
 318                         dev_err(i2c->dev, "Addr[0x%02x] no mbtf irq in STATE_WRITE\n", i2c->addr);
 319                         rk30_show_regs(i2c);
 320                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 321                         goto out;
 322                 }
 323                 i2c_writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
 324 prepare_write:
 325                 rk30_irq_write_prepare(i2c);
 326                 break;
 327         case STATE_READ:
 328                 if(!(ipd & I2C_MBRFIPD)){
 329                         rk30_i2c_stop(i2c, -ENXIO);
 330                         dev_err(i2c->dev, "Addr[0x%02x] no mbrf irq in STATE_READ\n", i2c->addr);
 331                         rk30_show_regs(i2c);
 332                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 333                         goto out;
 334                 }
 335                 i2c_writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
 336                 rk30_irq_read_get_data(i2c);
 337 prepare_read:
 338                 rk30_irq_read_prepare(i2c);
 339                 break;
 340         case STATE_STOP:
 341                 if(!(ipd & I2C_STOPIPD)){
 342                         rk30_i2c_stop(i2c, -ENXIO);
 343                         dev_err(i2c->dev, "Addr[0x%02x] no stop irq in STATE_STOP\n", i2c->addr);
 344                         rk30_show_regs(i2c);
 345                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 346                         goto out;
 347                 }
 348                 rk30_i2c_clean_stop(i2c);
 349                 i2c_writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
 350                 i2c->state = STATE_IDLE;
 351                 wake_up(&i2c->wait);
 352                 break;
 353         default:
 354                 break;
 355         }
 356 out:
 357         return;
 358 }
 359 static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
 360 {
 361         struct rk30_i2c *i2c = dev_id;
 362         unsigned int ipd;
 363
 364         spin_lock(&i2c->lock);
 365         ipd = i2c_readl(i2c->regs + I2C_IPD);
 366 #if 1
 367         if((ipd & I2C_NAKRCVIPD)  && (i2c->state != STATE_STOP)){
 368                 dev_err(i2c->dev, "Addr[0x%02x] ack was not received\n", i2c->addr);
 369                 rk30_show_regs(i2c);
 370                 i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
 371                 rk30_i2c_stop(i2c, -EAGAIN);
 372                 goto out;
 373         }
 374 #endif
 375         rk30_i2c_irq_nextblock(i2c, ipd);
 376 out:
 377         spin_unlock(&i2c->lock);
 378         return IRQ_HANDLED;
 379 }
 380
 381
 382 static int rk30_i2c_set_master(struct rk30_i2c *i2c, struct i2c_msg *msgs, int num)
 383 {
 384         unsigned int addr = (msgs[0].addr & 0x7f) << 1;
 385         unsigned int reg_valid_bits = 0;
 386         unsigned int reg_addr = 0;
 387
 388         if(num == 1) {
 389                 i2c->count = msgs[0].len;
 390                 if(!(msgs[0].flags & I2C_M_RD)){
 391                         i2c->msg = &msgs[0];
 392                         i2c->mode = I2C_CON_MOD_TX;
 393                 }
 394                 else {
 395                         addr |= 1;
 396                         i2c->msg = &msgs[0];
 397                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 398                         i2c->mode = I2C_CON_MOD_RX;
 399                 }
 400         }
 401         else if(num == 2) {
 402                 i2c->count = msgs[1].len;
 403                 switch(msgs[0].len){
 404                 case 1:
 405                         reg_addr = msgs[0].buf[0];
 406                         reg_valid_bits |= I2C_MRXADDR_LOW;
 407                         break;
 408                 case 2:
 409                         reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
 410                         reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
 411                         break;
 412                 case 3:
 413                         reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
 414                         reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
 415                         break;
 416                 default:
 417                         return -EIO;
 418                 }
 419                 if((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 420                         addr |= 1;
 421                         i2c->msg = &msgs[1];
 422                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 423                         i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 424                         i2c->mode = I2C_CON_MOD_RRX;
 425                 }
 426                 else if(!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 427                         i2c->msg = &msgs[1];
 428                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 429                         i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 430                         i2c->mode = I2C_CON_MOD_TRX;
 431                 }
 432                 else
 433                         return -EIO;
 434         }
 435         else {
 436                 dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
 437                 return -EIO;
 438         }
 439
 440         return 0;
 441 }
 442 /* rk30_i2c_doxfer
 443  *
 444  * this starts an i2c transfer
 445 */
 446 static int rk30_i2c_doxfer(struct rk30_i2c *i2c,
 447                               struct i2c_msg *msgs, int num)
 448 {
 449         unsigned long timeout;
 450         int ret = 0;
 451
 452         if (i2c->suspended)
 453                 return -EIO;
 454
 455         ret = rk30_i2c_set_master(i2c, msgs, num);
 456         if (ret != 0) {
 457                 dev_err(i2c->dev, "addr[0x%02x] set master error\n", msgs[0].addr);
 458                 return ret;
 459         }
 460         spin_lock_irq(&i2c->lock);
 461
 462         i2c->addr = msgs[0].addr;
 463         i2c->msg_num = num;
 464         i2c->msg_ptr = 0;
 465         i2c->msg_idx = num;
 466         i2c->state = STATE_START;
 467
 468         spin_unlock_irq(&i2c->lock);
 469
 470         i2c_writel(I2C_STARTIEN, i2c->regs + I2C_IEN);
 471         rk30_i2c_enable(i2c, (i2c->count > 32)?0:1); //if count > 32,  byte(32) send ack
 472         //rk30_i2c_enable_irq(i2c);
 473         //rk30_i2c_send_start(i2c);
 474
 475         timeout = wait_event_timeout(i2c->wait, (i2c->msg_num == 0), msecs_to_jiffies(I2C_WAIT_TIMEOUT));
 476
 477         ret = i2c->msg_idx;
 478
 479         if (timeout == 0){
 480                 dev_err(i2c->dev, "addr[0x%02x] wait event timeout, state = %d\n", msgs[0].addr, i2c->state);
 481                 rk30_show_regs(i2c);
 482                 if(i2c->state != STATE_STOP)
 483                         rk30_i2c_send_stop(i2c);
 484                 ret = -ETIMEDOUT;
 485         }
 486         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 487         rk30_i2c_disable_irq(i2c);
 488         rk30_i2c_disable(i2c);
 489         i2c_dbg(i2c->dev, "i2c transfer finished ret = %d\n", ret);
 490         return ret;
 491 }
 492
 493 /* rk30_i2c_xfer
 494  *
 495  * first port of call from the i2c bus code when an message needs
 496  * transferring across the i2c bus.
 497 */
 498
 499 static int rk30_i2c_xfer(struct i2c_adapter *adap,
 500                         struct i2c_msg *msgs, int num)
 501 {
 502         int ret = 0;
 503         unsigned long scl_rate;
 504         struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 505
 506         if(msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
 507                 scl_rate = msgs[0].scl_rate;
 508         else if(msgs[0].scl_rate > 400000){
 509                 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too high!",
 510                         msgs[0].addr, msgs[0].scl_rate/1000);
 511                 scl_rate = 400000;
 512         }
 513         else{
 514                 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too low!",
 515                         msgs[0].addr, msgs[0].scl_rate/1000);
 516                 scl_rate = 10000;
 517         }
 518         if(i2c->is_div_from_arm[i2c->adap.nr])
 519                 wake_lock(&i2c->idlelock[i2c->adap.nr]);
 520
 521         rk30_i2c_set_clk(i2c, scl_rate);
 522         udelay(i2c->tx_setup);
 523         i2c_dbg(i2c->dev, "i2c transfer: addr[0x%x], scl_reate[%ldKhz], len = %d\n", msgs[0].addr, scl_rate/1000, i2c->count);
 524         ret = rk30_i2c_doxfer(i2c, msgs, num);
 525
 526         i2c->state = STATE_IDLE;
 527         if(i2c->is_div_from_arm[i2c->adap.nr])
 528                 wake_unlock(&i2c->idlelock[i2c->adap.nr]);
 529         return ret;
 530 }
 531
 532 /* declare our i2c functionality */
 533 static u32 rk30_i2c_func(struct i2c_adapter *adap)
 534 {
 535         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 536 }
 537
 538 /* i2c bus registration info */
 539
 540 static const struct i2c_algorithm rk30_i2c_algorithm = {
 541         .master_xfer            = rk30_i2c_xfer,
 542         .functionality          = rk30_i2c_func,
 543 };
 544
 545 int i2c_add_rk30_adapter(struct i2c_adapter *adap)
 546 {
 547         int ret = 0;
 548         struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 549
 550         adap->algo = &rk30_i2c_algorithm;
 551
 552         i2c->i2c_init_hw = &rk30_i2c_init_hw;
 553         i2c->i2c_set_clk = &rk30_i2c_set_clk;
 554         i2c->i2c_irq = &rk30_i2c_irq;
 555
 556         ret = i2c_add_numbered_adapter(adap);
 557
 558         return ret;
 559 }
 560