1 /* drivers/i2c/busses/i2c-rk30-adapter.c
3 * Copyright (C) 2012 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #define COMPLETE_READ (1<<STATE_START|1<<STATE_READ|1<<STATE_STOP)
18 #define COMPLETE_WRITE (1<<STATE_START|1<<STATE_WRITE|1<<STATE_STOP)
20 /* Control register */
22 #define I2C_CON_EN (1 << 0)
23 #define I2C_CON_MOD(mod) ((mod) << 1)
24 #define I2C_CON_MASK (3 << 1)
31 #define I2C_CON_START (1 << 3)
32 #define I2C_CON_STOP (1 << 4)
33 #define I2C_CON_LASTACK (1 << 5)
34 #define I2C_CON_ACTACK (1 << 6)
36 /* Clock dividor register */
37 #define I2C_CLKDIV 0x004
38 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
40 /* the slave address accessed for master rx mode */
41 #define I2C_MRXADDR 0x008
42 #define I2C_MRXADDR_LOW (1 << 24)
43 #define I2C_MRXADDR_MID (1 << 25)
44 #define I2C_MRXADDR_HIGH (1 << 26)
46 /* the slave register address accessed for master rx mode */
47 #define I2C_MRXRADDR 0x00c
48 #define I2C_MRXRADDR_LOW (1 << 24)
49 #define I2C_MRXRADDR_MID (1 << 25)
50 #define I2C_MRXRADDR_HIGH (1 << 26)
53 #define I2C_MTXCNT 0x010
56 #define I2C_MRXCNT 0x014
58 /* interrupt enable register */
60 #define I2C_BTFIEN (1 << 0)
61 #define I2C_BRFIEN (1 << 1)
62 #define I2C_MBTFIEN (1 << 2)
63 #define I2C_MBRFIEN (1 << 3)
64 #define I2C_STARTIEN (1 << 4)
65 #define I2C_STOPIEN (1 << 5)
66 #define I2C_NAKRCVIEN (1 << 6)
67 #define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
68 #define IRQ_ALL_DISABLE 0
70 /* interrupt pending register */
72 #define I2C_BTFIPD (1 << 0)
73 #define I2C_BRFIPD (1 << 1)
74 #define I2C_MBTFIPD (1 << 2)
75 #define I2C_MBRFIPD (1 << 3)
76 #define I2C_STARTIPD (1 << 4)
77 #define I2C_STOPIPD (1 << 5)
78 #define I2C_NAKRCVIPD (1 << 6)
80 #define I2C_HOLD_SCL (1 << 7)
81 #define I2C_IPD_ALL_CLEAN 0x7f
84 #define I2C_FCNT 0x020
86 /* I2C tx data register */
87 #define I2C_TXDATA_BASE 0X100
89 /* I2C rx data register */
90 #define I2C_RXDATA_BASE 0x200
93 static void rk30_show_regs(struct rk30_i2c *i2c)
96 dev_info(i2c->dev, "i2c->clk = %lu\n", clk_get_rate(i2c->clk));
97 dev_info(i2c->dev, "i2c->start = %d\n", i2c->state);
98 dev_info(i2c->dev, "I2C_CON: 0x%08x\n", i2c_readl(i2c->regs + I2C_CON));
99 dev_info(i2c->dev, "I2C_CLKDIV: 0x%08x\n", i2c_readl(i2c->regs + I2C_CLKDIV));
100 dev_info(i2c->dev, "I2C_MRXADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXADDR));
101 dev_info(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXRADDR));
102 dev_info(i2c->dev, "I2C_MTXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MTXCNT));
103 dev_info(i2c->dev, "I2C_MRXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXCNT));
104 dev_info(i2c->dev, "I2C_IEN: 0x%08x\n", i2c_readl(i2c->regs + I2C_IEN));
105 dev_info(i2c->dev, "I2C_IPD: 0x%08x\n", i2c_readl(i2c->regs + I2C_IPD));
106 dev_info(i2c->dev, "I2C_FCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_FCNT));
107 for( i = 0; i < 8; i ++)
108 dev_info(i2c->dev, "I2C_TXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_TXDATA_BASE + i * 4));
109 for( i = 0; i < 8; i ++)
110 dev_info(i2c->dev, "I2C_RXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_RXDATA_BASE + i * 4));
113 static int rk30_i2c_check_idle(struct rk30_i2c *i2c)
117 int sda_lev, scl_lev;
119 sda_io = iomux_mode_to_gpio(i2c->sda_mode);
120 scl_io = iomux_mode_to_gpio(i2c->scl_mode);
122 ret = gpio_request(sda_io, NULL);
123 if(unlikely(ret < 0)){
124 dev_err(i2c->dev, "Failed to request gpio: SDA_GPIO\n");
127 ret = gpio_request(scl_io, NULL);
128 if(unlikely(ret < 0)){
129 dev_err(i2c->dev, "Failed to request gpio: SCL_GPIO\n");
133 gpio_direction_input(sda_io);
134 gpio_direction_input(scl_io);
136 sda_lev = gpio_get_value(sda_io);
137 scl_lev = gpio_get_value(scl_io);
142 iomux_set(i2c->sda_mode);
143 iomux_set(i2c->scl_mode);
145 if(sda_lev == 1 && scl_lev == 1)
147 else if(sda_lev == 0 && scl_lev == 1)
149 else if(sda_lev == 1 && scl_lev == 0)
154 static inline void rk30_i2c_enable(struct rk30_i2c *i2c, unsigned int lastnak)
156 unsigned int con = 0;
159 con |= I2C_CON_MOD(i2c->mode);
161 con |= I2C_CON_LASTACK;
162 con |= I2C_CON_START;
163 i2c_writel(con, i2c->regs + I2C_CON);
165 static inline void rk30_i2c_disable(struct rk30_i2c *i2c)
167 i2c_writel( 0, i2c->regs + I2C_CON);
170 static inline void rk30_i2c_clean_start(struct rk30_i2c *i2c)
172 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
174 con &= ~I2C_CON_START;
175 i2c_writel(con, i2c->regs + I2C_CON);
177 static inline void rk30_i2c_send_start(struct rk30_i2c *i2c)
179 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
181 con |= I2C_CON_START;
182 if(con & I2C_CON_STOP)
183 dev_warn(i2c->dev, "I2C_CON: stop bit is set\n");
185 i2c_writel(con, i2c->regs + I2C_CON);
187 static inline void rk30_i2c_send_stop(struct rk30_i2c *i2c)
189 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
192 if(con & I2C_CON_START)
193 dev_warn(i2c->dev, "I2C_CON: start bit is set\n");
195 i2c_writel(con, i2c->regs + I2C_CON);
197 static inline void rk30_i2c_clean_stop(struct rk30_i2c *i2c)
199 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
201 con &= ~I2C_CON_STOP;
202 i2c_writel(con, i2c->regs + I2C_CON);
205 static inline void rk30_i2c_disable_irq(struct rk30_i2c *i2c)
207 i2c_writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
210 static inline void rk30_i2c_enable_irq(struct rk30_i2c *i2c)
212 i2c_writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
214 static void rk30_get_div(int div, int *divh, int *divl)
220 *divh = rk30_ceil(div, 2);
224 /* SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
225 * SCL = i2c_rate/ SCLK Divisor
227 static void rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
229 unsigned long i2c_rate = clk_get_rate(i2c->clk);
233 if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
235 i2c->i2c_rate = i2c_rate;
236 i2c->scl_rate = scl_rate;
237 div = rk30_ceil(i2c_rate, (scl_rate * 8)) - 2;
238 if(unlikely(div < 0)){
239 dev_warn(i2c->dev, "Divisor(%d) is negative, set divl = divh = 0\n", div);
242 rk30_get_div(div, &divh, &divl);
244 i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
245 i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV));
248 static void rk30_i2c_init_hw(struct rk30_i2c *i2c, unsigned long scl_rate)
251 rk30_i2c_set_clk(i2c, scl_rate);
254 /* returns TRUE if we this is the last byte in the current message */
255 static inline int is_msglast(struct rk30_i2c *i2c)
257 return i2c->msg_ptr == i2c->msg->len-1;
260 /* returns TRUE if we reached the end of the current message */
261 static inline int is_msgend(struct rk30_i2c *i2c)
263 return i2c->msg_ptr >= i2c->msg->len;
266 static void rk30_i2c_stop(struct rk30_i2c *i2c, int ret)
272 i2c->state = STATE_IDLE;
278 i2c_writel(I2C_STOPIEN, i2c->regs + I2C_IEN);
279 i2c->state = STATE_STOP;
280 rk30_i2c_send_stop(i2c);
283 static inline void rk30_set_rx_mode(struct rk30_i2c *i2c, unsigned int lastnak)
285 unsigned long con = i2c_readl(i2c->regs + I2C_CON);
287 con &= (~I2C_CON_MASK);
288 con |= (I2C_CON_MOD_RX << 1);
290 con |= I2C_CON_LASTACK;
291 i2c_writel(con, i2c->regs + I2C_CON);
293 static void rk30_irq_read_prepare(struct rk30_i2c *i2c)
295 unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
297 if(len <= 32 && i2c->msg_ptr != 0)
298 rk30_set_rx_mode(i2c, 1);
299 else if(i2c->msg_ptr != 0)
300 rk30_set_rx_mode(i2c, 0);
303 rk30_i2c_stop(i2c, i2c->error);
310 i2c_writel(cnt, i2c->regs + I2C_MRXCNT);
312 static void rk30_irq_read_get_data(struct rk30_i2c *i2c)
314 unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
317 len = (len >= 32)?32:len;
319 for(i = 0; i < len; i++){
321 p = i2c_readl(i2c->regs + I2C_RXDATA_BASE + (i/4) * 4);
322 i2c->msg->buf[i2c->msg_ptr++] = (p >>((i%4) * 8)) & 0xff;
327 static void rk30_irq_write_prepare(struct rk30_i2c *i2c)
329 unsigned int data = 0, cnt = 0, i, j;
333 rk30_i2c_stop(i2c, i2c->error);
336 for(i = 0; i < 8; i++){
338 for(j = 0; j < 4; j++) {
341 if((i2c->msg_ptr == 0) && (cnt == 0))
342 byte = (i2c->addr_1st & 0x7f) << 1;
343 else if((i2c->msg_ptr == 0) && (cnt == 1) && (i2c->msg->flags & I2C_M_TEN))
344 byte = i2c->addr_2nd;
346 byte = i2c->msg->buf[i2c->msg_ptr++];
348 data |= (byte << (j * 8));
350 i2c_writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
354 i2c_writel(cnt, i2c->regs + I2C_MTXCNT);
356 static void rk30_i2c_irq_nextblock(struct rk30_i2c *i2c, unsigned int ipd)
358 switch (i2c->state) {
360 if(!(ipd & I2C_STARTIPD)){
361 rk30_i2c_stop(i2c, -ENXIO);
362 dev_err(i2c->dev, "Addr[0x%04x] no start irq in STATE_START\n", i2c->addr);
364 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
367 i2c->complete_what |= 1<<i2c->state;
368 i2c_writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
369 rk30_i2c_clean_start(i2c);
370 if(i2c->mode == I2C_CON_MOD_TX){
371 i2c_writel(I2C_MBTFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
372 i2c->state = STATE_WRITE;
375 i2c_writel(I2C_MBRFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
376 i2c->state = STATE_READ;
380 if(!(ipd & I2C_MBTFIPD)){
381 rk30_i2c_stop(i2c, -ENXIO);
382 dev_err(i2c->dev, "Addr[0x%04x] no mbtf irq in STATE_WRITE\n", i2c->addr);
384 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
387 i2c->complete_what |= 1<<i2c->state;
388 i2c_writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
390 rk30_irq_write_prepare(i2c);
393 if(!(ipd & I2C_MBRFIPD)){
394 rk30_i2c_stop(i2c, -ENXIO);
395 dev_err(i2c->dev, "Addr[0x%04x] no mbrf irq in STATE_READ, ipd = 0x%x\n", i2c->addr, ipd);
397 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
400 i2c->complete_what |= 1<<i2c->state;
401 i2c_writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
402 rk30_irq_read_get_data(i2c);
404 rk30_irq_read_prepare(i2c);
407 if(!(ipd & I2C_STOPIPD)){
408 rk30_i2c_stop(i2c, -ENXIO);
409 dev_err(i2c->dev, "Addr[0x%04x] no stop irq in STATE_STOP\n", i2c->addr);
411 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
414 rk30_i2c_clean_stop(i2c);
415 i2c_writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
417 i2c->complete_what |= 1<<i2c->state;
418 i2c->state = STATE_IDLE;
427 static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
429 struct rk30_i2c *i2c = dev_id;
432 spin_lock(&i2c->lock);
433 ipd = i2c_readl(i2c->regs + I2C_IPD);
434 if(i2c->state == STATE_IDLE){
435 dev_info(i2c->dev, "Addr[0x%04x] irq in STATE_IDLE, ipd = 0x%x\n", i2c->addr, ipd);
436 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
440 if(ipd & I2C_NAKRCVIPD){
441 i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
442 i2c->error = -EAGAIN;
445 rk30_i2c_irq_nextblock(i2c, ipd);
447 spin_unlock(&i2c->lock);
452 static int rk30_i2c_set_master(struct rk30_i2c *i2c, struct i2c_msg *msgs, int num)
454 unsigned int reg_valid_bits = 0;
455 unsigned int reg_addr = 0;
456 unsigned int addr = (i2c->addr_1st << 1) | 1;
459 i2c->count = msgs[0].len;
460 if(!(msgs[0].flags & I2C_M_RD)){
462 i2c->mode = I2C_CON_MOD_TX;
466 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
467 i2c_writel(0, i2c->regs + I2C_MRXRADDR);
468 i2c->mode = I2C_CON_MOD_TRX;
469 //i2c->mode = I2C_CON_MOD_RX;
473 i2c->count = msgs[1].len;
475 if(msgs[0].flags & I2C_M_TEN){
478 reg_addr = i2c->addr_2nd | (msgs[0].buf[0] << 8);
479 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
482 reg_addr = i2c->addr_2nd | (msgs[0].buf[0] << 8) | (msgs[0].buf[1] << 16);
483 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
491 reg_addr = msgs[0].buf[0];
492 reg_valid_bits |= I2C_MRXADDR_LOW;
495 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
496 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
499 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
500 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
506 if((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
508 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
509 i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
510 i2c->mode = I2C_CON_MOD_RRX;
512 else if(!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
514 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
515 i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
516 i2c->mode = I2C_CON_MOD_TRX;
522 dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
530 * this starts an i2c transfer
532 static int rk30_i2c_doxfer(struct rk30_i2c *i2c,
533 struct i2c_msg *msgs, int num)
535 unsigned long timeout, flags;
537 /* 32 -- max transfer bytes
538 * 2 -- addr bytes * 2
539 * 3 -- max reg addr bytes
540 * 9 -- cycles per bytes
541 * max cycles: (32 + 2 + 3) * 9 --> 400 cycles
543 int msleep_time = 400 * 1000/ i2c->scl_rate; // ms
546 dev_err(i2c->dev, "i2c is suspended\n");
550 spin_lock_irqsave(&i2c->lock, flags);
551 i2c->addr = msgs[0].addr;
552 if(msgs[0].flags & I2C_M_TEN){
553 i2c->addr_1st = ((i2c->addr & 0x0300)>>8) | 0x78;
554 i2c->addr_2nd = i2c->addr & 0x00ff;
556 i2c->addr_1st = i2c->addr & 0x007f;
559 i2c_dbg(i2c->dev, "addr: 0x%04x, addr_1st: 0x%02x, addr_2nd: 0x%02x\n",
560 i2c->addr, i2c->addr_1st, i2c->addr_2nd);
562 if(rk30_i2c_set_master(i2c, msgs, num) < 0){
563 spin_unlock_irqrestore(&i2c->lock, flags);
564 dev_err(i2c->dev, "addr[0x%04x] set master error\n", msgs[0].addr);
570 i2c->state = STATE_START;
571 i2c->complete_what = 0;
572 i2c_writel(I2C_STARTIEN, i2c->regs + I2C_IEN);
573 spin_unlock_irqrestore(&i2c->lock, flags);
575 rk30_i2c_enable(i2c, (i2c->count > 32)?0:1); //if count > 32, byte(32) send ack
578 int tmo = I2C_WAIT_TIMEOUT * USEC_PER_MSEC;
579 while(tmo-- && i2c->is_busy != 0)
581 timeout = (tmo <= 0)?0:1;
583 timeout = wait_event_timeout(i2c->wait, (i2c->is_busy == 0), msecs_to_jiffies(I2C_WAIT_TIMEOUT));
585 spin_lock_irqsave(&i2c->lock, flags);
586 i2c->state = STATE_IDLE;
588 spin_unlock_irqrestore(&i2c->lock, flags);
591 unsigned int ipd = i2c_readl(i2c->regs + I2C_IPD);
593 i2c_dbg(i2c->dev, "error = %d\n", error);
594 else if((i2c->complete_what !=COMPLETE_READ && i2c->complete_what != COMPLETE_WRITE)){
595 if(ipd & I2C_HOLD_SCL)
596 dev_err(i2c->dev, "SCL was hold by slave\n");
597 dev_err(i2c->dev, "Addr[0x%04x] wait event timeout, state: %d, is_busy: %d, error: %d, complete_what: 0x%x, ipd: 0x%x\n",
598 msgs[0].addr, i2c->state, i2c->is_busy, error, i2c->complete_what, ipd);
599 //rk30_show_regs(i2c);
605 rk30_i2c_send_stop(i2c);
612 i2c_dbg(i2c->dev, "Addr[0x%02x] wait event timeout, but transfer complete\n", i2c->addr);
614 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
615 rk30_i2c_disable_irq(i2c);
616 rk30_i2c_disable(i2c);
619 i2c_dbg(i2c->dev, "No ack(complete_what: 0x%x), Maybe slave(addr: 0x%04x) not exist or abnormal power-on\n",
620 i2c->complete_what, i2c->addr);
626 * first port of call from the i2c bus code when an message needs
627 * transferring across the i2c bus.
630 static int rk30_i2c_xfer(struct i2c_adapter *adap,
631 struct i2c_msg *msgs, int num)
633 int ret = 0, state, retry = 10;
634 unsigned long scl_rate;
635 struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
637 clk_enable(i2c->clk);
638 #ifdef I2C_CHECK_IDLE
639 while(retry-- && ((state = rk30_i2c_check_idle(i2c)) != I2C_IDLE)){
646 dev_err(i2c->dev, "i2c is not in idle(state = %d)\n", state);
651 if(msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
652 scl_rate = msgs[0].scl_rate;
653 else if(msgs[0].scl_rate > 400000){
654 dev_warn(i2c->dev, "Warning: addr[0x%04x] msg[0].scl_rate( = %dKhz) is too high!",
655 msgs[0].addr, msgs[0].scl_rate/1000);
659 dev_warn(i2c->dev, "Warning: addr[0x%04x] msg[0].scl_rate( = %dKhz) is too low!",
660 msgs[0].addr, msgs[0].scl_rate/1000);
663 if(i2c->is_div_from_arm[i2c->adap.nr]){
664 mutex_lock(&i2c->m_lock);
667 rk30_i2c_set_clk(i2c, scl_rate);
668 i2c_dbg(i2c->dev, "i2c transfer start: addr: 0x%04x, scl_reate: %ldKhz, len: %d\n", msgs[0].addr, scl_rate/1000, num);
669 ret = rk30_i2c_doxfer(i2c, msgs, num);
670 i2c_dbg(i2c->dev, "i2c transfer stop: addr: 0x%04x, state: %d, ret: %d\n", msgs[0].addr, ret, i2c->state);
672 if(i2c->is_div_from_arm[i2c->adap.nr]){
673 mutex_unlock(&i2c->m_lock);
676 clk_disable(i2c->clk);
677 return (ret < 0)?ret:num;
680 /* declare our i2c functionality */
681 static u32 rk30_i2c_func(struct i2c_adapter *adap)
683 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
686 /* i2c bus registration info */
688 static const struct i2c_algorithm rk30_i2c_algorithm = {
689 .master_xfer = rk30_i2c_xfer,
690 .functionality = rk30_i2c_func,
693 int i2c_add_rk30_adapter(struct i2c_adapter *adap)
696 struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
698 adap->algo = &rk30_i2c_algorithm;
700 i2c->i2c_init_hw = &rk30_i2c_init_hw;
701 i2c->i2c_set_clk = &rk30_i2c_set_clk;
702 i2c->i2c_irq = &rk30_i2c_irq;
704 ret = i2c_add_numbered_adapter(adap);