1 /* drivers/i2c/busses/i2c-rk30-adapter.c
3 * Copyright (C) 2012 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #define COMPLETE_READ (1<<STATE_START|1<<STATE_READ|1<<STATE_STOP)
18 #define COMPLETE_WRITE (1<<STATE_START|1<<STATE_WRITE|1<<STATE_STOP)
20 /* Control register */
22 #define I2C_CON_EN (1 << 0)
23 #define I2C_CON_MOD(mod) ((mod) << 1)
24 #define I2C_CON_MASK (3 << 1)
31 #define I2C_CON_START (1 << 3)
32 #define I2C_CON_STOP (1 << 4)
33 #define I2C_CON_LASTACK (1 << 5)
34 #define I2C_CON_ACTACK (1 << 6)
36 /* Clock dividor register */
37 #define I2C_CLKDIV 0x004
38 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
40 /* the slave address accessed for master rx mode */
41 #define I2C_MRXADDR 0x008
42 #define I2C_MRXADDR_LOW (1 << 24)
43 #define I2C_MRXADDR_MID (1 << 25)
44 #define I2C_MRXADDR_HIGH (1 << 26)
46 /* the slave register address accessed for master rx mode */
47 #define I2C_MRXRADDR 0x00c
48 #define I2C_MRXRADDR_LOW (1 << 24)
49 #define I2C_MRXRADDR_MID (1 << 25)
50 #define I2C_MRXRADDR_HIGH (1 << 26)
53 #define I2C_MTXCNT 0x010
56 #define I2C_MRXCNT 0x014
58 /* interrupt enable register */
60 #define I2C_BTFIEN (1 << 0)
61 #define I2C_BRFIEN (1 << 1)
62 #define I2C_MBTFIEN (1 << 2)
63 #define I2C_MBRFIEN (1 << 3)
64 #define I2C_STARTIEN (1 << 4)
65 #define I2C_STOPIEN (1 << 5)
66 #define I2C_NAKRCVIEN (1 << 6)
67 #define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
68 #define IRQ_ALL_DISABLE 0
70 /* interrupt pending register */
72 #define I2C_BTFIPD (1 << 0)
73 #define I2C_BRFIPD (1 << 1)
74 #define I2C_MBTFIPD (1 << 2)
75 #define I2C_MBRFIPD (1 << 3)
76 #define I2C_STARTIPD (1 << 4)
77 #define I2C_STOPIPD (1 << 5)
78 #define I2C_NAKRCVIPD (1 << 6)
79 #define I2C_IPD_ALL_CLEAN 0x7f
82 #define I2C_FCNT 0x020
84 /* I2C tx data register */
85 #define I2C_TXDATA_BASE 0X100
87 /* I2C rx data register */
88 #define I2C_RXDATA_BASE 0x200
91 static void rk30_show_regs(struct rk30_i2c *i2c)
94 dev_info(i2c->dev, "i2c->clk = %lu\n", clk_get_rate(i2c->clk));
95 dev_info(i2c->dev, "i2c->start = %d\n", i2c->state);
96 dev_info(i2c->dev, "I2C_CON: 0x%08x\n", i2c_readl(i2c->regs + I2C_CON));
97 dev_info(i2c->dev, "I2C_CLKDIV: 0x%08x\n", i2c_readl(i2c->regs + I2C_CLKDIV));
98 dev_info(i2c->dev, "I2C_MRXADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXADDR));
99 dev_info(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXRADDR));
100 dev_info(i2c->dev, "I2C_MTXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MTXCNT));
101 dev_info(i2c->dev, "I2C_MRXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXCNT));
102 dev_info(i2c->dev, "I2C_IEN: 0x%08x\n", i2c_readl(i2c->regs + I2C_IEN));
103 dev_info(i2c->dev, "I2C_IPD: 0x%08x\n", i2c_readl(i2c->regs + I2C_IPD));
104 dev_info(i2c->dev, "I2C_FCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_FCNT));
105 for( i = 0; i < 8; i ++)
106 dev_info(i2c->dev, "I2C_TXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_TXDATA_BASE + i * 4));
107 for( i = 0; i < 8; i ++)
108 dev_info(i2c->dev, "I2C_RXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_RXDATA_BASE + i * 4));
111 static int rk30_i2c_check_idle(struct rk30_i2c *i2c)
115 int sda_lev, scl_lev;
117 sda_io = iomux_mode_to_gpio(i2c->sda_mode);
118 scl_io = iomux_mode_to_gpio(i2c->scl_mode);
120 ret = gpio_request(sda_io, NULL);
121 if(unlikely(ret < 0)){
122 dev_err(i2c->dev, "Failed to request gpio: SDA_GPIO\n");
125 ret = gpio_request(scl_io, NULL);
126 if(unlikely(ret < 0)){
127 dev_err(i2c->dev, "Failed to request gpio: SCL_GPIO\n");
131 gpio_direction_input(sda_io);
132 gpio_direction_input(scl_io);
134 sda_lev = gpio_get_value(sda_io);
135 scl_lev = gpio_get_value(scl_io);
140 iomux_set(i2c->sda_mode);
141 iomux_set(i2c->scl_mode);
143 if(sda_lev == 1 && scl_lev == 1)
145 else if(sda_lev == 0 && scl_lev == 1)
147 else if(sda_lev == 1 && scl_lev == 0)
152 static inline void rk30_i2c_enable(struct rk30_i2c *i2c, unsigned int lastnak)
154 unsigned int con = 0;
157 con |= I2C_CON_MOD(i2c->mode);
159 con |= I2C_CON_LASTACK;
160 con |= I2C_CON_START;
161 i2c_writel(con, i2c->regs + I2C_CON);
163 static inline void rk30_i2c_disable(struct rk30_i2c *i2c)
165 i2c_writel( 0, i2c->regs + I2C_CON);
168 static inline void rk30_i2c_clean_start(struct rk30_i2c *i2c)
170 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
172 con &= ~I2C_CON_START;
173 i2c_writel(con, i2c->regs + I2C_CON);
175 static inline void rk30_i2c_send_start(struct rk30_i2c *i2c)
177 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
179 con |= I2C_CON_START;
180 if(con & I2C_CON_STOP)
181 dev_warn(i2c->dev, "I2C_CON: stop bit is set\n");
183 i2c_writel(con, i2c->regs + I2C_CON);
185 static inline void rk30_i2c_send_stop(struct rk30_i2c *i2c)
187 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
190 if(con & I2C_CON_START)
191 dev_warn(i2c->dev, "I2C_CON: start bit is set\n");
193 i2c_writel(con, i2c->regs + I2C_CON);
195 static inline void rk30_i2c_clean_stop(struct rk30_i2c *i2c)
197 unsigned int con = i2c_readl(i2c->regs + I2C_CON);
199 con &= ~I2C_CON_STOP;
200 i2c_writel(con, i2c->regs + I2C_CON);
203 static inline void rk30_i2c_disable_irq(struct rk30_i2c *i2c)
205 i2c_writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
208 static inline void rk30_i2c_enable_irq(struct rk30_i2c *i2c)
210 i2c_writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
213 /* SCL Divisor = 8 * (CLKDIVL + CLKDIVH)
214 * SCL = i2c_rate/ SCLK Divisor
216 static void rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
218 unsigned long i2c_rate = clk_get_rate(i2c->clk);
220 unsigned int div, divl, divh;
222 if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
224 i2c->i2c_rate = i2c_rate;
225 i2c->scl_rate = scl_rate;
226 div = rk30_ceil(i2c_rate, scl_rate * 8);
227 divh = divl = rk30_ceil(div, 2);
228 i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
229 i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV));
232 static void rk30_i2c_init_hw(struct rk30_i2c *i2c, unsigned long scl_rate)
235 rk30_i2c_set_clk(i2c, scl_rate);
238 /* returns TRUE if we this is the last byte in the current message */
239 static inline int is_msglast(struct rk30_i2c *i2c)
241 return i2c->msg_ptr == i2c->msg->len-1;
244 /* returns TRUE if we reached the end of the current message */
245 static inline int is_msgend(struct rk30_i2c *i2c)
247 return i2c->msg_ptr >= i2c->msg->len;
250 static void rk30_i2c_stop(struct rk30_i2c *i2c, int ret)
256 i2c->state = STATE_IDLE;
262 i2c_writel(I2C_STOPIEN, i2c->regs + I2C_IEN);
263 i2c->state = STATE_STOP;
264 rk30_i2c_send_stop(i2c);
267 static inline void rk30_set_rx_mode(struct rk30_i2c *i2c, unsigned int lastnak)
269 unsigned long con = i2c_readl(i2c->regs + I2C_CON);
271 con &= (~I2C_CON_MASK);
272 con |= (I2C_CON_MOD_RX << 1);
274 con |= I2C_CON_LASTACK;
275 i2c_writel(con, i2c->regs + I2C_CON);
277 static void rk30_irq_read_prepare(struct rk30_i2c *i2c)
279 unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
281 if(len <= 32 && i2c->msg_ptr != 0)
282 rk30_set_rx_mode(i2c, 1);
283 else if(i2c->msg_ptr != 0)
284 rk30_set_rx_mode(i2c, 0);
287 rk30_i2c_stop(i2c, i2c->error);
294 i2c_writel(cnt, i2c->regs + I2C_MRXCNT);
296 static void rk30_irq_read_get_data(struct rk30_i2c *i2c)
298 unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
301 len = (len >= 32)?32:len;
303 for(i = 0; i < len; i++){
305 p = i2c_readl(i2c->regs + I2C_RXDATA_BASE + (i/4) * 4);
306 i2c->msg->buf[i2c->msg_ptr++] = (p >>((i%4) * 8)) & 0xff;
311 static void rk30_irq_write_prepare(struct rk30_i2c *i2c)
313 unsigned int data = 0, cnt = 0, i, j;
317 rk30_i2c_stop(i2c, i2c->error);
320 for(i = 0; i < 8; i++){
322 for(j = 0; j < 4; j++) {
325 if(i2c->msg_ptr == 0 && cnt == 0)
326 byte = (i2c->addr & 0x7f) << 1;
328 byte = i2c->msg->buf[i2c->msg_ptr++];
330 data |= (byte << (j * 8));
332 i2c_writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
336 i2c_writel(cnt, i2c->regs + I2C_MTXCNT);
338 static void rk30_i2c_irq_nextblock(struct rk30_i2c *i2c, unsigned int ipd)
340 switch (i2c->state) {
342 if(!(ipd & I2C_STARTIPD)){
343 rk30_i2c_stop(i2c, -ENXIO);
344 dev_err(i2c->dev, "Addr[0x%02x] no start irq in STATE_START\n", i2c->addr);
346 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
349 i2c->complete_what |= 1<<i2c->state;
350 i2c_writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
351 rk30_i2c_clean_start(i2c);
352 if(i2c->mode == I2C_CON_MOD_TX){
353 i2c_writel(I2C_MBTFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
354 i2c->state = STATE_WRITE;
357 i2c_writel(I2C_MBRFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
358 i2c->state = STATE_READ;
362 if(!(ipd & I2C_MBTFIPD)){
363 rk30_i2c_stop(i2c, -ENXIO);
364 dev_err(i2c->dev, "Addr[0x%02x] no mbtf irq in STATE_WRITE\n", i2c->addr);
366 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
369 i2c->complete_what |= 1<<i2c->state;
370 i2c_writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
372 rk30_irq_write_prepare(i2c);
375 if(!(ipd & I2C_MBRFIPD)){
376 rk30_i2c_stop(i2c, -ENXIO);
377 dev_err(i2c->dev, "Addr[0x%02x] no mbrf irq in STATE_READ, ipd = 0x%x\n", i2c->addr, ipd);
379 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
382 i2c->complete_what |= 1<<i2c->state;
383 i2c_writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
384 rk30_irq_read_get_data(i2c);
386 rk30_irq_read_prepare(i2c);
389 if(!(ipd & I2C_STOPIPD)){
390 rk30_i2c_stop(i2c, -ENXIO);
391 dev_err(i2c->dev, "Addr[0x%02x] no stop irq in STATE_STOP\n", i2c->addr);
393 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
396 rk30_i2c_clean_stop(i2c);
397 i2c_writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
399 i2c->complete_what |= 1<<i2c->state;
400 i2c->state = STATE_IDLE;
409 static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
411 struct rk30_i2c *i2c = dev_id;
414 spin_lock(&i2c->lock);
415 ipd = i2c_readl(i2c->regs + I2C_IPD);
416 if(i2c->state == STATE_IDLE){
417 dev_info(i2c->dev, "Addr[0x%02x] irq in STATE_IDLE, ipd = 0x%x\n", i2c->addr, ipd);
418 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
422 if(ipd & I2C_NAKRCVIPD){
423 i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
424 i2c->error = -EAGAIN;
427 rk30_i2c_irq_nextblock(i2c, ipd);
429 spin_unlock(&i2c->lock);
434 static int rk30_i2c_set_master(struct rk30_i2c *i2c, struct i2c_msg *msgs, int num)
436 unsigned int addr = (msgs[0].addr & 0x7f) << 1;
437 unsigned int reg_valid_bits = 0;
438 unsigned int reg_addr = 0;
441 i2c->count = msgs[0].len;
442 if(!(msgs[0].flags & I2C_M_RD)){
444 i2c->mode = I2C_CON_MOD_TX;
449 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
450 i2c_writel(0, i2c->regs + I2C_MRXRADDR);
451 i2c->mode = I2C_CON_MOD_TRX;
452 //i2c->mode = I2C_CON_MOD_RX;
456 i2c->count = msgs[1].len;
459 reg_addr = msgs[0].buf[0];
460 reg_valid_bits |= I2C_MRXADDR_LOW;
463 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
464 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
467 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
468 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
473 if((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
476 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
477 i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
478 i2c->mode = I2C_CON_MOD_RRX;
480 else if(!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
482 i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
483 i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
484 i2c->mode = I2C_CON_MOD_TRX;
490 dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
498 * this starts an i2c transfer
500 static int rk30_i2c_doxfer(struct rk30_i2c *i2c,
501 struct i2c_msg *msgs, int num)
503 unsigned long timeout, flags;
505 /* 32 -- max transfer bytes
506 * 2 -- addr bytes * 2
507 * 3 -- max reg addr bytes
508 * 9 -- cycles per bytes
509 * max cycles: (32 + 2 + 3) * 9 --> 400 cycles
511 int msleep_time = 400 * 1000/ i2c->scl_rate; // ms
514 dev_err(i2c->dev, "i2c is suspended\n");
518 spin_lock_irqsave(&i2c->lock, flags);
519 if(rk30_i2c_set_master(i2c, msgs, num) < 0){
520 spin_unlock_irqrestore(&i2c->lock, flags);
521 dev_err(i2c->dev, "addr[0x%02x] set master error\n", msgs[0].addr);
524 i2c->addr = msgs[0].addr;
528 i2c->state = STATE_START;
529 i2c->complete_what = 0;
530 i2c_writel(I2C_STARTIEN, i2c->regs + I2C_IEN);
531 spin_unlock_irqrestore(&i2c->lock, flags);
533 rk30_i2c_enable(i2c, (i2c->count > 32)?0:1); //if count > 32, byte(32) send ack
536 int tmo = I2C_WAIT_TIMEOUT * USEC_PER_MSEC;
537 while(tmo-- && i2c->is_busy != 0)
539 timeout = (tmo <= 0)?0:1;
541 timeout = wait_event_timeout(i2c->wait, (i2c->is_busy == 0), msecs_to_jiffies(I2C_WAIT_TIMEOUT));
543 spin_lock_irqsave(&i2c->lock, flags);
544 i2c->state = STATE_IDLE;
546 spin_unlock_irqrestore(&i2c->lock, flags);
550 i2c_dbg(i2c->dev, "error = %d\n", error);
551 else if((i2c->complete_what !=COMPLETE_READ && i2c->complete_what != COMPLETE_WRITE)){
552 dev_err(i2c->dev, "Addr[0x%02x] wait event timeout, state: %d, is_busy: %d, error: %d, complete_what: 0x%x, ipd: 0x%x\n",
553 msgs[0].addr, i2c->state, i2c->is_busy, error, i2c->complete_what, i2c_readl(i2c->regs + I2C_IPD));
554 //rk30_show_regs(i2c);
557 rk30_i2c_send_stop(i2c);
561 i2c_dbg(i2c->dev, "Addr[0x%02x] wait event timeout, but transfer complete\n", i2c->addr);
563 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
564 rk30_i2c_disable_irq(i2c);
565 rk30_i2c_disable(i2c);
568 i2c_dbg(i2c->dev, "No ack(complete_what: 0x%x), Maybe slave(addr: 0x%02x) not exist or abnormal power-on\n",
569 i2c->complete_what, i2c->addr);
575 * first port of call from the i2c bus code when an message needs
576 * transferring across the i2c bus.
579 static int rk30_i2c_xfer(struct i2c_adapter *adap,
580 struct i2c_msg *msgs, int num)
582 int ret = 0, state, retry = 10;
583 unsigned long scl_rate;
584 struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
586 clk_enable(i2c->clk);
587 #ifdef I2C_CHECK_IDLE
588 while(retry-- && ((state = rk30_i2c_check_idle(i2c)) != I2C_IDLE)){
592 dev_err(i2c->dev, "i2c is not in idle(state = %d)\n", state);
597 if(msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
598 scl_rate = msgs[0].scl_rate;
599 else if(msgs[0].scl_rate > 400000){
600 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too high!",
601 msgs[0].addr, msgs[0].scl_rate/1000);
605 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too low!",
606 msgs[0].addr, msgs[0].scl_rate/1000);
609 if(i2c->is_div_from_arm[i2c->adap.nr]){
610 mutex_lock(&i2c->m_lock);
613 rk30_i2c_set_clk(i2c, scl_rate);
614 i2c_dbg(i2c->dev, "i2c transfer start: addr: 0x%x, scl_reate: %ldKhz, len: %d\n", msgs[0].addr, scl_rate/1000, num);
615 ret = rk30_i2c_doxfer(i2c, msgs, num);
616 i2c_dbg(i2c->dev, "i2c transfer stop: addr: 0x%x, state: %d, ret: %d\n", msgs[0].addr, ret, i2c->state);
618 if(i2c->is_div_from_arm[i2c->adap.nr]){
619 mutex_unlock(&i2c->m_lock);
622 clk_disable(i2c->clk);
623 return (ret < 0)?ret:num;
626 /* declare our i2c functionality */
627 static u32 rk30_i2c_func(struct i2c_adapter *adap)
629 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
632 /* i2c bus registration info */
634 static const struct i2c_algorithm rk30_i2c_algorithm = {
635 .master_xfer = rk30_i2c_xfer,
636 .functionality = rk30_i2c_func,
639 int i2c_add_rk30_adapter(struct i2c_adapter *adap)
642 struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
644 adap->algo = &rk30_i2c_algorithm;
646 i2c->i2c_init_hw = &rk30_i2c_init_hw;
647 i2c->i2c_set_clk = &rk30_i2c_set_clk;
648 i2c->i2c_irq = &rk30_i2c_irq;
650 ret = i2c_add_numbered_adapter(adap);