drivers/i2c/busses/i2c-rk30-adapter.c

   1 /* drivers/i2c/busses/i2c-rk30-adapter.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include "i2c-rk30.h"
  16
  17 /* Control register */
  18 #define I2C_CON         0X000
  19 enum{
  20     I2C_EN_BIT  = 0,
  21     I2C_MOD_BIT = 1,
  22     I2C_START_BIT = 3,
  23     I2C_STOP_BIT = 4,
  24     I2C_LAST_ACK_BIT = 5,
  25     I2C_ACT2ACK_BIT = 6,
  26 };
  27 //send ACK to slave when the last byte received in RX only mode
  28 #define LAST_SEND_ACK   0
  29 //send NAK to slave when the last byte received in RX only mode
  30 #define LAST_SEND_NAK   1
  31 #define LAST_SEND_TYPE  LAST_SEND_ACK //LAST_SEND_NAK
  32
  33 #define I2C_MOD_MASK    (3 << I2C_MOD_BIT)
  34 enum{
  35     I2C_MOD_TX = 0,
  36     I2C_MOD_TRX,
  37     I2C_MOD_RX,
  38     I2C_MOD_RRX,
  39 };
  40 /* Clock dividor register */
  41 #define I2C_CLKDIV      0x004
  42 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
  43 /* the slave address accessed  for master rx mode */
  44 #define I2C_MRXADDR     0x008
  45 #define I2C_MRXADDR_LOW     (1 << 24)
  46 #define I2C_MRXADDR_MID     (1 << 25)
  47 #define I2C_MRXADDR_HIGH     (1 << 26)
  48 /* the slave register address accessed  for master rx mode */
  49 #define I2C_MRXRADDR    0x00c
  50 #define I2C_MRXRADDR_LOW     (1 << 24)
  51 #define I2C_MRXRADDR_MID     (1 << 25)
  52 #define I2C_MRXRADDR_HIGH     (1 << 26)
  53 /* master tx count */
  54 #define I2C_MTXCNT      0x010
  55 /* master rx count */
  56 #define I2C_MRXCNT      0x014
  57 /* interrupt enable register */
  58 #define I2C_IEN         0x018
  59 #define I2C_BTFIEN  (1 << 0)
  60 #define I2C_BRFIEN  (1 << 1)
  61 #define I2C_MBTFIEN  (1 << 2)
  62 #define I2C_MBRFIEN  (1 << 3)
  63 #define I2C_STARTIEN  (1 << 4)
  64 #define I2C_STOPIEN  (1 << 5)
  65 #define I2C_NAKRCVIEN  (1 << 6)
  66 #define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
  67 #define IRQ_ALL_DISABLE 0
  68 /* interrupt pending register */
  69 #define I2C_IPD         0x01c
  70 #define I2C_BTFIPD  (1 << 0)
  71 #define I2C_BRFIPD  (1 << 1)
  72 #define I2C_MBTFIPD  (1 << 2)
  73 #define I2C_MBRFIPD  (1 << 3)
  74 #define I2C_STARTIPD  (1 << 4)
  75 #define I2C_STOPIPD  (1 << 5)
  76 #define I2C_NAKRCVIPD  (1 << 6)
  77 /* finished count */
  78 #define I2C_FCNT        0x020
  79 /* I2C tx data register */
  80 #define I2C_TXDATA_BASE 0X100
  81 /* I2C rx data register */
  82 #define I2C_RXDATA_BASE 0x200
  83 static void rk30_show_regs(struct rk30_i2c *i2c)
  84 {
  85     i2c_dbg(i2c->dev, "I2C_CON: 0x%08x\n", readl(i2c->regs + I2C_CON));
  86     i2c_dbg(i2c->dev, "I2C_CLKDIV: 0x%08x\n", readl(i2c->regs + I2C_CLKDIV));
  87     i2c_dbg(i2c->dev, "I2C_MRXADDR: 0x%08x\n", readl(i2c->regs + I2C_MRXADDR));
  88     i2c_dbg(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", readl(i2c->regs + I2C_MRXRADDR));
  89     i2c_dbg(i2c->dev, "I2C_MTXCNT: 0x%08x\n", readl(i2c->regs + I2C_MTXCNT));
  90     i2c_dbg(i2c->dev, "I2C_MRXCNT: 0x%08x\n", readl(i2c->regs + I2C_MRXCNT));
  91     i2c_dbg(i2c->dev, "I2C_IEN: 0x%08x\n", readl(i2c->regs + I2C_IEN));
  92     i2c_dbg(i2c->dev, "I2C_IPD: 0x%08x\n", readl(i2c->regs + I2C_IPD));
  93     i2c_dbg(i2c->dev, "I2C_FCNT: 0x%08x\n", readl(i2c->regs + I2C_FCNT));
  94     i2c_dbg(i2c->dev, "I2C_TXDATA0: 0x%08x\n", readl(i2c->regs + I2C_TXDATA_BASE + 0));
  95     i2c_dbg(i2c->dev, "I2C_RXDATA0: 0x%08x\n", readl(i2c->regs + I2C_RXDATA_BASE + 0));
  96 }
  97 static inline void rk30_i2c_last_ack(struct rk30_i2c *i2c, int enable)
  98 {
  99     unsigned int p = readl(i2c->regs + I2C_CON);
 100
 101     writel(rk30_set_bit(p, enable, I2C_LAST_ACK_BIT), i2c->regs + I2C_CON);
 102 }
 103 static inline void rk30_i2c_act2ack(struct rk30_i2c *i2c, int enable)
 104 {
 105     unsigned int p = readl(i2c->regs + I2C_CON);
 106
 107     writel(rk30_set_bit(p, enable, I2C_ACT2ACK_BIT), i2c->regs + I2C_CON);
 108 }
 109 static inline void rk30_i2c_enable(struct rk30_i2c *i2c, int enable)
 110 {
 111     unsigned int p = readl(i2c->regs + I2C_CON);
 112
 113     writel(rk30_set_bit(p, enable, I2C_EN_BIT), i2c->regs + I2C_CON);
 114 }
 115 static inline void rk30_i2c_set_mode(struct rk30_i2c *i2c)
 116 {
 117     unsigned int p = readl(i2c->regs + I2C_CON);
 118
 119     writel(rk30_set_bits(p, i2c->mode, I2C_MOD_BIT, I2C_MOD_MASK), i2c->regs + I2C_CON);
 120 }
 121 static inline void rk30_i2c_disable_irq(struct rk30_i2c *i2c)
 122 {
 123     writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
 124 }
 125
 126 static inline void rk30_i2c_enable_irq(struct rk30_i2c *i2c)
 127 {
 128     writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
 129 }
 130
 131 static inline void rk30_i2c_send_start(struct rk30_i2c *i2c)
 132 {
 133     unsigned int p = readl(i2c->regs + I2C_CON);
 134
 135     p = rk30_set_bit(p, 1, I2C_START_BIT);
 136     p = rk30_set_bit(p, 0, I2C_STOP_BIT);
 137     writel(p, i2c->regs + I2C_CON);
 138 }
 139 static inline void rk30_i2c_send_stop(struct rk30_i2c *i2c)
 140 {
 141     unsigned int p = readl(i2c->regs + I2C_CON);
 142
 143     p = rk30_set_bit(p, 0, I2C_START_BIT);
 144     p = rk30_set_bit(p, 1, I2C_STOP_BIT);
 145     writel(p, i2c->regs + I2C_CON);
 146
 147 }
 148 /* SCL Divisor = CLKDIVL + CLKDIVH
 149  * SCL = i2c_rate/ 8*SCLK Divisor
 150 */
 151 static void  rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
 152 {
 153     unsigned long i2c_rate = clk_get_rate(i2c->clk);
 154
 155     unsigned int div, divl, divh;
 156
 157     if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
 158         return;
 159     i2c->i2c_rate = i2c_rate;
 160     i2c->scl_rate = scl_rate;
 161     div = rk30_ceil(i2c_rate, scl_rate * 8);
 162     divh = divl = rk30_ceil(div, 2);
 163     writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
 164     return;
 165 }
 166 static void rk30_i2c_init_hw(struct rk30_i2c *i2c, unsigned long scl_rate)
 167 {
 168     rk30_i2c_set_clk(i2c, scl_rate);
 169         return;
 170 }
 171 /* returns TRUE if we this is the last byte in the current message */
 172 static inline int is_msglast(struct rk30_i2c *i2c)
 173 {
 174         return i2c->msg_ptr == i2c->msg->len-1;
 175 }
 176
 177 /* returns TRUE if we reached the end of the current message */
 178 static inline int is_msgend(struct rk30_i2c *i2c)
 179 {
 180         return i2c->msg_ptr >= i2c->msg->len;
 181 }
 182
 183 static void rk30_i2c_stop(struct rk30_i2c *i2c, int ret)
 184 {
 185
 186     i2c->msg_ptr = 0;
 187         i2c->msg = NULL;
 188         i2c->msg_idx++;
 189         i2c->msg_num = 0;
 190         if (ret)
 191                 i2c->msg_idx = ret;
 192
 193     i2c->state = STATE_STOP;
 194     rk30_i2c_send_stop(i2c);
 195 }
 196 static void rk30_irq_read_prepare(struct rk30_i2c *i2c)
 197 {
 198     unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
 199
 200     if(is_msgend(i2c)) {
 201         rk30_i2c_stop(i2c, 0);
 202         return;
 203     }
 204     if(len > 32)
 205         cnt = 32;
 206     else
 207         cnt = len;
 208
 209     writel(cnt, i2c->regs + I2C_MRXCNT);
 210 }
 211 static void rk30_irq_read_get_data(struct rk30_i2c *i2c)
 212 {
 213      unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
 214      unsigned int p;
 215
 216      len = (len >= 32)?32:len;
 217
 218      for(i = 0; i < len; i++){
 219          if(i%4 == 0)
 220              p = readl(i2c->regs + I2C_RXDATA_BASE +  (i/4) * 4);
 221          i2c->msg->buf[i2c->msg_ptr++] = (p >>((i%4) * 8)) & 0xff;
 222     }
 223
 224      return;
 225 }
 226 static void rk30_irq_write_prepare(struct rk30_i2c *i2c)
 227 {
 228     unsigned int data = 0, cnt = 0, i, j;
 229     unsigned char byte;
 230
 231     if(is_msgend(i2c)) {
 232         rk30_i2c_stop(i2c, 0);
 233         return;
 234     }
 235     for(i = 0; i < 8; i++){
 236         data = 0;
 237         for(j = 0; j < 4; j++) {
 238             if(is_msgend(i2c))
 239                 break;
 240             if(i2c->msg_ptr == 0 && cnt == 0)
 241                 byte = (i2c->addr & 0x7f) << 1;
 242             else
 243                 byte =  i2c->msg->buf[i2c->msg_ptr++];
 244             cnt++;
 245             data |= (byte << (j * 8));
 246         }
 247         writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
 248         if(is_msgend(i2c))
 249             break;
 250     }
 251     writel(cnt, i2c->regs + I2C_MTXCNT);
 252 }
 253 static void rk30_i2c_irq_nextblock(struct rk30_i2c *i2c, unsigned int ipd)
 254 {
 255     switch (i2c->state) {
 256         case STATE_IDLE:
 257                 dev_err(i2c->dev, "Addr[0x%02x] called in STATE_IDLE\n", i2c->addr);
 258                 goto out;
 259     case STATE_START:
 260         if(!(ipd & I2C_STARTIPD)){
 261             if(ipd & I2C_STOPIPD){
 262                 writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
 263                 rk30_i2c_send_start(i2c);
 264             }
 265             else {
 266                 rk30_i2c_stop(i2c, -ENXIO);
 267                             dev_err(i2c->dev, "Addr[0x%02x] no start irq in STATE_START\n", i2c->addr);
 268                 rk30_show_regs(i2c);
 269             }
 270             goto out;
 271         }
 272         writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
 273         if(i2c->mode ==  I2C_MOD_TX){
 274             i2c->state = STATE_WRITE;
 275             goto prepare_write;
 276         }
 277         else {
 278              i2c->state = STATE_READ;
 279              goto prepare_read;
 280         }
 281     case STATE_WRITE:
 282         if(!(ipd & I2C_MBTFIPD)){
 283             goto out;
 284         }
 285         writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
 286 prepare_write:
 287         rk30_irq_write_prepare(i2c);
 288         break;
 289     case STATE_READ:
 290         if(!(ipd & I2C_MBRFIPD)){
 291             goto out;
 292         }
 293         writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
 294         rk30_irq_read_get_data(i2c);
 295 prepare_read:
 296         rk30_irq_read_prepare(i2c);
 297         break;
 298     case STATE_STOP:
 299         if(ipd & I2C_STOPIPD || i2c->msg_idx  < 0){
 300             writel(0xff, i2c->regs + I2C_IPD);
 301                 rk30_i2c_disable_irq(i2c);
 302                 wake_up(&i2c->wait);
 303         }
 304         break;
 305     default:
 306         break;
 307     }
 308 out:
 309     return;
 310 }
 311 static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
 312 {
 313     struct rk30_i2c *i2c = dev_id;
 314     unsigned int ipd;
 315     spin_lock(&i2c->lock);
 316     ipd = readl(i2c->regs + I2C_IPD);
 317
 318     if(ipd & I2C_NAKRCVIPD) {
 319         writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
 320         rk30_i2c_stop(i2c, -EAGAIN);
 321                 dev_err(i2c->dev, "Addr[0x%02x] ack was not received\n", i2c->addr);
 322         rk30_show_regs(i2c);
 323         goto out;
 324     }
 325
 326     rk30_i2c_irq_nextblock(i2c, ipd);
 327 out:
 328     spin_unlock(&i2c->lock);
 329         return IRQ_HANDLED;
 330 }
 331
 332
 333 static int rk30_i2c_set_master(struct rk30_i2c *i2c, struct i2c_msg *msgs, int num)
 334 {
 335     unsigned int addr = (msgs[0].addr & 0x7f) << 1;
 336     unsigned int reg_valid_bits = 0;
 337     unsigned int reg_addr = 0;
 338
 339     if(num == 1) {
 340         if(!(msgs[0].flags & I2C_M_RD)){
 341                 i2c->msg = &msgs[0];
 342             i2c->mode = I2C_MOD_TX;
 343         }
 344         else {
 345             addr |= 1;
 346                 i2c->msg = &msgs[0];
 347             writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 348             i2c->mode = I2C_MOD_RX;
 349         }
 350     }
 351     else if(num == 2) {
 352         switch(msgs[0].len){
 353             case 1:
 354                 reg_addr = msgs[0].buf[0];
 355                 reg_valid_bits |= I2C_MRXADDR_LOW;
 356                 break;
 357             case 2:
 358                 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
 359                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
 360                 break;
 361             case 3:
 362                 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
 363                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
 364                 break;
 365             default:
 366                 return -EIO;
 367         }
 368         if((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 369             addr |= 1;
 370                 i2c->msg = &msgs[1];
 371             writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 372             writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 373             i2c->mode = I2C_MOD_RRX;
 374         }
 375         else if(!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 376                 i2c->msg = &msgs[1];
 377             writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 378             writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 379             i2c->mode = I2C_MOD_TRX;
 380         }
 381         else
 382             return -EIO;
 383     }
 384     else {
 385         dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
 386         return -EIO;
 387     }
 388     rk30_i2c_set_mode(i2c);
 389     rk30_i2c_last_ack(i2c, LAST_SEND_TYPE);
 390     if(msgs[0].flags & I2C_M_IGNORE_NAK)
 391         rk30_i2c_act2ack(i2c, 0);
 392     else
 393         rk30_i2c_act2ack(i2c, 1);
 394
 395     return 0;
 396 }
 397 /* rk30_i2c_doxfer
 398  *
 399  * this starts an i2c transfer
 400 */
 401 static int rk30_i2c_doxfer(struct rk30_i2c *i2c,
 402                               struct i2c_msg *msgs, int num)
 403 {
 404         unsigned long timeout;
 405         int ret = 0;
 406
 407         if (i2c->suspended)
 408                 return -EIO;
 409
 410         ret = rk30_i2c_set_master(i2c, msgs, num);
 411         if (ret != 0) {
 412         dev_err(i2c->dev, "addr[0x%02x] set master error\n", msgs[0].addr);
 413         return ret;
 414     }
 415         spin_lock_irq(&i2c->lock);
 416
 417     i2c->addr = msgs[0].addr;
 418         i2c->msg_num = num;
 419     i2c->msg_ptr = 0;
 420     i2c->msg_idx = 0;
 421     i2c->state = STATE_START;
 422
 423         spin_unlock_irq(&i2c->lock);
 424
 425         rk30_i2c_enable_irq(i2c);
 426     rk30_i2c_send_start(i2c);
 427
 428         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, msecs_to_jiffies(I2C_WAIT_TIMEOUT));
 429
 430         ret = i2c->msg_idx;
 431
 432         if (timeout == 0){
 433         dev_err(i2c->dev, "addr[0x%02x] wait event timeout, state = %d\n", msgs[0].addr, i2c->state);
 434         rk30_show_regs(i2c);
 435         rk30_i2c_send_stop(i2c);
 436         if(ret >= 0)
 437             ret = -ETIMEDOUT;
 438         goto out;
 439     }
 440     if(ret > 0)
 441         ret = num;
 442  out:
 443     writel(0xff, i2c->regs + I2C_IPD);
 444         rk30_i2c_disable_irq(i2c);
 445         return ret;
 446 }
 447
 448 /* rk30_i2c_xfer
 449  *
 450  * first port of call from the i2c bus code when an message needs
 451  * transferring across the i2c bus.
 452 */
 453
 454 static int rk30_i2c_xfer(struct i2c_adapter *adap,
 455                         struct i2c_msg *msgs, int num)
 456 {
 457         int ret = 0;
 458     unsigned long scl_rate;
 459         struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 460
 461     if(msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
 462                 scl_rate = msgs[0].scl_rate;
 463         else if(msgs[0].scl_rate > 400000){
 464                 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too high!",
 465                         msgs[0].addr, msgs[0].scl_rate/1000);
 466                 scl_rate = 400000;
 467         }
 468         else{
 469                 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too low!",
 470                         msgs[0].addr, msgs[0].scl_rate/1000);
 471                 scl_rate = 10000;
 472         }
 473     if(i2c->is_div_from_arm[i2c->adap.nr])
 474                 wake_lock(&i2c->idlelock[i2c->adap.nr]);
 475
 476     rk30_i2c_enable(i2c, 1);
 477         rk30_i2c_set_clk(i2c, scl_rate);
 478     udelay(i2c->tx_setup);
 479
 480     i2c_dbg(i2c->dev, "i2c transfer: addr[0x%x], scl_reate[%ldKhz]\n", msgs[0].addr, scl_rate/1000);
 481         ret = rk30_i2c_doxfer(i2c, msgs, num);
 482
 483     rk30_i2c_enable(i2c, 0);
 484     i2c->state = STATE_IDLE;
 485     if(i2c->is_div_from_arm[i2c->adap.nr])
 486                 wake_unlock(&i2c->idlelock[i2c->adap.nr]);
 487         return ret;
 488 }
 489
 490 /* declare our i2c functionality */
 491 static u32 rk30_i2c_func(struct i2c_adapter *adap)
 492 {
 493         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 494 }
 495
 496 /* i2c bus registration info */
 497
 498 static const struct i2c_algorithm rk30_i2c_algorithm = {
 499         .master_xfer            = rk30_i2c_xfer,
 500         .functionality          = rk30_i2c_func,
 501 };
 502
 503 int i2c_add_rk30_adapter(struct i2c_adapter *adap)
 504 {
 505     int ret = 0;
 506     struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 507
 508     adap->algo = &rk30_i2c_algorithm;
 509
 510     i2c->i2c_init_hw = &rk30_i2c_init_hw;
 511     i2c->i2c_set_clk = &rk30_i2c_set_clk;
 512     i2c->i2c_irq = &rk30_i2c_irq;
 513
 514     ret = i2c_add_numbered_adapter(adap);
 515
 516     return ret;
 517 }
 518