drivers/i2c/busses/i2c-rk30-adapter.c

   1 /* drivers/i2c/busses/i2c-rk30-adapter.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include "i2c-rk30.h"
  16
  17 /* Control register */
  18 #define I2C_CON         0X000
  19 enum{
  20     I2C_EN_BIT  = 0,
  21     I2C_MOD_BIT = 1,
  22     I2C_START_BIT = 3,
  23     I2C_STOP_BIT = 4,
  24     I2C_LAST_ACK_BIT = 5,
  25     I2C_ACT2ACK_BIT = 6,
  26 };
  27 //send ACK to slave when the last byte received in RX only mode
  28 #define LAST_SEND_ACK   0
  29 //send NAK to slave when the last byte received in RX only mode
  30 #define LAST_SEND_NAK   1
  31 #define LAST_SEND_TYPE  LAST_SEND_ACK //LAST_SEND_NAK
  32
  33 #define I2C_MOD_MASK    (3 << I2C_MOD_BIT)
  34 enum{
  35     I2C_MOD_TX = 0,
  36     I2C_MOD_TRX,
  37     I2C_MOD_RX,
  38     I2C_MOD_RRX,
  39 };
  40 /* Clock dividor register */
  41 #define I2C_CLKDIV      0x004
  42 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
  43 /* the slave address accessed  for master rx mode */
  44 #define I2C_MRXADDR     0x008
  45 #define I2C_MRXADDR_LOW     (1 << 24)
  46 #define I2C_MRXADDR_MID     (1 << 25)
  47 #define I2C_MRXADDR_HIGH     (1 << 26)
  48 /* the slave register address accessed  for master rx mode */
  49 #define I2C_MRXRADDR    0x00c
  50 #define I2C_MRXRADDR_LOW     (1 << 24)
  51 #define I2C_MRXRADDR_MID     (1 << 25)
  52 #define I2C_MRXRADDR_HIGH     (1 << 26)
  53 /* master tx count */
  54 #define I2C_MTXCNT      0x010
  55 /* master rx count */
  56 #define I2C_MRXCNT      0x014
  57 /* interrupt enable register */
  58 #define I2C_IEN         0x018
  59 #define I2C_BTFIEN  (1 << 0)
  60 #define I2C_BRFIEN  (1 << 1)
  61 #define I2C_MBTFIEN  (1 << 2)
  62 #define I2C_MBRFIEN  (1 << 3)
  63 #define I2C_STARTIEN  (1 << 4)
  64 #define I2C_STOPIEN  (1 << 5)
  65 #define I2C_NAKRCVIEN  (1 << 6)
  66 #define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
  67 #define IRQ_ALL_DISABLE 0
  68 /* interrupt pending register */
  69 #define I2C_IPD         0x01c
  70 #define I2C_BTFIPD  (1 << 0)
  71 #define I2C_BRFIPD  (1 << 1)
  72 #define I2C_MBTFIPD  (1 << 2)
  73 #define I2C_MBRFIPD  (1 << 3)
  74 #define I2C_STARTIPD  (1 << 4)
  75 #define I2C_STOPIPD  (1 << 5)
  76 #define I2C_NAKRCVIPD  (1 << 6)
  77 /* finished count */
  78 #define I2C_FCNT        0x020
  79 /* I2C tx data register */
  80 #define I2C_TXDATA_BASE 0X100
  81 /* I2C rx data register */
  82 #define I2C_RXDATA_BASE 0x200
  83 static void rk30_show_regs(struct rk30_i2c *i2c)
  84 {
  85     i2c_dbg(i2c->dev, "I2C_CON: 0x%08x\n", readl(i2c->regs + I2C_CON));
  86     i2c_dbg(i2c->dev, "I2C_CLKDIV: 0x%08x\n", readl(i2c->regs + I2C_CLKDIV));
  87     i2c_dbg(i2c->dev, "I2C_MRXADDR: 0x%08x\n", readl(i2c->regs + I2C_MRXADDR));
  88     i2c_dbg(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", readl(i2c->regs + I2C_MRXRADDR));
  89     i2c_dbg(i2c->dev, "I2C_MTXCNT: 0x%08x\n", readl(i2c->regs + I2C_MTXCNT));
  90     i2c_dbg(i2c->dev, "I2C_MRXCNT: 0x%08x\n", readl(i2c->regs + I2C_MRXCNT));
  91     i2c_dbg(i2c->dev, "I2C_IEN: 0x%08x\n", readl(i2c->regs + I2C_IEN));
  92     i2c_dbg(i2c->dev, "I2C_IPD: 0x%08x\n", readl(i2c->regs + I2C_IPD));
  93     i2c_dbg(i2c->dev, "I2C_FCNT: 0x%08x\n", readl(i2c->regs + I2C_FCNT));
  94     i2c_dbg(i2c->dev, "I2C_TXDATA0: 0x%08x\n", readl(i2c->regs + I2C_TXDATA_BASE + 0));
  95     i2c_dbg(i2c->dev, "I2C_RXDATA0: 0x%08x\n", readl(i2c->regs + I2C_RXDATA_BASE + 0));
  96 }
  97 static inline void rk30_i2c_last_ack(struct rk30_i2c *i2c, int enable)
  98 {
  99     unsigned int p = readl(i2c->regs + I2C_CON);
 100
 101     p = rk30_set_bit(p, 0, I2C_START_BIT);
 102     p = rk30_set_bit(p, 0, I2C_STOP_BIT);
 103     writel(rk30_set_bit(p, enable, I2C_LAST_ACK_BIT), i2c->regs + I2C_CON);
 104 }
 105 static inline void rk30_i2c_act2ack(struct rk30_i2c *i2c, int enable)
 106 {
 107     unsigned int p = readl(i2c->regs + I2C_CON);
 108
 109     p = rk30_set_bit(p, 0, I2C_START_BIT);
 110     p = rk30_set_bit(p, 0, I2C_STOP_BIT);
 111     writel(rk30_set_bit(p, enable, I2C_ACT2ACK_BIT), i2c->regs + I2C_CON);
 112 }
 113 static inline void rk30_i2c_enable(struct rk30_i2c *i2c, int enable)
 114 {
 115     unsigned int p = readl(i2c->regs + I2C_CON);
 116
 117     p = rk30_set_bit(p, 0, I2C_START_BIT);
 118     p = rk30_set_bit(p, 0, I2C_STOP_BIT);
 119
 120     writel(rk30_set_bit(p, enable, I2C_EN_BIT), i2c->regs + I2C_CON);
 121 }
 122 static inline void rk30_i2c_set_mode(struct rk30_i2c *i2c)
 123 {
 124     unsigned int p = readl(i2c->regs + I2C_CON);
 125
 126     p = rk30_set_bit(p, 0, I2C_START_BIT);
 127     p = rk30_set_bit(p, 0, I2C_STOP_BIT);
 128     writel(rk30_set_bits(p, i2c->mode, I2C_MOD_BIT, I2C_MOD_MASK), i2c->regs + I2C_CON);
 129 }
 130 static inline void rk30_i2c_disable_irq(struct rk30_i2c *i2c)
 131 {
 132     writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
 133 }
 134
 135 static inline void rk30_i2c_enable_irq(struct rk30_i2c *i2c)
 136 {
 137     writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
 138 }
 139
 140 static inline void rk30_i2c_send_start(struct rk30_i2c *i2c)
 141 {
 142     unsigned int p = readl(i2c->regs + I2C_CON);
 143
 144     p = rk30_set_bit(p, 1, I2C_START_BIT);
 145     p = rk30_set_bit(p, 0, I2C_STOP_BIT);
 146     writel(p, i2c->regs + I2C_CON);
 147 }
 148 static inline void rk30_i2c_send_stop(struct rk30_i2c *i2c)
 149 {
 150     unsigned int p = readl(i2c->regs + I2C_CON);
 151
 152     p = rk30_set_bit(p, 0, I2C_START_BIT);
 153     p = rk30_set_bit(p, 1, I2C_STOP_BIT);
 154     writel(p, i2c->regs + I2C_CON);
 155
 156 }
 157 /* SCL Divisor = 8 * (CLKDIVL + CLKDIVH)
 158  * SCL = i2c_rate/ SCLK Divisor
 159 */
 160 static void  rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
 161 {
 162     unsigned long i2c_rate = clk_get_rate(i2c->clk);
 163
 164     unsigned int div, divl, divh;
 165
 166     if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
 167         return;
 168     i2c->i2c_rate = i2c_rate;
 169     i2c->scl_rate = scl_rate;
 170     div = rk30_ceil(i2c_rate, scl_rate * 8);
 171     divh = divl = rk30_ceil(div, 2);
 172     i2c_dbg(i2c->dev, "div divh divl: %d %d %d\n", div, divh, divl);
 173     writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
 174     return;
 175 }
 176 static void rk30_i2c_init_hw(struct rk30_i2c *i2c, unsigned long scl_rate)
 177 {
 178     rk30_i2c_set_clk(i2c, scl_rate);
 179         return;
 180 }
 181 /* returns TRUE if we this is the last byte in the current message */
 182 static inline int is_msglast(struct rk30_i2c *i2c)
 183 {
 184         return i2c->msg_ptr == i2c->msg->len-1;
 185 }
 186
 187 /* returns TRUE if we reached the end of the current message */
 188 static inline int is_msgend(struct rk30_i2c *i2c)
 189 {
 190         return i2c->msg_ptr >= i2c->msg->len;
 191 }
 192
 193 static void rk30_i2c_stop(struct rk30_i2c *i2c, int ret)
 194 {
 195
 196     i2c->msg_ptr = 0;
 197         i2c->msg = NULL;
 198         i2c->msg_idx++;
 199         i2c->msg_num = 0;
 200         if (ret)
 201                 i2c->msg_idx = ret;
 202
 203         mdelay(10);
 204     i2c->state = STATE_STOP;
 205     rk30_i2c_send_stop(i2c);
 206 }
 207 static void rk30_irq_read_prepare(struct rk30_i2c *i2c)
 208 {
 209     unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
 210
 211     if(is_msgend(i2c)) {
 212         rk30_i2c_stop(i2c, 0);
 213         return;
 214     }
 215     if(len > 32)
 216         cnt = 32;
 217     else
 218         cnt = len;
 219
 220     writel(cnt, i2c->regs + I2C_MRXCNT);
 221 }
 222 static void rk30_irq_read_get_data(struct rk30_i2c *i2c)
 223 {
 224      unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
 225      unsigned int p;
 226
 227      len = (len >= 32)?32:len;
 228
 229      for(i = 0; i < len; i++){
 230          if(i%4 == 0)
 231              p = readl(i2c->regs + I2C_RXDATA_BASE +  (i/4) * 4);
 232          i2c->msg->buf[i2c->msg_ptr++] = (p >>((i%4) * 8)) & 0xff;
 233     }
 234
 235      return;
 236 }
 237 static void rk30_irq_write_prepare(struct rk30_i2c *i2c)
 238 {
 239     unsigned int data = 0, cnt = 0, i, j;
 240     unsigned char byte;
 241
 242     if(is_msgend(i2c)) {
 243         rk30_i2c_stop(i2c, 0);
 244         return;
 245     }
 246     for(i = 0; i < 8; i++){
 247         data = 0;
 248         for(j = 0; j < 4; j++) {
 249             if(is_msgend(i2c))
 250                 break;
 251             if(i2c->msg_ptr == 0 && cnt == 0)
 252                 byte = (i2c->addr & 0x7f) << 1;
 253             else
 254                 byte =  i2c->msg->buf[i2c->msg_ptr++];
 255             cnt++;
 256             data |= (byte << (j * 8));
 257         }
 258         writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
 259         if(is_msgend(i2c))
 260             break;
 261     }
 262     writel(cnt, i2c->regs + I2C_MTXCNT);
 263 }
 264 static void rk30_i2c_irq_nextblock(struct rk30_i2c *i2c, unsigned int ipd)
 265 {
 266     switch (i2c->state) {
 267         case STATE_IDLE:
 268                 dev_err(i2c->dev, "Addr[0x%02x] called in STATE_IDLE\n", i2c->addr);
 269                 goto out;
 270     case STATE_START:
 271         if(!(ipd & I2C_STARTIPD)){
 272             if(ipd & I2C_STOPIPD){
 273                 writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
 274             }
 275             else {
 276                 rk30_i2c_stop(i2c, -ENXIO);
 277                             dev_err(i2c->dev, "Addr[0x%02x] no start irq in STATE_START\n", i2c->addr);
 278                 rk30_show_regs(i2c);
 279             }
 280             goto out;
 281         }
 282         writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
 283         if(i2c->mode ==  I2C_MOD_TX){
 284             i2c->state = STATE_WRITE;
 285             goto prepare_write;
 286         }
 287         else {
 288              i2c->state = STATE_READ;
 289              goto prepare_read;
 290         }
 291     case STATE_WRITE:
 292         if(!(ipd & I2C_MBTFIPD)){
 293             goto out;
 294         }
 295         writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
 296 prepare_write:
 297         rk30_irq_write_prepare(i2c);
 298         break;
 299     case STATE_READ:
 300         if(!(ipd & I2C_MBRFIPD)){
 301             goto out;
 302         }
 303         writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
 304         rk30_irq_read_get_data(i2c);
 305 prepare_read:
 306         rk30_irq_read_prepare(i2c);
 307         break;
 308     case STATE_STOP:
 309         if(ipd & I2C_STOPIPD){
 310             writel(0xff, i2c->regs + I2C_IPD);
 311             i2c->state = STATE_IDLE;
 312                 rk30_i2c_disable_irq(i2c);
 313                 wake_up(&i2c->wait);
 314         }
 315         break;
 316     default:
 317         break;
 318     }
 319 out:
 320     return;
 321 }
 322 static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
 323 {
 324     struct rk30_i2c *i2c = dev_id;
 325     unsigned int ipd;
 326     spin_lock(&i2c->lock);
 327     ipd = readl(i2c->regs + I2C_IPD);
 328
 329     if(ipd & I2C_NAKRCVIPD) {
 330         writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
 331         rk30_i2c_stop(i2c, -EAGAIN);
 332                 dev_dbg(i2c->dev, "Addr[0x%02x] ack was not received\n", i2c->addr);
 333         rk30_show_regs(i2c);
 334         goto out;
 335     }
 336
 337     rk30_i2c_irq_nextblock(i2c, ipd);
 338 out:
 339     spin_unlock(&i2c->lock);
 340         return IRQ_HANDLED;
 341 }
 342
 343
 344 static int rk30_i2c_set_master(struct rk30_i2c *i2c, struct i2c_msg *msgs, int num)
 345 {
 346     unsigned int addr = (msgs[0].addr & 0x7f) << 1;
 347     unsigned int reg_valid_bits = 0;
 348     unsigned int reg_addr = 0;
 349
 350     if(num == 1) {
 351         if(!(msgs[0].flags & I2C_M_RD)){
 352                 i2c->msg = &msgs[0];
 353             i2c->mode = I2C_MOD_TX;
 354         }
 355         else {
 356             addr |= 1;
 357                 i2c->msg = &msgs[0];
 358             writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 359             i2c->mode = I2C_MOD_RX;
 360         }
 361     }
 362     else if(num == 2) {
 363         switch(msgs[0].len){
 364             case 1:
 365                 reg_addr = msgs[0].buf[0];
 366                 reg_valid_bits |= I2C_MRXADDR_LOW;
 367                 break;
 368             case 2:
 369                 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
 370                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
 371                 break;
 372             case 3:
 373                 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
 374                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
 375                 break;
 376             default:
 377                 return -EIO;
 378         }
 379         if((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 380             addr |= 1;
 381                 i2c->msg = &msgs[1];
 382             writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 383             writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 384             i2c->mode = I2C_MOD_RRX;
 385         }
 386         else if(!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 387                 i2c->msg = &msgs[1];
 388             writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 389             writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 390             i2c->mode = I2C_MOD_TRX;
 391         }
 392         else
 393             return -EIO;
 394     }
 395     else {
 396         dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
 397         return -EIO;
 398     }
 399     rk30_i2c_set_mode(i2c);
 400     rk30_i2c_last_ack(i2c, LAST_SEND_TYPE);
 401     if(msgs[0].flags & I2C_M_IGNORE_NAK)
 402         rk30_i2c_act2ack(i2c, 0);
 403     else
 404         rk30_i2c_act2ack(i2c, 1);
 405
 406     return 0;
 407 }
 408 /* rk30_i2c_doxfer
 409  *
 410  * this starts an i2c transfer
 411 */
 412 static int rk30_i2c_doxfer(struct rk30_i2c *i2c,
 413                               struct i2c_msg *msgs, int num)
 414 {
 415         unsigned long timeout;
 416         int ret = 0;
 417
 418         if (i2c->suspended)
 419                 return -EIO;
 420
 421         ret = rk30_i2c_set_master(i2c, msgs, num);
 422         if (ret != 0) {
 423         dev_err(i2c->dev, "addr[0x%02x] set master error\n", msgs[0].addr);
 424         return ret;
 425     }
 426         spin_lock_irq(&i2c->lock);
 427
 428     i2c->addr = msgs[0].addr;
 429         i2c->msg_num = num;
 430     i2c->msg_ptr = 0;
 431     i2c->msg_idx = 0;
 432     i2c->state = STATE_START;
 433
 434         spin_unlock_irq(&i2c->lock);
 435
 436         rk30_i2c_enable_irq(i2c);
 437     rk30_i2c_send_start(i2c);
 438
 439         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, msecs_to_jiffies(I2C_WAIT_TIMEOUT));
 440
 441         ret = i2c->msg_idx;
 442
 443         if (timeout == 0){
 444         dev_err(i2c->dev, "addr[0x%02x] wait event timeout, state = %d\n", msgs[0].addr, i2c->state);
 445         rk30_show_regs(i2c);
 446         writel(0xff, i2c->regs + I2C_IPD);
 447             rk30_i2c_disable_irq(i2c);
 448         rk30_i2c_send_stop(i2c);
 449         if(ret >= 0)
 450             ret = -ETIMEDOUT;
 451         return ret;
 452     }
 453     if(ret > 0)
 454         ret = num;
 455         return ret;
 456 }
 457
 458 /* rk30_i2c_xfer
 459  *
 460  * first port of call from the i2c bus code when an message needs
 461  * transferring across the i2c bus.
 462 */
 463
 464 static int rk30_i2c_xfer(struct i2c_adapter *adap,
 465                         struct i2c_msg *msgs, int num)
 466 {
 467         int ret = 0;
 468     unsigned long scl_rate;
 469         struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 470
 471     if(msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
 472                 scl_rate = msgs[0].scl_rate;
 473         else if(msgs[0].scl_rate > 400000){
 474                 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too high!",
 475                         msgs[0].addr, msgs[0].scl_rate/1000);
 476                 scl_rate = 400000;
 477         }
 478         else{
 479                 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too low!",
 480                         msgs[0].addr, msgs[0].scl_rate/1000);
 481                 scl_rate = 10000;
 482         }
 483     if(i2c->is_div_from_arm[i2c->adap.nr])
 484                 wake_lock(&i2c->idlelock[i2c->adap.nr]);
 485
 486     rk30_i2c_enable(i2c, 1);
 487         rk30_i2c_set_clk(i2c, scl_rate);
 488     udelay(i2c->tx_setup);
 489
 490     i2c_dbg(i2c->dev, "i2c transfer: addr[0x%x], scl_reate[%ldKhz]\n", msgs[0].addr, scl_rate/1000);
 491         ret = rk30_i2c_doxfer(i2c, msgs, num);
 492
 493     rk30_i2c_enable(i2c, 0);
 494     i2c->state = STATE_IDLE;
 495     if(i2c->is_div_from_arm[i2c->adap.nr])
 496                 wake_unlock(&i2c->idlelock[i2c->adap.nr]);
 497         return ret;
 498 }
 499
 500 /* declare our i2c functionality */
 501 static u32 rk30_i2c_func(struct i2c_adapter *adap)
 502 {
 503         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 504 }
 505
 506 /* i2c bus registration info */
 507
 508 static const struct i2c_algorithm rk30_i2c_algorithm = {
 509         .master_xfer            = rk30_i2c_xfer,
 510         .functionality          = rk30_i2c_func,
 511 };
 512
 513 int i2c_add_rk30_adapter(struct i2c_adapter *adap)
 514 {
 515     int ret = 0;
 516     struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 517
 518     adap->algo = &rk30_i2c_algorithm;
 519
 520     i2c->i2c_init_hw = &rk30_i2c_init_hw;
 521     i2c->i2c_set_clk = &rk30_i2c_set_clk;
 522     i2c->i2c_irq = &rk30_i2c_irq;
 523
 524     ret = i2c_add_numbered_adapter(adap);
 525
 526     return ret;
 527 }
 528