drivers/i2c/busses/i2c-rk30-adapter.c

   1 /* drivers/i2c/busses/i2c-rk30-adapter.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include "i2c-rk30.h"
  16
  17 #define COMPLETE_READ     (1<<STATE_START|1<<STATE_READ|1<<STATE_STOP)
  18 #define COMPLETE_WRITE     (1<<STATE_START|1<<STATE_WRITE|1<<STATE_STOP)
  19
  20 /* Control register */
  21 #define I2C_CON                 0x000
  22 #define I2C_CON_EN              (1 << 0)
  23 #define I2C_CON_MOD(mod)        ((mod) << 1)
  24 #define I2C_CON_MASK            (3 << 1)
  25 enum{
  26         I2C_CON_MOD_TX = 0,
  27         I2C_CON_MOD_TRX,
  28         I2C_CON_MOD_RX,
  29         I2C_CON_MOD_RRX,
  30 };
  31 #define I2C_CON_START           (1 << 3)
  32 #define I2C_CON_STOP            (1 << 4)
  33 #define I2C_CON_LASTACK         (1 << 5)
  34 #define I2C_CON_ACTACK          (1 << 6)
  35
  36 /* Clock dividor register */
  37 #define I2C_CLKDIV              0x004
  38 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
  39
  40 /* the slave address accessed  for master rx mode */
  41 #define I2C_MRXADDR             0x008
  42 #define I2C_MRXADDR_LOW         (1 << 24)
  43 #define I2C_MRXADDR_MID         (1 << 25)
  44 #define I2C_MRXADDR_HIGH        (1 << 26)
  45
  46 /* the slave register address accessed  for master rx mode */
  47 #define I2C_MRXRADDR            0x00c
  48 #define I2C_MRXRADDR_LOW        (1 << 24)
  49 #define I2C_MRXRADDR_MID        (1 << 25)
  50 #define I2C_MRXRADDR_HIGH       (1 << 26)
  51
  52 /* master tx count */
  53 #define I2C_MTXCNT              0x010
  54
  55 /* master rx count */
  56 #define I2C_MRXCNT              0x014
  57
  58 /* interrupt enable register */
  59 #define I2C_IEN                 0x018
  60 #define I2C_BTFIEN              (1 << 0)
  61 #define I2C_BRFIEN              (1 << 1)
  62 #define I2C_MBTFIEN             (1 << 2)
  63 #define I2C_MBRFIEN             (1 << 3)
  64 #define I2C_STARTIEN            (1 << 4)
  65 #define I2C_STOPIEN             (1 << 5)
  66 #define I2C_NAKRCVIEN           (1 << 6)
  67 #define IRQ_MST_ENABLE          (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
  68 #define IRQ_ALL_DISABLE         0
  69
  70 /* interrupt pending register */
  71 #define I2C_IPD                 0x01c
  72 #define I2C_BTFIPD              (1 << 0)
  73 #define I2C_BRFIPD              (1 << 1)
  74 #define I2C_MBTFIPD             (1 << 2)
  75 #define I2C_MBRFIPD             (1 << 3)
  76 #define I2C_STARTIPD            (1 << 4)
  77 #define I2C_STOPIPD             (1 << 5)
  78 #define I2C_NAKRCVIPD           (1 << 6)
  79 #define I2C_IPD_ALL_CLEAN       0x7f
  80
  81 /* finished count */
  82 #define I2C_FCNT                0x020
  83
  84 /* I2C tx data register */
  85 #define I2C_TXDATA_BASE         0X100
  86
  87 /* I2C rx data register */
  88 #define I2C_RXDATA_BASE         0x200
  89
  90
  91 static void rk30_show_regs(struct rk30_i2c *i2c)
  92 {
  93         int i;
  94         dev_info(i2c->dev, "i2c->clk = %lu\n", clk_get_rate(i2c->clk));
  95         dev_info(i2c->dev, "i2c->start = %d\n", i2c->state);
  96         dev_info(i2c->dev, "I2C_CON: 0x%08x\n", i2c_readl(i2c->regs + I2C_CON));
  97         dev_info(i2c->dev, "I2C_CLKDIV: 0x%08x\n", i2c_readl(i2c->regs + I2C_CLKDIV));
  98         dev_info(i2c->dev, "I2C_MRXADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXADDR));
  99         dev_info(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXRADDR));
 100         dev_info(i2c->dev, "I2C_MTXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MTXCNT));
 101         dev_info(i2c->dev, "I2C_MRXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXCNT));
 102         dev_info(i2c->dev, "I2C_IEN: 0x%08x\n", i2c_readl(i2c->regs + I2C_IEN));
 103         dev_info(i2c->dev, "I2C_IPD: 0x%08x\n", i2c_readl(i2c->regs + I2C_IPD));
 104         dev_info(i2c->dev, "I2C_FCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_FCNT));
 105         for( i = 0; i < 8; i ++)
 106                 dev_info(i2c->dev, "I2C_TXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_TXDATA_BASE + i * 4));
 107         for( i = 0; i < 8; i ++)
 108                 dev_info(i2c->dev, "I2C_RXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_RXDATA_BASE + i * 4));
 109 }
 110 static inline void rk30_i2c_enable(struct rk30_i2c *i2c, unsigned int lastnak)
 111 {
 112         unsigned int con = 0;
 113
 114         con |= I2C_CON_EN;
 115         con |= I2C_CON_MOD(i2c->mode);
 116         if(lastnak)
 117                 con |= I2C_CON_LASTACK;
 118         con |= I2C_CON_START;
 119         i2c_writel(con, i2c->regs + I2C_CON);
 120 }
 121 static inline void rk30_i2c_disable(struct rk30_i2c *i2c)
 122 {
 123         i2c_writel( 0, i2c->regs + I2C_CON);
 124 }
 125
 126 static inline void rk30_i2c_clean_start(struct rk30_i2c *i2c)
 127 {
 128         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 129
 130         con &= ~I2C_CON_START;
 131         i2c_writel(con, i2c->regs + I2C_CON);
 132 }
 133 static inline void rk30_i2c_send_start(struct rk30_i2c *i2c)
 134 {
 135         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 136
 137         con |= I2C_CON_START;
 138         if(con & I2C_CON_STOP)
 139                 dev_warn(i2c->dev, "I2C_CON: stop bit is set\n");
 140
 141         i2c_writel(con, i2c->regs + I2C_CON);
 142 }
 143 static inline void rk30_i2c_send_stop(struct rk30_i2c *i2c)
 144 {
 145         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 146
 147         con |= I2C_CON_STOP;
 148         if(con & I2C_CON_START)
 149                 dev_warn(i2c->dev, "I2C_CON: start bit is set\n");
 150
 151         i2c_writel(con, i2c->regs + I2C_CON);
 152 }
 153 static inline void rk30_i2c_clean_stop(struct rk30_i2c *i2c)
 154 {
 155         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 156
 157         con &= ~I2C_CON_STOP;
 158         i2c_writel(con, i2c->regs + I2C_CON);
 159 }
 160
 161 static inline void rk30_i2c_disable_irq(struct rk30_i2c *i2c)
 162 {
 163         i2c_writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
 164 }
 165
 166 static inline void rk30_i2c_enable_irq(struct rk30_i2c *i2c)
 167 {
 168         i2c_writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
 169 }
 170
 171 /* SCL Divisor = 8 * (CLKDIVL + CLKDIVH)
 172  * SCL = i2c_rate/ SCLK Divisor
 173 */
 174 static void  rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
 175 {
 176         unsigned long i2c_rate = clk_get_rate(i2c->clk);
 177
 178         unsigned int div, divl, divh;
 179
 180         if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
 181                 return;
 182         i2c->i2c_rate = i2c_rate;
 183         i2c->scl_rate = scl_rate;
 184         div = rk30_ceil(i2c_rate, scl_rate * 8);
 185         divh = divl = rk30_ceil(div, 2);
 186         i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
 187         i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV));
 188         return;
 189 }
 190 static void rk30_i2c_init_hw(struct rk30_i2c *i2c, unsigned long scl_rate)
 191 {
 192         i2c->scl_rate = 0;
 193         rk30_i2c_set_clk(i2c, scl_rate);
 194         return;
 195 }
 196 /* returns TRUE if we this is the last byte in the current message */
 197 static inline int is_msglast(struct rk30_i2c *i2c)
 198 {
 199         return i2c->msg_ptr == i2c->msg->len-1;
 200 }
 201
 202 /* returns TRUE if we reached the end of the current message */
 203 static inline int is_msgend(struct rk30_i2c *i2c)
 204 {
 205         return i2c->msg_ptr >= i2c->msg->len;
 206 }
 207
 208 static void rk30_i2c_stop(struct rk30_i2c *i2c, int ret)
 209 {
 210
 211         i2c->msg_ptr = 0;
 212         i2c->msg = NULL;
 213         if(ret == -EAGAIN){
 214                 i2c->state = STATE_IDLE;
 215                 i2c->is_busy = 0;
 216                 wake_up(&i2c->wait);
 217                 return;
 218         }
 219         i2c->error = ret;
 220         i2c_writel(I2C_STOPIEN, i2c->regs + I2C_IEN);
 221         i2c->state = STATE_STOP;
 222         rk30_i2c_send_stop(i2c);
 223         return;
 224 }
 225 static inline void rk30_set_rx_mode(struct rk30_i2c *i2c, unsigned int lastnak)
 226 {
 227         unsigned long con = i2c_readl(i2c->regs + I2C_CON);
 228
 229         con &= (~I2C_CON_MASK);
 230         con |= (I2C_CON_MOD_RX << 1);
 231         if(lastnak)
 232                 con |= I2C_CON_LASTACK;
 233         i2c_writel(con, i2c->regs + I2C_CON);
 234 }
 235 static void rk30_irq_read_prepare(struct rk30_i2c *i2c)
 236 {
 237     unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
 238
 239     if(len <= 32 && i2c->msg_ptr != 0)
 240             rk30_set_rx_mode(i2c, 1);
 241     else if(i2c->msg_ptr != 0)
 242             rk30_set_rx_mode(i2c, 0);
 243
 244     if(is_msgend(i2c)) {
 245         rk30_i2c_stop(i2c, i2c->error);
 246         return;
 247     }
 248     if(len > 32)
 249         cnt = 32;
 250     else
 251         cnt = len;
 252     i2c_writel(cnt, i2c->regs + I2C_MRXCNT);
 253 }
 254 static void rk30_irq_read_get_data(struct rk30_i2c *i2c)
 255 {
 256      unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
 257      unsigned int p;
 258
 259      len = (len >= 32)?32:len;
 260
 261      for(i = 0; i < len; i++){
 262          if(i%4 == 0)
 263              p = i2c_readl(i2c->regs + I2C_RXDATA_BASE +  (i/4) * 4);
 264          i2c->msg->buf[i2c->msg_ptr++] = (p >>((i%4) * 8)) & 0xff;
 265     }
 266
 267      return;
 268 }
 269 static void rk30_irq_write_prepare(struct rk30_i2c *i2c)
 270 {
 271     unsigned int data = 0, cnt = 0, i, j;
 272     unsigned char byte;
 273
 274     if(is_msgend(i2c)) {
 275         rk30_i2c_stop(i2c, i2c->error);
 276         return;
 277     }
 278     for(i = 0; i < 8; i++){
 279         data = 0;
 280         for(j = 0; j < 4; j++) {
 281             if(is_msgend(i2c))
 282                 break;
 283             if(i2c->msg_ptr == 0 && cnt == 0)
 284                 byte = (i2c->addr & 0x7f) << 1;
 285             else
 286                 byte =  i2c->msg->buf[i2c->msg_ptr++];
 287             cnt++;
 288             data |= (byte << (j * 8));
 289         }
 290         i2c_writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
 291         if(is_msgend(i2c))
 292             break;
 293     }
 294     i2c_writel(cnt, i2c->regs + I2C_MTXCNT);
 295 }
 296 static void rk30_i2c_irq_nextblock(struct rk30_i2c *i2c, unsigned int ipd)
 297 {
 298         switch (i2c->state) {
 299         case STATE_START:
 300                 if(!(ipd & I2C_STARTIPD)){
 301                         rk30_i2c_stop(i2c, -ENXIO);
 302                         dev_err(i2c->dev, "Addr[0x%02x] no start irq in STATE_START\n", i2c->addr);
 303                         rk30_show_regs(i2c);
 304                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 305                         goto out;
 306                 }
 307                 i2c->complete_what |= 1<<i2c->state;
 308                 i2c_writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
 309                 rk30_i2c_clean_start(i2c);
 310                 if(i2c->mode ==  I2C_CON_MOD_TX){
 311                         i2c_writel(I2C_MBTFIEN  | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
 312                         i2c->state = STATE_WRITE;
 313                         goto prepare_write;
 314                 } else {
 315                         i2c_writel(I2C_MBRFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
 316                         i2c->state = STATE_READ;
 317                         goto prepare_read;
 318                 }
 319         case STATE_WRITE:
 320                 if(!(ipd & I2C_MBTFIPD)){
 321                         rk30_i2c_stop(i2c, -ENXIO);
 322                         dev_err(i2c->dev, "Addr[0x%02x] no mbtf irq in STATE_WRITE\n", i2c->addr);
 323                         rk30_show_regs(i2c);
 324                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 325                         goto out;
 326                 }
 327                 i2c->complete_what |= 1<<i2c->state;
 328                 i2c_writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
 329 prepare_write:
 330                 rk30_irq_write_prepare(i2c);
 331                 break;
 332         case STATE_READ:
 333                 if(!(ipd & I2C_MBRFIPD)){
 334                         rk30_i2c_stop(i2c, -ENXIO);
 335                         dev_err(i2c->dev, "Addr[0x%02x] no mbrf irq in STATE_READ, ipd = 0x%x\n", i2c->addr, ipd);
 336                         rk30_show_regs(i2c);
 337                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 338                         goto out;
 339                 }
 340                 i2c->complete_what |= 1<<i2c->state;
 341                 i2c_writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
 342                 rk30_irq_read_get_data(i2c);
 343 prepare_read:
 344                 rk30_irq_read_prepare(i2c);
 345                 break;
 346         case STATE_STOP:
 347                 if(!(ipd & I2C_STOPIPD)){
 348                         rk30_i2c_stop(i2c, -ENXIO);
 349                         dev_err(i2c->dev, "Addr[0x%02x] no stop irq in STATE_STOP\n", i2c->addr);
 350                         rk30_show_regs(i2c);
 351                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 352                         goto out;
 353                 }
 354                 rk30_i2c_clean_stop(i2c);
 355                 i2c_writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
 356                 i2c->is_busy = 0;
 357                 i2c->complete_what |= 1<<i2c->state;
 358                 i2c->state = STATE_IDLE;
 359                 wake_up(&i2c->wait);
 360                 break;
 361         default:
 362                 break;
 363         }
 364 out:
 365         return;
 366 }
 367 static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
 368 {
 369         struct rk30_i2c *i2c = dev_id;
 370         unsigned int ipd;
 371
 372         spin_lock(&i2c->lock);
 373         ipd = i2c_readl(i2c->regs + I2C_IPD);
 374         if(i2c->state == STATE_IDLE){
 375                 dev_info(i2c->dev, "Addr[0x%02x]  irq in STATE_IDLE, ipd = 0x%x\n", i2c->addr, ipd);
 376                 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 377                 goto out;
 378         }
 379
 380         if(ipd & I2C_NAKRCVIPD){
 381                 i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
 382                 i2c->error = -EAGAIN;
 383                 goto out;
 384         }
 385         rk30_i2c_irq_nextblock(i2c, ipd);
 386 out:
 387         spin_unlock(&i2c->lock);
 388         return IRQ_HANDLED;
 389 }
 390
 391
 392 static int rk30_i2c_set_master(struct rk30_i2c *i2c, struct i2c_msg *msgs, int num)
 393 {
 394         unsigned int addr = (msgs[0].addr & 0x7f) << 1;
 395         unsigned int reg_valid_bits = 0;
 396         unsigned int reg_addr = 0;
 397
 398         if(num == 1) {
 399                 i2c->count = msgs[0].len;
 400                 if(!(msgs[0].flags & I2C_M_RD)){
 401                         i2c->msg = &msgs[0];
 402                         i2c->mode = I2C_CON_MOD_TX;
 403                 }
 404                 else {
 405                         addr |= 1;
 406                         i2c->msg = &msgs[0];
 407                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 408                         i2c_writel(0, i2c->regs + I2C_MRXRADDR);
 409                         i2c->mode = I2C_CON_MOD_TRX;
 410                         //i2c->mode = I2C_CON_MOD_RX;
 411                 }
 412         }
 413         else if(num == 2) {
 414                 i2c->count = msgs[1].len;
 415                 switch(msgs[0].len){
 416                 case 1:
 417                         reg_addr = msgs[0].buf[0];
 418                         reg_valid_bits |= I2C_MRXADDR_LOW;
 419                         break;
 420                 case 2:
 421                         reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
 422                         reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
 423                         break;
 424                 case 3:
 425                         reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
 426                         reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
 427                         break;
 428                 default:
 429                         return -EIO;
 430                 }
 431                 if((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 432                         addr |= 1;
 433                         i2c->msg = &msgs[1];
 434                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 435                         i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 436                         i2c->mode = I2C_CON_MOD_RRX;
 437                 }
 438                 else if(!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 439                         i2c->msg = &msgs[1];
 440                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 441                         i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 442                         i2c->mode = I2C_CON_MOD_TRX;
 443                 }
 444                 else
 445                         return -EIO;
 446         }
 447         else {
 448                 dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
 449                 return -EIO;
 450         }
 451
 452         return 0;
 453 }
 454 /* rk30_i2c_doxfer
 455  *
 456  * this starts an i2c transfer
 457 */
 458 static int rk30_i2c_doxfer(struct rk30_i2c *i2c,
 459                               struct i2c_msg *msgs, int num)
 460 {
 461         unsigned long timeout, flags;
 462         int error = 0;
 463         /* 32 -- max transfer bytes
 464          * 2 -- addr bytes * 2
 465          * 3 -- max reg addr bytes
 466          * 9 -- cycles per bytes
 467          * max cycles: (32 + 2 + 3) * 9 --> 400 cycles
 468          */
 469         int msleep_time = 400 * 1000/ i2c->scl_rate; // ms
 470
 471         if (i2c->suspended){
 472                 dev_err(i2c->dev, "i2c is suspended\n");
 473                 return -EIO;
 474         }
 475
 476         spin_lock_irqsave(&i2c->lock, flags);
 477         if(rk30_i2c_set_master(i2c, msgs, num) < 0){
 478                 spin_unlock_irqrestore(&i2c->lock, flags);
 479                 dev_err(i2c->dev, "addr[0x%02x] set master error\n", msgs[0].addr);
 480                 return -EIO;
 481         }
 482         i2c->addr = msgs[0].addr;
 483         i2c->msg_ptr = 0;
 484         i2c->error = 0;
 485         i2c->is_busy = 1;
 486         i2c->state = STATE_START;
 487         i2c->complete_what = 0;
 488         i2c_writel(I2C_STARTIEN, i2c->regs + I2C_IEN);
 489         spin_unlock_irqrestore(&i2c->lock, flags);
 490
 491         rk30_i2c_enable(i2c, (i2c->count > 32)?0:1); //if count > 32,  byte(32) send ack
 492
 493         timeout = wait_event_timeout(i2c->wait, (i2c->is_busy == 0), msecs_to_jiffies(I2C_WAIT_TIMEOUT));
 494
 495         spin_lock_irqsave(&i2c->lock, flags);
 496         i2c->state = STATE_IDLE;
 497         error = i2c->error;
 498         spin_unlock_irqrestore(&i2c->lock, flags);
 499
 500         if (timeout == 0){
 501                 if(error < 0)
 502                         i2c_dbg(i2c->dev, "error = %d\n", error);
 503                 else if((i2c->complete_what !=COMPLETE_READ  && i2c->complete_what != COMPLETE_WRITE)){
 504                         dev_err(i2c->dev, "Addr[0x%02x] wait event timeout, state: %d, is_busy: %d, error: %d, complete_what: 0x%x, ipd: 0x%x\n",
 505                                 msgs[0].addr, i2c->state, i2c->is_busy, error, i2c->complete_what, i2c_readl(i2c->regs + I2C_IPD));
 506                         //rk30_show_regs(i2c);
 507                         error = -ETIMEDOUT;
 508                         msleep(msleep_time);
 509                         rk30_i2c_send_stop(i2c);
 510                         msleep(1);
 511                 }
 512                 else
 513                         i2c_dbg(i2c->dev, "Addr[0x%02x] wait event timeout, but transfer complete\n", i2c->addr);
 514         }
 515         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 516         rk30_i2c_disable_irq(i2c);
 517         rk30_i2c_disable(i2c);
 518
 519         if(error == -EAGAIN)
 520                 i2c_dbg(i2c->dev, "No ack(complete_what: 0x%x), Maybe slave(addr: 0x%02x) not exist or abnormal power-on\n",
 521                                 i2c->complete_what, i2c->addr);
 522         return error;
 523 }
 524
 525 /* rk30_i2c_xfer
 526  *
 527  * first port of call from the i2c bus code when an message needs
 528  * transferring across the i2c bus.
 529 */
 530
 531 static int rk30_i2c_xfer(struct i2c_adapter *adap,
 532                         struct i2c_msg *msgs, int num)
 533 {
 534         int ret = 0, state, retry = 10;
 535         unsigned long scl_rate;
 536         struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 537
 538         clk_enable(i2c->clk);
 539         while(retry-- && ((state = i2c->check_idle()) != I2C_IDLE)){
 540                 msleep(10);
 541         }
 542         if(retry == 0){
 543                 dev_err(i2c->dev, "i2c is not in idle(state = %d)\n", state);
 544                 return -EIO;
 545         }
 546
 547         if(msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
 548                 scl_rate = msgs[0].scl_rate;
 549         else if(msgs[0].scl_rate > 400000){
 550                 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too high!",
 551                         msgs[0].addr, msgs[0].scl_rate/1000);
 552                 scl_rate = 400000;
 553         }
 554         else{
 555                 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too low!",
 556                         msgs[0].addr, msgs[0].scl_rate/1000);
 557                 scl_rate = 10000;
 558         }
 559         if(i2c->is_div_from_arm[i2c->adap.nr]){
 560                 mutex_lock(&i2c->m_lock);
 561                 wake_lock(&i2c->idlelock[i2c->adap.nr]);
 562         }
 563
 564         rk30_i2c_set_clk(i2c, scl_rate);
 565         i2c_dbg(i2c->dev, "i2c transfer start: addr: 0x%x, scl_reate: %ldKhz, len: %d\n", msgs[0].addr, scl_rate/1000, num);
 566         ret = rk30_i2c_doxfer(i2c, msgs, num);
 567         i2c_dbg(i2c->dev, "i2c transfer stop: addr: 0x%x, state: %d, ret: %d\n", msgs[0].addr, ret, i2c->state);
 568
 569         if(i2c->is_div_from_arm[i2c->adap.nr]){
 570                 wake_unlock(&i2c->idlelock[i2c->adap.nr]);
 571                 mutex_unlock(&i2c->m_lock);
 572         }
 573
 574         clk_disable(i2c->clk);
 575         return (ret < 0)?ret:num;
 576 }
 577
 578 /* declare our i2c functionality */
 579 static u32 rk30_i2c_func(struct i2c_adapter *adap)
 580 {
 581         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 582 }
 583
 584 /* i2c bus registration info */
 585
 586 static const struct i2c_algorithm rk30_i2c_algorithm = {
 587         .master_xfer            = rk30_i2c_xfer,
 588         .functionality          = rk30_i2c_func,
 589 };
 590
 591 int i2c_add_rk30_adapter(struct i2c_adapter *adap)
 592 {
 593         int ret = 0;
 594         struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 595
 596         adap->algo = &rk30_i2c_algorithm;
 597
 598         i2c->i2c_init_hw = &rk30_i2c_init_hw;
 599         i2c->i2c_set_clk = &rk30_i2c_set_clk;
 600         i2c->i2c_irq = &rk30_i2c_irq;
 601
 602         ret = i2c_add_numbered_adapter(adap);
 603
 604         return ret;
 605 }
 606