drivers/i2c/busses/i2c-rk30-adapter.c

   1 /* drivers/i2c/busses/i2c-rk30-adapter.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include "i2c-rk30.h"
  16
  17 /* Control register */
  18 #define I2C_CON         0X000
  19 enum{
  20     I2C_EN_BIT  = 0,
  21     I2C_MOD_BIT = 1,
  22     I2C_START_BIT = 3,
  23     I2C_STOP_BIT = 4,
  24     I2C_LAST_ACK_BIT = 5,
  25     I2C_ACT2ACK_BIT = 6,
  26 };
  27 //send ACK to slave when the last byte received in RX only mode
  28 #define LAST_SEND_ACK   0
  29 //send NAK to slave when the last byte received in RX only mode
  30 #define LAST_SEND_NAK   1
  31 #define LAST_SEND_TYPE  LAST_SEND_ACK //LAST_SEND_NAK
  32
  33 #define I2C_MOD_MASK    (3 << I2C_MOD_BIT)
  34 enum{
  35     I2C_MOD_TX = 0,
  36     I2C_MOD_TRX,
  37     I2C_MOD_RX,
  38     I2C_MOD_RRX,
  39 };
  40 /* Clock dividor register */
  41 #define I2C_CLKDIV      0x004
  42 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
  43 /* the slave address accessed  for master rx mode */
  44 #define I2C_MRXADDR     0x008
  45 #define I2C_MRXADDR_LOW     (1 << 24)
  46 #define I2C_MRXADDR_MID     (1 << 25)
  47 #define I2C_MRXADDR_HIGH     (1 << 26)
  48 /* the slave register address accessed  for master rx mode */
  49 #define I2C_MRXRADDR    0x00c
  50 #define I2C_MRXRADDR_LOW     (1 << 24)
  51 #define I2C_MRXRADDR_MID     (1 << 25)
  52 #define I2C_MRXRADDR_HIGH     (1 << 26)
  53 /* master tx count */
  54 #define I2C_MTXCNT      0x010
  55 /* master rx count */
  56 #define I2C_MRXCNT      0x014
  57 /* interrupt enable register */
  58 #define I2C_IEN         0x018
  59 #define I2C_BTFIEN  (1 << 0)
  60 #define I2C_BRFIEN  (1 << 1)
  61 #define I2C_MBTFIEN  (1 << 2)
  62 #define I2C_MBRFIEN  (1 << 3)
  63 #define I2C_STARTIEN  (1 << 4)
  64 #define I2C_STOPIEN  (1 << 5)
  65 #define I2C_NAKRCVIEN  (1 << 6)
  66 #define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
  67 #define IRQ_ALL_DISABLE 0
  68 /* interrupt pending register */
  69 #define I2C_IPD         0x01c
  70 #define I2C_BTFIPD  (1 << 0)
  71 #define I2C_BRFIPD  (1 << 1)
  72 #define I2C_MBTFIPD  (1 << 2)
  73 #define I2C_MBRFIPD  (1 << 3)
  74 #define I2C_STARTIPD  (1 << 4)
  75 #define I2C_STOPIPD  (1 << 5)
  76 #define I2C_NAKRCVIPD  (1 << 6)
  77 /* finished count */
  78 #define I2C_FCNT        0x020
  79 /* I2C tx data register */
  80 #define I2C_TXDATA_BASE 0X100
  81 /* I2C rx data register */
  82 #define I2C_RXDATA_BASE 0x200
  83 static void rk30_show_regs(struct rk30_i2c *i2c)
  84 {
  85     i2c_dbg(i2c->dev, "I2C_CON: 0x%08x\n", readl(i2c->regs + I2C_CON));
  86     i2c_dbg(i2c->dev, "I2C_CLKDIV: 0x%08x\n", readl(i2c->regs + I2C_CLKDIV));
  87     i2c_dbg(i2c->dev, "I2C_MRXADDR: 0x%08x\n", readl(i2c->regs + I2C_MRXADDR));
  88     i2c_dbg(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", readl(i2c->regs + I2C_MRXRADDR));
  89     i2c_dbg(i2c->dev, "I2C_MTXCNT: 0x%08x\n", readl(i2c->regs + I2C_MTXCNT));
  90     i2c_dbg(i2c->dev, "I2C_MRXCNT: 0x%08x\n", readl(i2c->regs + I2C_MRXCNT));
  91     i2c_dbg(i2c->dev, "I2C_IEN: 0x%08x\n", readl(i2c->regs + I2C_IEN));
  92     i2c_dbg(i2c->dev, "I2C_IPD: 0x%08x\n", readl(i2c->regs + I2C_IPD));
  93     i2c_dbg(i2c->dev, "I2C_FCNT: 0x%08x\n", readl(i2c->regs + I2C_FCNT));
  94     i2c_dbg(i2c->dev, "I2C_TXDATA0: 0x%08x\n", readl(i2c->regs + I2C_TXDATA_BASE + 0));
  95     i2c_dbg(i2c->dev, "I2C_RXDATA0: 0x%08x\n", readl(i2c->regs + I2C_RXDATA_BASE + 0));
  96 }
  97 static inline void rk30_i2c_last_ack(struct rk30_i2c *i2c, int enable)
  98 {
  99     unsigned int p = readl(i2c->regs + I2C_CON);
 100
 101     writel(rk30_set_bit(p, enable, I2C_LAST_ACK_BIT), i2c->regs + I2C_CON);
 102 }
 103 static inline void rk30_i2c_act2ack(struct rk30_i2c *i2c, int enable)
 104 {
 105     unsigned int p = readl(i2c->regs + I2C_CON);
 106
 107     writel(rk30_set_bit(p, enable, I2C_ACT2ACK_BIT), i2c->regs + I2C_CON);
 108 }
 109 static inline void rk30_i2c_enable(struct rk30_i2c *i2c, int enable)
 110 {
 111     unsigned int p = readl(i2c->regs + I2C_CON);
 112
 113     writel(rk30_set_bit(p, enable, I2C_EN_BIT), i2c->regs + I2C_CON);
 114 }
 115 static inline void rk30_i2c_set_mode(struct rk30_i2c *i2c)
 116 {
 117     unsigned int p = readl(i2c->regs + I2C_CON);
 118
 119     writel(rk30_set_bits(p, i2c->mode, I2C_MOD_BIT, I2C_MOD_MASK), i2c->regs + I2C_CON);
 120 }
 121 static inline void rk30_i2c_disable_irq(struct rk30_i2c *i2c)
 122 {
 123     writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
 124 }
 125
 126 static inline void rk30_i2c_enable_irq(struct rk30_i2c *i2c)
 127 {
 128     writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
 129 }
 130
 131 static inline void rk30_i2c_send_start(struct rk30_i2c *i2c)
 132 {
 133     unsigned int p = readl(i2c->regs + I2C_CON);
 134
 135     p = rk30_set_bit(p, 1, I2C_START_BIT);
 136     p = rk30_set_bit(p, 0, I2C_STOP_BIT);
 137     writel(p, i2c->regs + I2C_CON);
 138 }
 139 static inline void rk30_i2c_send_stop(struct rk30_i2c *i2c)
 140 {
 141     unsigned int p = readl(i2c->regs + I2C_CON);
 142
 143     p = rk30_set_bit(p, 0, I2C_START_BIT);
 144     p = rk30_set_bit(p, 1, I2C_STOP_BIT);
 145     writel(p, i2c->regs + I2C_CON);
 146
 147 }
 148 /* SCL Divisor = 8 * (CLKDIVL + CLKDIVH)
 149  * SCL = i2c_rate/ SCLK Divisor
 150 */
 151 static void  rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
 152 {
 153     unsigned long i2c_rate = clk_get_rate(i2c->clk);
 154
 155     unsigned int div, divl, divh;
 156
 157     if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
 158         return;
 159     i2c->i2c_rate = i2c_rate;
 160     i2c->scl_rate = scl_rate;
 161     div = rk30_ceil(i2c_rate, scl_rate * 8);
 162     divh = divl = rk30_ceil(div, 2);
 163     i2c_dbg(i2c->dev, "div divh divl: %d %d %d\n", div, divh, divl);
 164     writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
 165     return;
 166 }
 167 static void rk30_i2c_init_hw(struct rk30_i2c *i2c, unsigned long scl_rate)
 168 {
 169     rk30_i2c_set_clk(i2c, scl_rate);
 170         return;
 171 }
 172 /* returns TRUE if we this is the last byte in the current message */
 173 static inline int is_msglast(struct rk30_i2c *i2c)
 174 {
 175         return i2c->msg_ptr == i2c->msg->len-1;
 176 }
 177
 178 /* returns TRUE if we reached the end of the current message */
 179 static inline int is_msgend(struct rk30_i2c *i2c)
 180 {
 181         return i2c->msg_ptr >= i2c->msg->len;
 182 }
 183
 184 static void rk30_i2c_stop(struct rk30_i2c *i2c, int ret)
 185 {
 186
 187     i2c->msg_ptr = 0;
 188         i2c->msg = NULL;
 189         i2c->msg_idx++;
 190         i2c->msg_num = 0;
 191         if (ret)
 192                 i2c->msg_idx = ret;
 193
 194     i2c->state = STATE_STOP;
 195     rk30_i2c_send_stop(i2c);
 196 }
 197 static void rk30_irq_read_prepare(struct rk30_i2c *i2c)
 198 {
 199     unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
 200
 201     if(is_msgend(i2c)) {
 202         rk30_i2c_stop(i2c, 0);
 203         return;
 204     }
 205     if(len > 32)
 206         cnt = 32;
 207     else
 208         cnt = len;
 209
 210     writel(cnt, i2c->regs + I2C_MRXCNT);
 211 }
 212 static void rk30_irq_read_get_data(struct rk30_i2c *i2c)
 213 {
 214      unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
 215      unsigned int p;
 216
 217      len = (len >= 32)?32:len;
 218
 219      for(i = 0; i < len; i++){
 220          if(i%4 == 0)
 221              p = readl(i2c->regs + I2C_RXDATA_BASE +  (i/4) * 4);
 222          i2c->msg->buf[i2c->msg_ptr++] = (p >>((i%4) * 8)) & 0xff;
 223     }
 224
 225      return;
 226 }
 227 static void rk30_irq_write_prepare(struct rk30_i2c *i2c)
 228 {
 229     unsigned int data = 0, cnt = 0, i, j;
 230     unsigned char byte;
 231
 232     if(is_msgend(i2c)) {
 233         rk30_i2c_stop(i2c, 0);
 234         return;
 235     }
 236     for(i = 0; i < 8; i++){
 237         data = 0;
 238         for(j = 0; j < 4; j++) {
 239             if(is_msgend(i2c))
 240                 break;
 241             if(i2c->msg_ptr == 0 && cnt == 0)
 242                 byte = (i2c->addr & 0x7f) << 1;
 243             else
 244                 byte =  i2c->msg->buf[i2c->msg_ptr++];
 245             cnt++;
 246             data |= (byte << (j * 8));
 247         }
 248         writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
 249         if(is_msgend(i2c))
 250             break;
 251     }
 252     writel(cnt, i2c->regs + I2C_MTXCNT);
 253 }
 254 static void rk30_i2c_irq_nextblock(struct rk30_i2c *i2c, unsigned int ipd)
 255 {
 256     switch (i2c->state) {
 257         case STATE_IDLE:
 258                 dev_err(i2c->dev, "Addr[0x%02x] called in STATE_IDLE\n", i2c->addr);
 259                 goto out;
 260     case STATE_START:
 261         if(!(ipd & I2C_STARTIPD)){
 262             if(ipd & I2C_STOPIPD){
 263                 writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
 264             }
 265             else {
 266                 rk30_i2c_stop(i2c, -ENXIO);
 267                             dev_err(i2c->dev, "Addr[0x%02x] no start irq in STATE_START\n", i2c->addr);
 268                 rk30_show_regs(i2c);
 269             }
 270             goto out;
 271         }
 272         writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
 273         if(i2c->mode ==  I2C_MOD_TX){
 274             i2c->state = STATE_WRITE;
 275             goto prepare_write;
 276         }
 277         else {
 278              i2c->state = STATE_READ;
 279              goto prepare_read;
 280         }
 281     case STATE_WRITE:
 282         if(!(ipd & I2C_MBTFIPD)){
 283             goto out;
 284         }
 285         writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
 286 prepare_write:
 287         rk30_irq_write_prepare(i2c);
 288         break;
 289     case STATE_READ:
 290         if(!(ipd & I2C_MBRFIPD)){
 291             goto out;
 292         }
 293         writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
 294         rk30_irq_read_get_data(i2c);
 295 prepare_read:
 296         rk30_irq_read_prepare(i2c);
 297         break;
 298     case STATE_STOP:
 299         if(ipd & I2C_STOPIPD){
 300             writel(0xff, i2c->regs + I2C_IPD);
 301             i2c->state = STATE_IDLE;
 302                 rk30_i2c_disable_irq(i2c);
 303                 wake_up(&i2c->wait);
 304         }
 305         break;
 306     default:
 307         break;
 308     }
 309 out:
 310     return;
 311 }
 312 static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
 313 {
 314     struct rk30_i2c *i2c = dev_id;
 315     unsigned int ipd;
 316     spin_lock(&i2c->lock);
 317     ipd = readl(i2c->regs + I2C_IPD);
 318
 319     if(ipd & I2C_NAKRCVIPD) {
 320         writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
 321         rk30_i2c_stop(i2c, -EAGAIN);
 322                 dev_err(i2c->dev, "Addr[0x%02x] ack was not received\n", i2c->addr);
 323         rk30_show_regs(i2c);
 324         goto out;
 325     }
 326
 327     rk30_i2c_irq_nextblock(i2c, ipd);
 328 out:
 329     spin_unlock(&i2c->lock);
 330         return IRQ_HANDLED;
 331 }
 332
 333
 334 static int rk30_i2c_set_master(struct rk30_i2c *i2c, struct i2c_msg *msgs, int num)
 335 {
 336     unsigned int addr = (msgs[0].addr & 0x7f) << 1;
 337     unsigned int reg_valid_bits = 0;
 338     unsigned int reg_addr = 0;
 339
 340     if(num == 1) {
 341         if(!(msgs[0].flags & I2C_M_RD)){
 342                 i2c->msg = &msgs[0];
 343             i2c->mode = I2C_MOD_TX;
 344         }
 345         else {
 346             addr |= 1;
 347                 i2c->msg = &msgs[0];
 348             writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 349             i2c->mode = I2C_MOD_RX;
 350         }
 351     }
 352     else if(num == 2) {
 353         switch(msgs[0].len){
 354             case 1:
 355                 reg_addr = msgs[0].buf[0];
 356                 reg_valid_bits |= I2C_MRXADDR_LOW;
 357                 break;
 358             case 2:
 359                 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
 360                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
 361                 break;
 362             case 3:
 363                 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
 364                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
 365                 break;
 366             default:
 367                 return -EIO;
 368         }
 369         if((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 370             addr |= 1;
 371                 i2c->msg = &msgs[1];
 372             writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 373             writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 374             i2c->mode = I2C_MOD_RRX;
 375         }
 376         else if(!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 377                 i2c->msg = &msgs[1];
 378             writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 379             writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 380             i2c->mode = I2C_MOD_TRX;
 381         }
 382         else
 383             return -EIO;
 384     }
 385     else {
 386         dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
 387         return -EIO;
 388     }
 389     rk30_i2c_set_mode(i2c);
 390     rk30_i2c_last_ack(i2c, LAST_SEND_TYPE);
 391     if(msgs[0].flags & I2C_M_IGNORE_NAK)
 392         rk30_i2c_act2ack(i2c, 0);
 393     else
 394         rk30_i2c_act2ack(i2c, 1);
 395
 396     return 0;
 397 }
 398 /* rk30_i2c_doxfer
 399  *
 400  * this starts an i2c transfer
 401 */
 402 static int rk30_i2c_doxfer(struct rk30_i2c *i2c,
 403                               struct i2c_msg *msgs, int num)
 404 {
 405         unsigned long timeout;
 406         int ret = 0;
 407
 408         if (i2c->suspended)
 409                 return -EIO;
 410
 411         ret = rk30_i2c_set_master(i2c, msgs, num);
 412         if (ret != 0) {
 413         dev_err(i2c->dev, "addr[0x%02x] set master error\n", msgs[0].addr);
 414         return ret;
 415     }
 416         spin_lock_irq(&i2c->lock);
 417
 418     i2c->addr = msgs[0].addr;
 419         i2c->msg_num = num;
 420     i2c->msg_ptr = 0;
 421     i2c->msg_idx = 0;
 422     i2c->state = STATE_START;
 423
 424         spin_unlock_irq(&i2c->lock);
 425
 426         rk30_i2c_enable_irq(i2c);
 427     rk30_i2c_send_start(i2c);
 428
 429         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, msecs_to_jiffies(I2C_WAIT_TIMEOUT));
 430
 431         ret = i2c->msg_idx;
 432
 433         if (timeout == 0){
 434         dev_err(i2c->dev, "addr[0x%02x] wait event timeout, state = %d\n", msgs[0].addr, i2c->state);
 435         rk30_show_regs(i2c);
 436         writel(0xff, i2c->regs + I2C_IPD);
 437             rk30_i2c_disable_irq(i2c);
 438         rk30_i2c_send_stop(i2c);
 439         if(ret >= 0)
 440             ret = -ETIMEDOUT;
 441         return ret;
 442     }
 443     if(ret > 0)
 444         ret = num;
 445         return ret;
 446 }
 447
 448 /* rk30_i2c_xfer
 449  *
 450  * first port of call from the i2c bus code when an message needs
 451  * transferring across the i2c bus.
 452 */
 453
 454 static int rk30_i2c_xfer(struct i2c_adapter *adap,
 455                         struct i2c_msg *msgs, int num)
 456 {
 457         int ret = 0;
 458     unsigned long scl_rate;
 459         struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 460
 461     if(msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
 462                 scl_rate = msgs[0].scl_rate;
 463         else if(msgs[0].scl_rate > 400000){
 464                 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too high!",
 465                         msgs[0].addr, msgs[0].scl_rate/1000);
 466                 scl_rate = 400000;
 467         }
 468         else{
 469                 dev_warn(i2c->dev, "Warning: addr[0x%x] msg[0].scl_rate( = %dKhz) is too low!",
 470                         msgs[0].addr, msgs[0].scl_rate/1000);
 471                 scl_rate = 10000;
 472         }
 473     if(i2c->is_div_from_arm[i2c->adap.nr])
 474                 wake_lock(&i2c->idlelock[i2c->adap.nr]);
 475
 476     rk30_i2c_enable(i2c, 1);
 477         rk30_i2c_set_clk(i2c, scl_rate);
 478     udelay(i2c->tx_setup);
 479
 480     i2c_dbg(i2c->dev, "i2c transfer: addr[0x%x], scl_reate[%ldKhz]\n", msgs[0].addr, scl_rate/1000);
 481         ret = rk30_i2c_doxfer(i2c, msgs, num);
 482
 483     rk30_i2c_enable(i2c, 0);
 484     i2c->state = STATE_IDLE;
 485     if(i2c->is_div_from_arm[i2c->adap.nr])
 486                 wake_unlock(&i2c->idlelock[i2c->adap.nr]);
 487         return ret;
 488 }
 489
 490 /* declare our i2c functionality */
 491 static u32 rk30_i2c_func(struct i2c_adapter *adap)
 492 {
 493         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 494 }
 495
 496 /* i2c bus registration info */
 497
 498 static const struct i2c_algorithm rk30_i2c_algorithm = {
 499         .master_xfer            = rk30_i2c_xfer,
 500         .functionality          = rk30_i2c_func,
 501 };
 502
 503 int i2c_add_rk30_adapter(struct i2c_adapter *adap)
 504 {
 505     int ret = 0;
 506     struct rk30_i2c *i2c = (struct rk30_i2c *)adap->algo_data;
 507
 508     adap->algo = &rk30_i2c_algorithm;
 509
 510     i2c->i2c_init_hw = &rk30_i2c_init_hw;
 511     i2c->i2c_set_clk = &rk30_i2c_set_clk;
 512     i2c->i2c_irq = &rk30_i2c_irq;
 513
 514     ret = i2c_add_numbered_adapter(adap);
 515
 516     return ret;
 517 }
 518