2 * Driver for I2C adapter in Rockchip RK3xxx SoC
4 * Max Schwarz <max.schwarz@online.de>
5 * based on the patches by Rockchip Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/platform_device.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/spinlock.h>
23 #include <linux/clk.h>
24 #include <linux/wait.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/regmap.h>
27 #include <linux/math64.h>
31 #define REG_CON 0x00 /* control register */
32 #define REG_CLKDIV 0x04 /* clock divisor register */
33 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */
34 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */
35 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
36 #define REG_MRXCNT 0x14 /* number of bytes to be received */
37 #define REG_IEN 0x18 /* interrupt enable */
38 #define REG_IPD 0x1c /* interrupt pending */
39 #define REG_FCNT 0x20 /* finished count */
41 /* Data buffer offsets */
42 #define TXBUFFER_BASE 0x100
43 #define RXBUFFER_BASE 0x200
46 #define REG_CON_EN BIT(0)
48 REG_CON_MOD_TX = 0, /* transmit data */
49 REG_CON_MOD_REGISTER_TX, /* select register and restart */
50 REG_CON_MOD_RX, /* receive data */
51 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
54 #define REG_CON_MOD(mod) ((mod) << 1)
55 #define REG_CON_MOD_MASK (BIT(1) | BIT(2))
56 #define REG_CON_START BIT(3)
57 #define REG_CON_STOP BIT(4)
58 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
59 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
61 /* REG_MRXADDR bits */
62 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
64 /* REG_IEN/REG_IPD bits */
65 #define REG_INT_BTF BIT(0) /* a byte was transmitted */
66 #define REG_INT_BRF BIT(1) /* a byte was received */
67 #define REG_INT_MBTF BIT(2) /* master data transmit finished */
68 #define REG_INT_MBRF BIT(3) /* master data receive finished */
69 #define REG_INT_START BIT(4) /* START condition generated */
70 #define REG_INT_STOP BIT(5) /* STOP condition generated */
71 #define REG_INT_NAKRCV BIT(6) /* NACK received */
72 #define REG_INT_ALL 0x7f
75 #define WAIT_TIMEOUT 1000 /* ms */
76 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
87 * @grf_offset: offset inside the grf regmap for setting the i2c type
89 struct rk3x_i2c_soc_data {
94 struct i2c_adapter adap;
96 struct rk3x_i2c_soc_data *soc_data;
98 /* Hardware resources */
101 struct notifier_block clk_rate_nb;
104 unsigned int scl_frequency;
105 unsigned int scl_rise_ns;
106 unsigned int scl_fall_ns;
107 unsigned int sda_fall_ns;
109 /* Synchronization & notification */
111 wait_queue_head_t wait;
114 /* Current message */
120 /* I2C state machine */
121 enum rk3x_i2c_state state;
122 unsigned int processed; /* sent/received bytes */
126 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
129 writel(value, i2c->regs + offset);
132 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
134 return readl(i2c->regs + offset);
137 /* Reset all interrupt pending bits */
138 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
140 i2c_writel(i2c, REG_INT_ALL, REG_IPD);
144 * Generate a START condition, which triggers a REG_INT_START interrupt.
146 static void rk3x_i2c_start(struct rk3x_i2c *i2c)
150 rk3x_i2c_clean_ipd(i2c);
151 i2c_writel(i2c, REG_INT_START, REG_IEN);
153 /* enable adapter with correct mode, send START condition */
154 val = REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
156 /* if we want to react to NACK, set ACTACK bit */
157 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
158 val |= REG_CON_ACTACK;
160 i2c_writel(i2c, val, REG_CON);
164 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
166 * @error: Error code to return in rk3x_i2c_xfer
168 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
176 if (i2c->is_last_msg) {
177 /* Enable stop interrupt */
178 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
180 i2c->state = STATE_STOP;
182 ctrl = i2c_readl(i2c, REG_CON);
183 ctrl |= REG_CON_STOP;
184 i2c_writel(i2c, ctrl, REG_CON);
186 /* Signal rk3x_i2c_xfer to start the next message. */
188 i2c->state = STATE_IDLE;
191 * The HW is actually not capable of REPEATED START. But we can
192 * get the intended effect by resetting its internal state
193 * and issuing an ordinary START.
195 i2c_writel(i2c, 0, REG_CON);
197 /* signal that we are finished with the current msg */
203 * Setup a read according to i2c->msg
205 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
207 unsigned int len = i2c->msg->len - i2c->processed;
210 con = i2c_readl(i2c, REG_CON);
213 * The hw can read up to 32 bytes at a time. If we need more than one
214 * chunk, send an ACK after the last byte of the current chunk.
218 con &= ~REG_CON_LASTACK;
220 con |= REG_CON_LASTACK;
223 /* make sure we are in plain RX mode if we read a second chunk */
224 if (i2c->processed != 0) {
225 con &= ~REG_CON_MOD_MASK;
226 con |= REG_CON_MOD(REG_CON_MOD_RX);
229 i2c_writel(i2c, con, REG_CON);
230 i2c_writel(i2c, len, REG_MRXCNT);
234 * Fill the transmit buffer with data from i2c->msg
236 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c)
243 for (i = 0; i < 8; ++i) {
245 for (j = 0; j < 4; ++j) {
246 if ((i2c->processed == i2c->msg->len) && (cnt != 0))
249 if (i2c->processed == 0 && cnt == 0)
250 byte = (i2c->addr & 0x7f) << 1;
252 byte = i2c->msg->buf[i2c->processed++];
254 val |= byte << (j * 8);
258 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
260 if (i2c->processed == i2c->msg->len)
264 i2c_writel(i2c, cnt, REG_MTXCNT);
268 /* IRQ handlers for individual states */
270 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd)
272 if (!(ipd & REG_INT_START)) {
273 rk3x_i2c_stop(i2c, -EIO);
274 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
275 rk3x_i2c_clean_ipd(i2c);
280 i2c_writel(i2c, REG_INT_START, REG_IPD);
282 /* disable start bit */
283 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON);
285 /* enable appropriate interrupts and transition */
286 if (i2c->mode == REG_CON_MOD_TX) {
287 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
288 i2c->state = STATE_WRITE;
289 rk3x_i2c_fill_transmit_buf(i2c);
291 /* in any other case, we are going to be reading. */
292 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
293 i2c->state = STATE_READ;
294 rk3x_i2c_prepare_read(i2c);
298 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
300 if (!(ipd & REG_INT_MBTF)) {
301 rk3x_i2c_stop(i2c, -EIO);
302 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
303 rk3x_i2c_clean_ipd(i2c);
308 i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
310 /* are we finished? */
311 if (i2c->processed == i2c->msg->len)
312 rk3x_i2c_stop(i2c, i2c->error);
314 rk3x_i2c_fill_transmit_buf(i2c);
317 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
320 unsigned int len = i2c->msg->len - i2c->processed;
321 u32 uninitialized_var(val);
324 /* we only care for MBRF here. */
325 if (!(ipd & REG_INT_MBRF))
329 i2c_writel(i2c, REG_INT_MBRF, REG_IPD);
331 /* Can only handle a maximum of 32 bytes at a time */
335 /* read the data from receive buffer */
336 for (i = 0; i < len; ++i) {
338 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
340 byte = (val >> ((i % 4) * 8)) & 0xff;
341 i2c->msg->buf[i2c->processed++] = byte;
344 /* are we finished? */
345 if (i2c->processed == i2c->msg->len)
346 rk3x_i2c_stop(i2c, i2c->error);
348 rk3x_i2c_prepare_read(i2c);
351 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
355 if (!(ipd & REG_INT_STOP)) {
356 rk3x_i2c_stop(i2c, -EIO);
357 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
358 rk3x_i2c_clean_ipd(i2c);
363 i2c_writel(i2c, REG_INT_STOP, REG_IPD);
365 /* disable STOP bit */
366 con = i2c_readl(i2c, REG_CON);
367 con &= ~REG_CON_STOP;
368 i2c_writel(i2c, con, REG_CON);
371 i2c->state = STATE_IDLE;
373 /* signal rk3x_i2c_xfer that we are finished */
377 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
379 struct rk3x_i2c *i2c = dev_id;
382 spin_lock(&i2c->lock);
384 ipd = i2c_readl(i2c, REG_IPD);
385 if (i2c->state == STATE_IDLE) {
386 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
387 rk3x_i2c_clean_ipd(i2c);
391 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
393 /* Clean interrupt bits we don't care about */
394 ipd &= ~(REG_INT_BRF | REG_INT_BTF);
396 if (ipd & REG_INT_NAKRCV) {
398 * We got a NACK in the last operation. Depending on whether
399 * IGNORE_NAK is set, we have to stop the operation and report
402 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
404 ipd &= ~REG_INT_NAKRCV;
406 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
407 rk3x_i2c_stop(i2c, -ENXIO);
410 /* is there anything left to handle? */
411 if ((ipd & REG_INT_ALL) == 0)
414 switch (i2c->state) {
416 rk3x_i2c_handle_start(i2c, ipd);
419 rk3x_i2c_handle_write(i2c, ipd);
422 rk3x_i2c_handle_read(i2c, ipd);
425 rk3x_i2c_handle_stop(i2c, ipd);
432 spin_unlock(&i2c->lock);
437 * Calculate divider values for desired SCL frequency
439 * @clk_rate: I2C input clock rate
440 * @scl_rate: Desired SCL rate
441 * @scl_rise_ns: How many ns it takes for SCL to rise.
442 * @scl_fall_ns: How many ns it takes for SCL to fall.
443 * @sda_fall_ns: How many ns it takes for SDA to fall.
444 * @div_low: Divider output for low
445 * @div_high: Divider output for high
447 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
448 * a best-effort divider value is returned in divs. If the target rate is
449 * too high, we silently use the highest possible rate.
451 static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate,
452 unsigned long scl_rise_ns,
453 unsigned long scl_fall_ns,
454 unsigned long sda_fall_ns,
455 unsigned long *div_low, unsigned long *div_high)
457 unsigned long spec_min_low_ns, spec_min_high_ns;
458 unsigned long spec_setup_start, spec_max_data_hold_ns;
459 unsigned long data_hold_buffer_ns;
461 unsigned long min_low_ns, min_high_ns;
462 unsigned long max_low_ns, min_total_ns;
464 unsigned long clk_rate_khz, scl_rate_khz;
466 unsigned long min_low_div, min_high_div;
467 unsigned long max_low_div;
469 unsigned long min_div_for_hold, min_total_div;
470 unsigned long extra_div, extra_low_div, ideal_low_div;
474 /* Only support standard-mode and fast-mode */
475 if (WARN_ON(scl_rate > 400000))
478 /* prevent scl_rate_khz from becoming 0 */
479 if (WARN_ON(scl_rate < 1000))
483 * min_low_ns: The minimum number of ns we need to hold low to
484 * meet I2C specification, should include fall time.
485 * min_high_ns: The minimum number of ns we need to hold high to
486 * meet I2C specification, should include rise time.
487 * max_low_ns: The maximum number of ns we can hold low to meet
490 * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
491 * This is because the i2c host on Rockchip holds the data line
492 * for half the low time.
494 if (scl_rate <= 100000) {
496 spec_min_low_ns = 4700;
497 spec_setup_start = 4700;
498 spec_min_high_ns = 4000;
499 spec_max_data_hold_ns = 3450;
500 data_hold_buffer_ns = 50;
503 spec_min_low_ns = 1300;
504 spec_setup_start = 600;
505 spec_min_high_ns = 600;
506 spec_max_data_hold_ns = 900;
507 data_hold_buffer_ns = 50;
509 min_high_ns = scl_rise_ns + spec_min_high_ns;
512 * Timings for repeated start:
513 * - controller appears to drop SDA at .875x (7/8) programmed clk high.
514 * - controller appears to keep SCL high for 2x programmed clk high.
516 * We need to account for those rules in picking our "high" time so
517 * we meet tSU;STA and tHD;STA times.
519 min_high_ns = max(min_high_ns,
520 DIV_ROUND_UP((scl_rise_ns + spec_setup_start) * 1000, 875));
521 min_high_ns = max(min_high_ns,
522 DIV_ROUND_UP((scl_rise_ns + spec_setup_start +
523 sda_fall_ns + spec_min_high_ns), 2));
525 min_low_ns = scl_fall_ns + spec_min_low_ns;
526 max_low_ns = spec_max_data_hold_ns * 2 - data_hold_buffer_ns;
527 min_total_ns = min_low_ns + min_high_ns;
529 /* Adjust to avoid overflow */
530 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
531 scl_rate_khz = scl_rate / 1000;
534 * We need the total div to be >= this number
535 * so we don't clock too fast.
537 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
539 /* These are the min dividers needed for min hold times. */
540 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
541 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
542 min_div_for_hold = (min_low_div + min_high_div);
545 * This is the maximum divider so we don't go over the maximum.
546 * We don't round up here (we round down) since this is a maximum.
548 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
550 if (min_low_div > max_low_div) {
552 "Conflicting, min_low_div %lu, max_low_div %lu\n",
553 min_low_div, max_low_div);
554 max_low_div = min_low_div;
557 if (min_div_for_hold > min_total_div) {
559 * Time needed to meet hold requirements is important.
562 *div_low = min_low_div;
563 *div_high = min_high_div;
566 * We've got to distribute some time among the low and high
567 * so we don't run too fast.
569 extra_div = min_total_div - min_div_for_hold;
572 * We'll try to split things up perfectly evenly,
573 * biasing slightly towards having a higher div
574 * for low (spend more time low).
576 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
577 scl_rate_khz * 8 * min_total_ns);
579 /* Don't allow it to go over the maximum */
580 if (ideal_low_div > max_low_div)
581 ideal_low_div = max_low_div;
584 * Handle when the ideal low div is going to take up
587 if (ideal_low_div > min_low_div + extra_div)
588 ideal_low_div = min_low_div + extra_div;
590 /* Give low the "ideal" and give high whatever extra is left */
591 extra_low_div = ideal_low_div - min_low_div;
592 *div_low = ideal_low_div;
593 *div_high = min_high_div + (extra_div - extra_low_div);
597 * Adjust to the fact that the hardware has an implicit "+1".
598 * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
600 *div_low = *div_low - 1;
601 *div_high = *div_high - 1;
603 /* Maximum divider supported by hw is 0xffff */
604 if (*div_low > 0xffff) {
609 if (*div_high > 0xffff) {
617 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
619 unsigned long div_low, div_high;
620 u64 t_low_ns, t_high_ns;
623 ret = rk3x_i2c_calc_divs(clk_rate, i2c->scl_frequency, i2c->scl_rise_ns,
624 i2c->scl_fall_ns, i2c->sda_fall_ns,
625 &div_low, &div_high);
626 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", i2c->scl_frequency);
628 clk_enable(i2c->clk);
629 i2c_writel(i2c, (div_high << 16) | (div_low & 0xffff), REG_CLKDIV);
630 clk_disable(i2c->clk);
632 t_low_ns = div_u64(((u64)div_low + 1) * 8 * 1000000000, clk_rate);
633 t_high_ns = div_u64(((u64)div_high + 1) * 8 * 1000000000, clk_rate);
635 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
637 1000000000 / i2c->scl_frequency,
638 t_low_ns, t_high_ns);
642 * rk3x_i2c_clk_notifier_cb - Clock rate change callback
643 * @nb: Pointer to notifier block
644 * @event: Notification reason
645 * @data: Pointer to notification data object
647 * The callback checks whether a valid bus frequency can be generated after the
648 * change. If so, the change is acknowledged, otherwise the change is aborted.
649 * New dividers are written to the HW in the pre- or post change notification
650 * depending on the scaling direction.
652 * Code adapted from i2c-cadence.c.
654 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
655 * to acknowedge the change, NOTIFY_DONE if the notification is
656 * considered irrelevant.
658 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
661 struct clk_notifier_data *ndata = data;
662 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
663 unsigned long div_low, div_high;
666 case PRE_RATE_CHANGE:
667 if (rk3x_i2c_calc_divs(ndata->new_rate, i2c->scl_frequency,
668 i2c->scl_rise_ns, i2c->scl_fall_ns,
670 &div_low, &div_high) != 0)
674 if (ndata->new_rate > ndata->old_rate)
675 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
678 case POST_RATE_CHANGE:
680 if (ndata->new_rate < ndata->old_rate)
681 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
683 case ABORT_RATE_CHANGE:
685 if (ndata->new_rate > ndata->old_rate)
686 rk3x_i2c_adapt_div(i2c, ndata->old_rate);
694 * Setup I2C registers for an I2C operation specified by msgs, num.
696 * Must be called with i2c->lock held.
698 * @msgs: I2C msgs to process
699 * @num: Number of msgs
701 * returns: Number of I2C msgs processed or negative in case of error
703 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
705 u32 addr = (msgs[0].addr & 0x7f) << 1;
709 * The I2C adapter can issue a small (len < 4) write packet before
710 * reading. This speeds up SMBus-style register reads.
711 * The MRXADDR/MRXRADDR hold the slave address and the slave register
712 * address in this case.
715 if (num >= 2 && msgs[0].len < 4 &&
716 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
720 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
723 /* Fill MRXRADDR with the register address(es) */
724 for (i = 0; i < msgs[0].len; ++i) {
725 reg_addr |= msgs[0].buf[i] << (i * 8);
726 reg_addr |= REG_MRXADDR_VALID(i);
729 /* msgs[0] is handled by hw. */
732 i2c->mode = REG_CON_MOD_REGISTER_TX;
734 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
735 i2c_writel(i2c, reg_addr, REG_MRXRADDR);
740 * We'll have to do it the boring way and process the msgs
744 if (msgs[0].flags & I2C_M_RD) {
745 addr |= 1; /* set read bit */
748 * We have to transmit the slave addr first. Use
749 * MOD_REGISTER_TX for that purpose.
751 i2c->mode = REG_CON_MOD_REGISTER_TX;
752 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
754 i2c_writel(i2c, 0, REG_MRXRADDR);
756 i2c->mode = REG_CON_MOD_TX;
764 i2c->addr = msgs[0].addr;
766 i2c->state = STATE_START;
770 rk3x_i2c_clean_ipd(i2c);
775 static int rk3x_i2c_xfer(struct i2c_adapter *adap,
776 struct i2c_msg *msgs, int num)
778 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
779 unsigned long timeout, flags;
783 spin_lock_irqsave(&i2c->lock, flags);
785 clk_enable(i2c->clk);
787 i2c->is_last_msg = false;
790 * Process msgs. We can handle more than one message at once (see
793 for (i = 0; i < num; i += ret) {
794 ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
797 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
802 i2c->is_last_msg = true;
804 spin_unlock_irqrestore(&i2c->lock, flags);
808 timeout = wait_event_timeout(i2c->wait, !i2c->busy,
809 msecs_to_jiffies(WAIT_TIMEOUT));
811 spin_lock_irqsave(&i2c->lock, flags);
814 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
815 i2c_readl(i2c, REG_IPD), i2c->state);
817 /* Force a STOP condition without interrupt */
818 i2c_writel(i2c, 0, REG_IEN);
819 i2c_writel(i2c, REG_CON_EN | REG_CON_STOP, REG_CON);
821 i2c->state = STATE_IDLE;
833 clk_disable(i2c->clk);
834 spin_unlock_irqrestore(&i2c->lock, flags);
836 return ret < 0 ? ret : num;
839 static u32 rk3x_i2c_func(struct i2c_adapter *adap)
841 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
844 static const struct i2c_algorithm rk3x_i2c_algorithm = {
845 .master_xfer = rk3x_i2c_xfer,
846 .functionality = rk3x_i2c_func,
849 static struct rk3x_i2c_soc_data soc_data[3] = {
850 { .grf_offset = 0x154 }, /* rk3066 */
851 { .grf_offset = 0x0a4 }, /* rk3188 */
852 { .grf_offset = -1 }, /* no I2C switching needed */
855 static const struct of_device_id rk3x_i2c_match[] = {
856 { .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] },
857 { .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] },
858 { .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] },
861 MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
863 static int rk3x_i2c_probe(struct platform_device *pdev)
865 struct device_node *np = pdev->dev.of_node;
866 const struct of_device_id *match;
867 struct rk3x_i2c *i2c;
868 struct resource *mem;
873 unsigned long clk_rate;
875 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
879 match = of_match_node(rk3x_i2c_match, np);
880 i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data;
882 if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
883 &i2c->scl_frequency)) {
884 dev_info(&pdev->dev, "using default SCL frequency: %d\n",
886 i2c->scl_frequency = DEFAULT_SCL_RATE;
889 if (i2c->scl_frequency == 0 || i2c->scl_frequency > 400 * 1000) {
890 dev_warn(&pdev->dev, "invalid SCL frequency specified.\n");
891 dev_warn(&pdev->dev, "using default SCL frequency: %d\n",
893 i2c->scl_frequency = DEFAULT_SCL_RATE;
897 * Read rise and fall time from device tree. If not available use
898 * the default maximum timing from the specification.
900 if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-rising-time-ns",
901 &i2c->scl_rise_ns)) {
902 if (i2c->scl_frequency <= 100000)
903 i2c->scl_rise_ns = 1000;
905 i2c->scl_rise_ns = 300;
907 if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-falling-time-ns",
909 i2c->scl_fall_ns = 300;
910 if (of_property_read_u32(pdev->dev.of_node, "i2c-sda-falling-time-ns",
912 i2c->sda_fall_ns = i2c->scl_fall_ns;
914 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
915 i2c->adap.owner = THIS_MODULE;
916 i2c->adap.algo = &rk3x_i2c_algorithm;
917 i2c->adap.retries = 3;
918 i2c->adap.dev.of_node = np;
919 i2c->adap.algo_data = i2c;
920 i2c->adap.dev.parent = &pdev->dev;
922 i2c->dev = &pdev->dev;
924 spin_lock_init(&i2c->lock);
925 init_waitqueue_head(&i2c->wait);
927 i2c->clk = devm_clk_get(&pdev->dev, NULL);
928 if (IS_ERR(i2c->clk)) {
929 dev_err(&pdev->dev, "cannot get clock\n");
930 return PTR_ERR(i2c->clk);
933 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
934 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
935 if (IS_ERR(i2c->regs))
936 return PTR_ERR(i2c->regs);
938 /* Try to set the I2C adapter number from dt */
939 bus_nr = of_alias_get_id(np, "i2c");
942 * Switch to new interface if the SoC also offers the old one.
943 * The control bit is located in the GRF register space.
945 if (i2c->soc_data->grf_offset >= 0) {
948 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
951 "rk3x-i2c needs 'rockchip,grf' property\n");
956 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
960 /* 27+i: write mask, 11+i: value */
961 value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
963 ret = regmap_write(grf, i2c->soc_data->grf_offset, value);
965 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
971 irq = platform_get_irq(pdev, 0);
973 dev_err(&pdev->dev, "cannot find rk3x IRQ\n");
977 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
978 0, dev_name(&pdev->dev), i2c);
980 dev_err(&pdev->dev, "cannot request IRQ\n");
984 platform_set_drvdata(pdev, i2c);
986 ret = clk_prepare(i2c->clk);
988 dev_err(&pdev->dev, "Could not prepare clock\n");
992 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
993 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
995 dev_err(&pdev->dev, "Unable to register clock notifier\n");
999 clk_rate = clk_get_rate(i2c->clk);
1000 rk3x_i2c_adapt_div(i2c, clk_rate);
1002 ret = i2c_add_adapter(&i2c->adap);
1004 dev_err(&pdev->dev, "Could not register adapter\n");
1005 goto err_clk_notifier;
1008 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs);
1013 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1015 clk_unprepare(i2c->clk);
1019 static int rk3x_i2c_remove(struct platform_device *pdev)
1021 struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
1023 i2c_del_adapter(&i2c->adap);
1025 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1026 clk_unprepare(i2c->clk);
1031 static struct platform_driver rk3x_i2c_driver = {
1032 .probe = rk3x_i2c_probe,
1033 .remove = rk3x_i2c_remove,
1036 .of_match_table = rk3x_i2c_match,
1040 module_platform_driver(rk3x_i2c_driver);
1042 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1043 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1044 MODULE_LICENSE("GPL v2");