drivers/i2c/busses/i2c-rockchip.c

   1 /*
   2  * Copyright (C) 2012-2014 ROCKCHIP, Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/uaccess.h>
  16 #include <linux/fs.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/wakelock.h>
  20 #include <linux/i2c.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/of_i2c.h>
  23 #include <linux/init.h>
  24 #include <linux/time.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/err.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/slab.h>
  32 #include <linux/io.h>
  33 #include <linux/mutex.h>
  34 #include <linux/miscdevice.h>
  35 #include <linux/gpio.h>
  36 #include <asm/irq.h>
  37
  38 #if 0
  39 #define i2c_dbg(dev, format, arg...)            \
  40         dev_printk(KERN_INFO , dev , format , ## arg)
  41 #else
  42 #define i2c_dbg(dev, format, arg...)
  43 #endif
  44
  45 enum {
  46         I2C_IDLE = 0,
  47         I2C_SDA_LOW,
  48         I2C_SCL_LOW,
  49         BOTH_LOW,
  50 };
  51
  52 #define i2c_writel                      writel_relaxed
  53 #define i2c_readl                       readl_relaxed
  54
  55 #define I2C_WAIT_TIMEOUT                200  //200ms
  56
  57 #define rockchip_set_bit(p, v, b)       (((p) & ~(1 << (b))) | ((v) << (b)))
  58 #define rockchip_get_bit(p, b)          (((p) & (1 << (b))) >> (b))
  59
  60 #define rockchip_set_bits(p, v, b, m)   (((p) & ~(m)) | ((v) << (b)))
  61 #define rockchip_get_bits(p, b, m)      (((p) & (m)) >> (b))
  62
  63 #define rockchip_ceil(x, y) \
  64         ({ unsigned long __x = (x), __y = (y); (__x + __y - 1) / __y; })
  65
  66 enum rockchip_i2c_state {
  67         STATE_IDLE,
  68         STATE_START,
  69         STATE_READ,
  70         STATE_WRITE,
  71         STATE_STOP
  72 };
  73
  74 struct rockchip_i2c {
  75         spinlock_t              lock;
  76         wait_queue_head_t       wait;
  77         unsigned int            suspended:1;
  78
  79         struct i2c_msg          *msg;
  80         unsigned int            is_busy;
  81         int                     error;
  82         unsigned int            msg_ptr;
  83
  84         unsigned int            irq;
  85
  86         enum rockchip_i2c_state state;
  87         unsigned int            complete_what;
  88         unsigned long           clkrate;
  89
  90         void __iomem            *regs;
  91         struct clk              *clk;
  92         struct device           *dev;
  93         struct resource         *ioarea;
  94         struct i2c_adapter      adap;
  95         struct mutex            suspend_lock;
  96
  97         unsigned long           scl_rate;
  98         unsigned long           i2c_rate;
  99         unsigned int            addr;
 100         unsigned char           addr_1st, addr_2nd;
 101         unsigned int            mode;
 102         unsigned int            count;
 103
 104         unsigned int            check_idle;
 105         int                     sda_gpio, scl_gpio;
 106         struct pinctrl_state    *gpio_state;
 107 };
 108
 109 #define COMPLETE_READ      (1<<STATE_START | 1<<STATE_READ  | 1<<STATE_STOP)
 110 #define COMPLETE_WRITE     (1<<STATE_START | 1<<STATE_WRITE | 1<<STATE_STOP)
 111
 112 /* Control register */
 113 #define I2C_CON                 0x000
 114 #define I2C_CON_EN              (1 << 0)
 115 #define I2C_CON_MOD(mod)        ((mod) << 1)
 116 #define I2C_CON_MASK            (3 << 1)
 117
 118 enum {
 119         I2C_CON_MOD_TX = 0,
 120         I2C_CON_MOD_TRX,
 121         I2C_CON_MOD_RX,
 122         I2C_CON_MOD_RRX,
 123 };
 124
 125 #define I2C_CON_START           (1 << 3)
 126 #define I2C_CON_STOP            (1 << 4)
 127 #define I2C_CON_LASTACK         (1 << 5)
 128 #define I2C_CON_ACTACK          (1 << 6)
 129
 130 /* Clock dividor register */
 131 #define I2C_CLKDIV              0x004
 132 #define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
 133
 134 /* the slave address accessed  for master rx mode */
 135 #define I2C_MRXADDR             0x008
 136 #define I2C_MRXADDR_LOW         (1 << 24)
 137 #define I2C_MRXADDR_MID         (1 << 25)
 138 #define I2C_MRXADDR_HIGH        (1 << 26)
 139
 140 /* the slave register address accessed  for master rx mode */
 141 #define I2C_MRXRADDR            0x00c
 142 #define I2C_MRXRADDR_LOW        (1 << 24)
 143 #define I2C_MRXRADDR_MID        (1 << 25)
 144 #define I2C_MRXRADDR_HIGH       (1 << 26)
 145
 146 /* master tx count */
 147 #define I2C_MTXCNT              0x010
 148
 149 /* master rx count */
 150 #define I2C_MRXCNT              0x014
 151
 152 /* interrupt enable register */
 153 #define I2C_IEN                 0x018
 154 #define I2C_BTFIEN              (1 << 0)
 155 #define I2C_BRFIEN              (1 << 1)
 156 #define I2C_MBTFIEN             (1 << 2)
 157 #define I2C_MBRFIEN             (1 << 3)
 158 #define I2C_STARTIEN            (1 << 4)
 159 #define I2C_STOPIEN             (1 << 5)
 160 #define I2C_NAKRCVIEN           (1 << 6)
 161 #define IRQ_MST_ENABLE          (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
 162 #define IRQ_ALL_DISABLE         0
 163
 164 /* interrupt pending register */
 165 #define I2C_IPD                 0x01c
 166 #define I2C_BTFIPD              (1 << 0)
 167 #define I2C_BRFIPD              (1 << 1)
 168 #define I2C_MBTFIPD             (1 << 2)
 169 #define I2C_MBRFIPD             (1 << 3)
 170 #define I2C_STARTIPD            (1 << 4)
 171 #define I2C_STOPIPD             (1 << 5)
 172 #define I2C_NAKRCVIPD           (1 << 6)
 173
 174 #define I2C_HOLD_SCL            (1 << 7)
 175 #define I2C_IPD_ALL_CLEAN       0x7f
 176
 177 /* finished count */
 178 #define I2C_FCNT                0x020
 179
 180 /* I2C tx data register */
 181 #define I2C_TXDATA_BASE         0X100
 182
 183 /* I2C rx data register */
 184 #define I2C_RXDATA_BASE         0x200
 185
 186 static void rockchip_show_regs(struct rockchip_i2c *i2c)
 187 {
 188         int i;
 189
 190         dev_info(i2c->dev, "i2c->clk = %lu\n", clk_get_rate(i2c->clk));
 191         dev_info(i2c->dev, "i2c->state = %d\n", i2c->state);
 192         dev_info(i2c->dev, "I2C_CON: 0x%08x\n", i2c_readl(i2c->regs + I2C_CON));
 193         dev_info(i2c->dev, "I2C_CLKDIV: 0x%08x\n", i2c_readl(i2c->regs + I2C_CLKDIV));
 194         dev_info(i2c->dev, "I2C_MRXADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXADDR));
 195         dev_info(i2c->dev, "I2C_MRXRADDR: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXRADDR));
 196         dev_info(i2c->dev, "I2C_MTXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MTXCNT));
 197         dev_info(i2c->dev, "I2C_MRXCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_MRXCNT));
 198         dev_info(i2c->dev, "I2C_IEN: 0x%08x\n", i2c_readl(i2c->regs + I2C_IEN));
 199         dev_info(i2c->dev, "I2C_IPD: 0x%08x\n", i2c_readl(i2c->regs + I2C_IPD));
 200         dev_info(i2c->dev, "I2C_FCNT: 0x%08x\n", i2c_readl(i2c->regs + I2C_FCNT));
 201         for (i = 0; i < 8; i++)
 202                 dev_info(i2c->dev, "I2C_TXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_TXDATA_BASE + i * 4));
 203         for (i = 0; i < 8; i++)
 204                 dev_info(i2c->dev, "I2C_RXDATA%d: 0x%08x\n", i, i2c_readl(i2c->regs + I2C_RXDATA_BASE + i * 4));
 205 }
 206
 207 static int rockchip_i2c_check_idle(struct rockchip_i2c *i2c)
 208 {
 209         int ret = I2C_IDLE;
 210         int sda_lev, scl_lev;
 211
 212         if (!gpio_is_valid(i2c->sda_gpio))
 213                 return ret;
 214
 215         if (pinctrl_select_state(i2c->dev->pins->p, i2c->gpio_state))
 216                 return ret;
 217
 218         sda_lev = gpio_get_value(i2c->sda_gpio);
 219         scl_lev = gpio_get_value(i2c->scl_gpio);
 220
 221         pinctrl_select_state(i2c->dev->pins->p, i2c->dev->pins->default_state);
 222
 223         if (sda_lev == 1 && scl_lev == 1)
 224                 return I2C_IDLE;
 225         else if (sda_lev == 0 && scl_lev == 1)
 226                 return I2C_SDA_LOW;
 227         else if (sda_lev == 1 && scl_lev == 0)
 228                 return I2C_SCL_LOW;
 229         else
 230                 return BOTH_LOW;
 231 }
 232
 233 static inline void rockchip_i2c_enable(struct rockchip_i2c *i2c, unsigned int lastnak)
 234 {
 235         unsigned int con = 0;
 236
 237         con |= I2C_CON_EN;
 238         con |= I2C_CON_MOD(i2c->mode);
 239         if (lastnak)
 240                 con |= I2C_CON_LASTACK;
 241         con |= I2C_CON_START;
 242         i2c_writel(con, i2c->regs + I2C_CON);
 243 }
 244
 245 static inline void rockchip_i2c_disable(struct rockchip_i2c *i2c)
 246 {
 247         i2c_writel(0, i2c->regs + I2C_CON);
 248 }
 249
 250 static inline void rockchip_i2c_clean_start(struct rockchip_i2c *i2c)
 251 {
 252         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 253
 254         con &= ~I2C_CON_START;
 255         i2c_writel(con, i2c->regs + I2C_CON);
 256 }
 257
 258 static inline void rockchip_i2c_send_start(struct rockchip_i2c *i2c)
 259 {
 260         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 261
 262         con |= I2C_CON_START;
 263         if (con & I2C_CON_STOP)
 264                 dev_warn(i2c->dev, "I2C_CON: stop bit is set\n");
 265
 266         i2c_writel(con, i2c->regs + I2C_CON);
 267 }
 268
 269 static inline void rockchip_i2c_send_stop(struct rockchip_i2c *i2c)
 270 {
 271         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 272
 273         con |= I2C_CON_STOP;
 274         if (con & I2C_CON_START)
 275                 dev_warn(i2c->dev, "I2C_CON: start bit is set\n");
 276
 277         i2c_writel(con, i2c->regs + I2C_CON);
 278 }
 279
 280 static inline void rockchip_i2c_clean_stop(struct rockchip_i2c *i2c)
 281 {
 282         unsigned int con = i2c_readl(i2c->regs + I2C_CON);
 283
 284         con &= ~I2C_CON_STOP;
 285         i2c_writel(con, i2c->regs + I2C_CON);
 286 }
 287
 288 static inline void rockchip_i2c_disable_irq(struct rockchip_i2c *i2c)
 289 {
 290         i2c_writel(IRQ_ALL_DISABLE, i2c->regs + I2C_IEN);
 291 }
 292
 293 static inline void rockchip_i2c_enable_irq(struct rockchip_i2c *i2c)
 294 {
 295         i2c_writel(IRQ_MST_ENABLE, i2c->regs + I2C_IEN);
 296 }
 297
 298 static void rockchip_get_div(int div, int *divh, int *divl)
 299 {
 300         if (div % 2 == 0) {
 301                 *divh = div / 2;
 302                 *divl = div / 2;
 303         } else {
 304                 *divh = rockchip_ceil(div, 2);
 305                 *divl = div / 2;
 306         }
 307 }
 308
 309 /* SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
 310  * SCL = i2c_rate/ SCLK Divisor
 311 */
 312 static void rockchip_i2c_set_clk(struct rockchip_i2c *i2c, unsigned long scl_rate)
 313 {
 314         unsigned long i2c_rate = i2c->i2c_rate;
 315         int div, divl, divh;
 316
 317         if (scl_rate == i2c->scl_rate)
 318                 return;
 319         i2c->scl_rate = scl_rate;
 320         div = rockchip_ceil(i2c_rate, (scl_rate * 8)) - 2;
 321         if (unlikely(div < 0)) {
 322                 dev_warn(i2c->dev, "Divisor(%d) is negative, set divl = divh = 0\n", div);
 323                 divh = divl = 0;
 324         } else {
 325                 rockchip_get_div(div, &divh, &divl);
 326         }
 327         i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
 328         i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV));
 329 }
 330
 331 static void rockchip_i2c_init_hw(struct rockchip_i2c *i2c, unsigned long scl_rate)
 332 {
 333         i2c->scl_rate = 0;
 334         clk_enable(i2c->clk);
 335         rockchip_i2c_set_clk(i2c, scl_rate);
 336         clk_disable(i2c->clk);
 337 }
 338
 339 /* returns TRUE if we this is the last byte in the current message */
 340 static inline int is_msglast(struct rockchip_i2c *i2c)
 341 {
 342         return i2c->msg_ptr == i2c->msg->len - 1;
 343 }
 344
 345 /* returns TRUE if we reached the end of the current message */
 346 static inline int is_msgend(struct rockchip_i2c *i2c)
 347 {
 348         return i2c->msg_ptr >= i2c->msg->len;
 349 }
 350
 351 static void rockchip_i2c_stop(struct rockchip_i2c *i2c, int ret)
 352 {
 353
 354         i2c->msg_ptr = 0;
 355         i2c->msg = NULL;
 356         if (ret == -EAGAIN) {
 357                 i2c->state = STATE_IDLE;
 358                 i2c->is_busy = 0;
 359                 wake_up(&i2c->wait);
 360                 return;
 361         }
 362         i2c->error = ret;
 363         i2c_writel(I2C_STOPIEN, i2c->regs + I2C_IEN);
 364         i2c->state = STATE_STOP;
 365         rockchip_i2c_send_stop(i2c);
 366 }
 367
 368 static inline void rockchip_set_rx_mode(struct rockchip_i2c *i2c, unsigned int lastnak)
 369 {
 370         unsigned long con = i2c_readl(i2c->regs + I2C_CON);
 371
 372         con &= (~I2C_CON_MASK);
 373         con |= (I2C_CON_MOD_RX << 1);
 374         if (lastnak)
 375                 con |= I2C_CON_LASTACK;
 376         i2c_writel(con, i2c->regs + I2C_CON);
 377 }
 378
 379 static void rockchip_irq_read_prepare(struct rockchip_i2c *i2c)
 380 {
 381         unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;
 382
 383         if (len <= 32 && i2c->msg_ptr != 0)
 384                 rockchip_set_rx_mode(i2c, 1);
 385         else if (i2c->msg_ptr != 0)
 386                 rockchip_set_rx_mode(i2c, 0);
 387
 388         if (is_msgend(i2c)) {
 389                 rockchip_i2c_stop(i2c, i2c->error);
 390                 return;
 391         }
 392         if (len > 32)
 393                 cnt = 32;
 394         else
 395                 cnt = len;
 396         i2c_writel(cnt, i2c->regs + I2C_MRXCNT);
 397 }
 398
 399 static void rockchip_irq_read_get_data(struct rockchip_i2c *i2c)
 400 {
 401         unsigned int i, len = i2c->msg->len - i2c->msg_ptr;
 402         unsigned int p = 0;
 403
 404         len = (len >= 32) ? 32 : len;
 405
 406         for (i = 0; i < len; i++) {
 407                 if (i % 4 == 0)
 408                         p = i2c_readl(i2c->regs + I2C_RXDATA_BASE + (i / 4) * 4);
 409                 i2c->msg->buf[i2c->msg_ptr++] = (p >> ((i % 4) * 8)) & 0xff;
 410         }
 411 }
 412
 413 static void rockchip_irq_write_prepare(struct rockchip_i2c *i2c)
 414 {
 415         unsigned int data = 0, cnt = 0, i, j;
 416         unsigned char byte;
 417
 418         if (is_msgend(i2c)) {
 419                 rockchip_i2c_stop(i2c, i2c->error);
 420                 return;
 421         }
 422         for (i = 0; i < 8; i++) {
 423                 data = 0;
 424                 for (j = 0; j < 4; j++) {
 425                         if (is_msgend(i2c))
 426                                 break;
 427                         if ((i2c->msg_ptr == 0) && (cnt == 0))
 428                                 byte = (i2c->addr_1st & 0x7f) << 1;
 429                         else if ((i2c->msg_ptr == 0) && (cnt == 1) && (i2c->msg->flags & I2C_M_TEN))
 430                                 byte = i2c->addr_2nd;
 431                         else
 432                                 byte = i2c->msg->buf[i2c->msg_ptr++];
 433                         cnt++;
 434                         data |= (byte << (j * 8));
 435                 }
 436                 i2c_writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
 437                 if (is_msgend(i2c))
 438                         break;
 439         }
 440         i2c_writel(cnt, i2c->regs + I2C_MTXCNT);
 441 }
 442
 443 static void rockchip_i2c_irq_nextblock(struct rockchip_i2c *i2c, unsigned int ipd)
 444 {
 445         switch (i2c->state) {
 446         case STATE_START:
 447                 if (!(ipd & I2C_STARTIPD)) {
 448                         rockchip_i2c_stop(i2c, -ENXIO);
 449                         dev_err(i2c->dev, "Addr[0x%04x] no start irq in STATE_START\n", i2c->addr);
 450                         rockchip_show_regs(i2c);
 451                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 452                         goto out;
 453                 }
 454                 i2c->complete_what |= 1 << i2c->state;
 455                 i2c_writel(I2C_STARTIPD, i2c->regs + I2C_IPD);
 456                 rockchip_i2c_clean_start(i2c);
 457                 if (i2c->mode == I2C_CON_MOD_TX) {
 458                         i2c_writel(I2C_MBTFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
 459                         i2c->state = STATE_WRITE;
 460                         goto prepare_write;
 461                 } else {
 462                         i2c_writel(I2C_MBRFIEN | I2C_NAKRCVIEN, i2c->regs + I2C_IEN);
 463                         i2c->state = STATE_READ;
 464                         goto prepare_read;
 465                 }
 466         case STATE_WRITE:
 467                 if (!(ipd & I2C_MBTFIPD)) {
 468                         rockchip_i2c_stop(i2c, -ENXIO);
 469                         dev_err(i2c->dev, "Addr[0x%04x] no mbtf irq in STATE_WRITE\n", i2c->addr);
 470                         rockchip_show_regs(i2c);
 471                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 472                         goto out;
 473                 }
 474                 i2c->complete_what |= 1 << i2c->state;
 475                 i2c_writel(I2C_MBTFIPD, i2c->regs + I2C_IPD);
 476 prepare_write:
 477                 rockchip_irq_write_prepare(i2c);
 478                 break;
 479         case STATE_READ:
 480                 if (!(ipd & I2C_MBRFIPD)) {
 481                         rockchip_i2c_stop(i2c, -ENXIO);
 482                         dev_err(i2c->dev, "Addr[0x%04x] no mbrf irq in STATE_READ, ipd = 0x%x\n", i2c->addr, ipd);
 483                         rockchip_show_regs(i2c);
 484                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 485                         goto out;
 486                 }
 487                 i2c->complete_what |= 1 << i2c->state;
 488                 i2c_writel(I2C_MBRFIPD, i2c->regs + I2C_IPD);
 489                 rockchip_irq_read_get_data(i2c);
 490 prepare_read:
 491                 rockchip_irq_read_prepare(i2c);
 492                 break;
 493         case STATE_STOP:
 494                 if (!(ipd & I2C_STOPIPD)) {
 495                         rockchip_i2c_stop(i2c, -ENXIO);
 496                         dev_err(i2c->dev, "Addr[0x%04x] no stop irq in STATE_STOP\n", i2c->addr);
 497                         rockchip_show_regs(i2c);
 498                         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 499                         goto out;
 500                 }
 501                 rockchip_i2c_clean_stop(i2c);
 502                 i2c_writel(I2C_STOPIPD, i2c->regs + I2C_IPD);
 503                 i2c->is_busy = 0;
 504                 i2c->complete_what |= 1 << i2c->state;
 505                 i2c->state = STATE_IDLE;
 506                 wake_up(&i2c->wait);
 507                 break;
 508         default:
 509                 break;
 510         }
 511 out:
 512         return;
 513 }
 514
 515 static irqreturn_t rockchip_i2c_irq(int irq, void *dev_id)
 516 {
 517         struct rockchip_i2c *i2c = dev_id;
 518         unsigned int ipd;
 519
 520         spin_lock(&i2c->lock);
 521         ipd = i2c_readl(i2c->regs + I2C_IPD);
 522         if (i2c->state == STATE_IDLE) {
 523                 dev_info(i2c->dev, "Addr[0x%04x]  irq in STATE_IDLE, ipd = 0x%x\n", i2c->addr, ipd);
 524                 i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 525                 goto out;
 526         }
 527
 528         if (ipd & I2C_NAKRCVIPD) {
 529                 i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
 530                 i2c->error = -EAGAIN;
 531                 goto out;
 532         }
 533         rockchip_i2c_irq_nextblock(i2c, ipd);
 534 out:
 535         spin_unlock(&i2c->lock);
 536         return IRQ_HANDLED;
 537 }
 538
 539 static int rockchip_i2c_set_master(struct rockchip_i2c *i2c, struct i2c_msg *msgs, int num)
 540 {
 541         unsigned int reg_valid_bits = 0;
 542         unsigned int reg_addr = 0;
 543         unsigned int addr = (i2c->addr_1st << 1) | 1;
 544
 545         if (num == 1) {
 546                 i2c->count = msgs[0].len;
 547                 if (!(msgs[0].flags & I2C_M_RD)) {
 548                         i2c->msg = &msgs[0];
 549                         i2c->mode = I2C_CON_MOD_TX;
 550                 } else {
 551                         i2c->msg = &msgs[0];
 552                         i2c_writel(addr | I2C_MRXADDR_LOW,
 553                                    i2c->regs + I2C_MRXADDR);
 554                         i2c_writel(0, i2c->regs + I2C_MRXRADDR);
 555                         i2c->mode = I2C_CON_MOD_TRX;
 556                         //i2c->mode = I2C_CON_MOD_RX;
 557                 }
 558         } else if (num == 2) {
 559                 i2c->count = msgs[1].len;
 560
 561                 if (msgs[0].flags & I2C_M_TEN) {
 562                         switch (msgs[0].len) {
 563                         case 1:
 564                                 reg_addr = i2c->addr_2nd | (msgs[0].buf[0] << 8);
 565                                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
 566                                 break;
 567                         case 2:
 568                                 reg_addr = i2c->addr_2nd | (msgs[0].buf[0] << 8) | (msgs[0].buf[1] << 16);
 569                                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
 570                                 break;
 571                         default:
 572                                 return -EIO;
 573                         }
 574                 } else {
 575                         switch (msgs[0].len) {
 576                         case 1:
 577                                 reg_addr = msgs[0].buf[0];
 578                                 reg_valid_bits |= I2C_MRXADDR_LOW;
 579                                 break;
 580                         case 2:
 581                                 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8);
 582                                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID;
 583                                 break;
 584                         case 3:
 585                                 reg_addr = msgs[0].buf[0] | (msgs[0].buf[1] << 8) | (msgs[0].buf[2] << 16);
 586                                 reg_valid_bits |= I2C_MRXADDR_LOW | I2C_MRXADDR_MID | I2C_MRXADDR_HIGH;
 587                                 break;
 588                         default:
 589                                 return -EIO;
 590                         }
 591                 }
 592                 if ((msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 593                         i2c->msg = &msgs[1];
 594                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 595                         i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 596                         i2c->mode = I2C_CON_MOD_RRX;
 597                 } else if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 598                         i2c->msg = &msgs[1];
 599                         i2c_writel(addr | I2C_MRXADDR_LOW, i2c->regs + I2C_MRXADDR);
 600                         i2c_writel(reg_addr | reg_valid_bits, i2c->regs + I2C_MRXRADDR);
 601                         i2c->mode = I2C_CON_MOD_TRX;
 602                 } else
 603                         return -EIO;
 604         } else {
 605                 dev_err(i2c->dev, "This case(num > 2) has not been support now\n");
 606                 return -EIO;
 607         }
 608
 609         return 0;
 610 }
 611
 612 /* rockchip_i2c_doxfer
 613  *
 614  * this starts an i2c transfer
 615 */
 616 static int rockchip_i2c_doxfer(struct rockchip_i2c *i2c,
 617                               struct i2c_msg *msgs, int num)
 618 {
 619         unsigned long timeout, flags;
 620         int error = 0;
 621         /* 32 -- max transfer bytes
 622          * 2 -- addr bytes * 2
 623          * 3 -- max reg addr bytes
 624          * 9 -- cycles per bytes
 625          * max cycles: (32 + 2 + 3) * 9 --> 400 cycles
 626          */
 627         int msleep_time = 400 * 1000 / i2c->scl_rate;   // ms
 628         int can_sleep = !(in_atomic() || irqs_disabled());
 629
 630         spin_lock_irqsave(&i2c->lock, flags);
 631         i2c->addr = msgs[0].addr;
 632         if (msgs[0].flags & I2C_M_TEN) {
 633                 i2c->addr_1st = ((i2c->addr & 0x0300) >> 8) | 0x78;
 634                 i2c->addr_2nd = i2c->addr & 0x00ff;
 635         } else {
 636                 i2c->addr_1st = i2c->addr & 0x007f;
 637                 i2c->addr_2nd = 0;
 638         }
 639         i2c_dbg(i2c->dev, "addr: 0x%04x, addr_1st: 0x%02x, addr_2nd: 0x%02x\n",
 640                 i2c->addr, i2c->addr_1st, i2c->addr_2nd);
 641
 642         if (rockchip_i2c_set_master(i2c, msgs, num) < 0) {
 643                 spin_unlock_irqrestore(&i2c->lock, flags);
 644                 dev_err(i2c->dev, "addr[0x%04x] set master error\n", msgs[0].addr);
 645                 return -EIO;
 646         }
 647         i2c->msg_ptr = 0;
 648         i2c->error = 0;
 649         i2c->is_busy = 1;
 650         i2c->state = STATE_START;
 651         i2c->complete_what = 0;
 652         i2c_writel(I2C_STARTIEN, i2c->regs + I2C_IEN);
 653
 654         rockchip_i2c_enable(i2c, (i2c->count > 32) ? 0 : 1);    //if count > 32,  byte(32) send ack
 655
 656         if (can_sleep) {
 657                 long ret = msecs_to_jiffies(I2C_WAIT_TIMEOUT);
 658                 if (i2c->is_busy) {
 659                         DEFINE_WAIT(wait);
 660                         for (;;) {
 661                                 prepare_to_wait(&i2c->wait, &wait, TASK_UNINTERRUPTIBLE);
 662                                 if (i2c->is_busy == 0)
 663                                         break;
 664                                 spin_unlock_irqrestore(&i2c->lock, flags);
 665                                 ret = schedule_timeout(ret);
 666                                 spin_lock_irqsave(&i2c->lock, flags);
 667                                 if (!ret)
 668                                         break;
 669                         }
 670                         if (!ret && (i2c->is_busy == 0))
 671                                 ret = 1;
 672                         finish_wait(&i2c->wait, &wait);
 673                 }
 674                 timeout = ret;
 675         } else {
 676                 int cpu = raw_smp_processor_id();
 677                 int tmo = I2C_WAIT_TIMEOUT * USEC_PER_MSEC;
 678                 while (tmo-- && i2c->is_busy != 0) {
 679                         spin_unlock_irqrestore(&i2c->lock, flags);
 680                         udelay(1);
 681                         if (cpu == 0 && irqs_disabled()
 682                             && (i2c_readl(i2c->regs + I2C_IPD)
 683                                 & i2c_readl(i2c->regs + I2C_IEN))) {
 684                                 rockchip_i2c_irq(i2c->irq, i2c);
 685                         }
 686                         spin_lock_irqsave(&i2c->lock, flags);
 687                 }
 688                 timeout = (tmo <= 0) ? 0 : 1;
 689         }
 690
 691         error = i2c->error;
 692
 693         if (timeout == 0) {
 694                 unsigned int ipd = i2c_readl(i2c->regs + I2C_IPD);
 695                 if (error < 0)
 696                         i2c_dbg(i2c->dev, "error = %d\n", error);
 697                 else if (i2c->complete_what != COMPLETE_READ && i2c->complete_what != COMPLETE_WRITE) {
 698                         if (ipd & I2C_HOLD_SCL)
 699                                 dev_err(i2c->dev, "SCL was hold by slave\n");
 700                         dev_err(i2c->dev, "Addr[0x%04x] wait event timeout, state: %d, is_busy: %d, error: %d, complete_what: 0x%x, ipd: 0x%x\n",
 701                                 msgs[0].addr, i2c->state, i2c->is_busy, error, i2c->complete_what, ipd);
 702                         //rockchip_show_regs(i2c);
 703                         error = -ETIMEDOUT;
 704                         mdelay(msleep_time);
 705                         rockchip_i2c_send_stop(i2c);
 706                         mdelay(1);
 707                 } else
 708                         i2c_dbg(i2c->dev, "Addr[0x%02x] wait event timeout, but transfer complete\n", i2c->addr);
 709         }
 710
 711         i2c->state = STATE_IDLE;
 712
 713         i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
 714         rockchip_i2c_disable_irq(i2c);
 715         rockchip_i2c_disable(i2c);
 716         spin_unlock_irqrestore(&i2c->lock, flags);
 717
 718         if (error == -EAGAIN)
 719                 i2c_dbg(i2c->dev, "No ack(complete_what: 0x%x), Maybe slave(addr: 0x%04x) not exist or abnormal power-on\n",
 720                         i2c->complete_what, i2c->addr);
 721
 722         return error;
 723 }
 724
 725 /* rockchip_i2c_xfer
 726  *
 727  * first port of call from the i2c bus code when an message needs
 728  * transferring across the i2c bus.
 729 */
 730
 731 static int rockchip_i2c_xfer(struct i2c_adapter *adap,
 732                         struct i2c_msg *msgs, int num)
 733 {
 734         int ret;
 735         struct rockchip_i2c *i2c = i2c_get_adapdata(adap);
 736         unsigned long scl_rate = i2c->scl_rate;
 737         int can_sleep = !(in_atomic() || irqs_disabled());
 738
 739         if (can_sleep) {
 740                 mutex_lock(&i2c->suspend_lock);
 741                 if (i2c->suspended) {
 742                         dev_err(i2c->dev, "i2c is suspended\n");
 743                         mutex_unlock(&i2c->suspend_lock);
 744                         return -EIO;
 745                 }
 746         }
 747
 748         clk_enable(i2c->clk);
 749         if (i2c->check_idle) {
 750                 int state, retry = 10;
 751                 while (retry) {
 752                         state = rockchip_i2c_check_idle(i2c);
 753                         if (state == I2C_IDLE)
 754                                 break;
 755                         if (can_sleep)
 756                                 msleep(10);
 757                         else
 758                                 mdelay(10);
 759                         retry--;
 760                 }
 761                 if (retry == 0) {
 762                         dev_err(i2c->dev, "i2c is not in idle(state = %d)\n", state);
 763                         ret = -EIO;
 764                         goto out;
 765                 }
 766         }
 767
 768 #ifdef CONFIG_I2C_ROCKCHIP_COMPAT
 769         if (msgs[0].scl_rate <= 400000 && msgs[0].scl_rate >= 10000)
 770                 scl_rate = msgs[0].scl_rate;
 771         else if (msgs[0].scl_rate > 400000) {
 772                 dev_warn_ratelimited(i2c->dev, "Warning: addr[0x%04x] msg[0].scl_rate( = %dKhz) is too high!",
 773                         msgs[0].addr, msgs[0].scl_rate/1000);
 774                 scl_rate = 400000;
 775         } else {
 776                 dev_warn_ratelimited(i2c->dev, "Warning: addr[0x%04x] msg[0].scl_rate( = %dKhz) is too low!",
 777                         msgs[0].addr, msgs[0].scl_rate/1000);
 778                 scl_rate = 100000;
 779         }
 780
 781         rockchip_i2c_set_clk(i2c, scl_rate);
 782 #endif
 783
 784         i2c_dbg(i2c->dev, "i2c transfer start: addr: 0x%04x, scl_reate: %ldKhz, len: %d\n", msgs[0].addr, scl_rate/1000, num);
 785         ret = rockchip_i2c_doxfer(i2c, msgs, num);
 786         i2c_dbg(i2c->dev, "i2c transfer stop: addr: 0x%04x, state: %d, ret: %d\n", msgs[0].addr, ret, i2c->state);
 787
 788 out:
 789         clk_disable(i2c->clk);
 790         if (can_sleep)
 791                 mutex_unlock(&i2c->suspend_lock);
 792
 793         return (ret < 0) ? ret : num;
 794 }
 795
 796 /* declare our i2c functionality */
 797 static u32 rockchip_i2c_func(struct i2c_adapter *adap)
 798 {
 799         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 800 }
 801
 802 /* i2c bus registration info */
 803
 804 static const struct i2c_algorithm rockchip_i2c_algorithm = {
 805         .master_xfer            = rockchip_i2c_xfer,
 806         .functionality          = rockchip_i2c_func,
 807 };
 808
 809 /* rockchip_i2c_probe
 810  *
 811  * called by the bus driver when a suitable device is found
 812 */
 813
 814 static int rockchip_i2c_probe(struct platform_device *pdev)
 815 {
 816         struct rockchip_i2c *i2c = NULL;
 817         struct resource *res;
 818         struct device_node *np = pdev->dev.of_node;
 819         int ret;
 820
 821         if (!np) {
 822                 dev_err(&pdev->dev, "Missing device tree node.\n");
 823                 return -EINVAL;
 824         }
 825
 826         i2c = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_i2c), GFP_KERNEL);
 827         if (!i2c) {
 828                 dev_err(&pdev->dev, "no memory for state\n");
 829                 return -ENOMEM;
 830         }
 831
 832         strlcpy(i2c->adap.name, "rockchip_i2c", sizeof(i2c->adap.name));
 833         i2c->dev = &pdev->dev;
 834         i2c->adap.owner = THIS_MODULE;
 835         i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 836         i2c->adap.retries = 2;
 837         i2c->adap.timeout = msecs_to_jiffies(100);
 838         i2c->adap.algo = &rockchip_i2c_algorithm;
 839         i2c_set_adapdata(&i2c->adap, i2c);
 840         i2c->adap.dev.parent = &pdev->dev;
 841         i2c->adap.dev.of_node = np;
 842
 843         spin_lock_init(&i2c->lock);
 844         init_waitqueue_head(&i2c->wait);
 845
 846         /* map the registers */
 847         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 848         i2c->regs = devm_ioremap_resource(&pdev->dev, res);
 849         if (IS_ERR(i2c->regs))
 850                 return PTR_ERR(i2c->regs);
 851
 852         i2c_dbg(&pdev->dev, "registers %p (%p, %p)\n",
 853                 i2c->regs, i2c->ioarea, res);
 854
 855         i2c->check_idle = true;
 856         of_property_read_u32(np, "rockchip,check-idle", &i2c->check_idle);
 857         if (i2c->check_idle) {
 858                 i2c->sda_gpio = of_get_gpio(np, 0);
 859                 if (!gpio_is_valid(i2c->sda_gpio)) {
 860                         dev_err(&pdev->dev, "sda gpio is invalid\n");
 861                         return -EINVAL;
 862                 }
 863                 ret = devm_gpio_request(&pdev->dev, i2c->sda_gpio, dev_name(&i2c->adap.dev));
 864                 if (ret) {
 865                         dev_err(&pdev->dev, "failed to request sda gpio\n");
 866                         return ret;
 867                 }
 868                 i2c->scl_gpio = of_get_gpio(np, 1);
 869                 if (!gpio_is_valid(i2c->scl_gpio)) {
 870                         dev_err(&pdev->dev, "scl gpio is invalid\n");
 871                         return -EINVAL;
 872                 }
 873                 ret = devm_gpio_request(&pdev->dev, i2c->scl_gpio, dev_name(&i2c->adap.dev));
 874                 if (ret) {
 875                         dev_err(&pdev->dev, "failed to request scl gpio\n");
 876                         return ret;
 877                 }
 878                 i2c->gpio_state = pinctrl_lookup_state(i2c->dev->pins->p, "gpio");
 879                 if (IS_ERR(i2c->gpio_state)) {
 880                         dev_err(&pdev->dev, "no gpio pinctrl state\n");
 881                         return PTR_ERR(i2c->gpio_state);
 882                 }
 883                 pinctrl_select_state(i2c->dev->pins->p, i2c->gpio_state);
 884                 gpio_direction_input(i2c->sda_gpio);
 885                 gpio_direction_input(i2c->scl_gpio);
 886                 pinctrl_select_state(i2c->dev->pins->p, i2c->dev->pins->default_state);
 887         }
 888
 889         /* setup info block for the i2c core */
 890         ret = i2c_add_adapter(&i2c->adap);
 891         if (ret < 0) {
 892                 dev_err(&pdev->dev, "failed to add adapter\n");
 893                 return ret;
 894         }
 895
 896         platform_set_drvdata(pdev, i2c);
 897
 898         /* find the clock and enable it */
 899         i2c->clk = devm_clk_get(&pdev->dev, NULL);
 900         if (IS_ERR(i2c->clk)) {
 901                 dev_err(&pdev->dev, "cannot get clock\n");
 902                 return PTR_ERR(i2c->clk);
 903         }
 904
 905         i2c_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
 906
 907         /* find the IRQ for this unit (note, this relies on the init call to
 908          * ensure no current IRQs pending
 909          */
 910         i2c->irq = ret = platform_get_irq(pdev, 0);
 911         if (ret < 0) {
 912                 dev_err(&pdev->dev, "cannot find IRQ\n");
 913                 return ret;
 914         }
 915
 916         ret = devm_request_irq(&pdev->dev, i2c->irq, rockchip_i2c_irq, 0,
 917                         dev_name(&i2c->adap.dev), i2c);
 918         if (ret) {
 919                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
 920                 return ret;
 921         }
 922
 923         ret = clk_prepare(i2c->clk);
 924         if (ret < 0) {
 925                 dev_err(&pdev->dev, "Could not prepare clock\n");
 926                 return ret;
 927         }
 928
 929         i2c->i2c_rate = clk_get_rate(i2c->clk);
 930
 931         rockchip_i2c_init_hw(i2c, 100 * 1000);
 932         dev_info(&pdev->dev, "%s: Rockchip I2C adapter\n", dev_name(&i2c->adap.dev));
 933
 934         of_i2c_register_devices(&i2c->adap);
 935         mutex_init(&i2c->suspend_lock);
 936
 937         return 0;
 938 }
 939
 940 /* rockchip_i2c_remove
 941  *
 942  * called when device is removed from the bus
 943 */
 944
 945 static int rockchip_i2c_remove(struct platform_device *pdev)
 946 {
 947         struct rockchip_i2c *i2c = platform_get_drvdata(pdev);
 948
 949         mutex_lock(&i2c->suspend_lock);
 950         i2c->suspended = 1;
 951         i2c_del_adapter(&i2c->adap);
 952         clk_unprepare(i2c->clk);
 953         mutex_unlock(&i2c->suspend_lock);
 954
 955         return 0;
 956 }
 957
 958 /* rockchip_i2c_shutdown
 959  *
 960  * called when device is shutdown from the bus
 961 */
 962 static void rockchip_i2c_shutdown(struct platform_device *pdev)
 963 {
 964         struct rockchip_i2c *i2c = platform_get_drvdata(pdev);
 965
 966         mutex_lock(&i2c->suspend_lock);
 967         i2c->suspended = 1;
 968         mutex_unlock(&i2c->suspend_lock);
 969 }
 970
 971 #ifdef CONFIG_PM
 972 static int rockchip_i2c_suspend_noirq(struct device *dev)
 973 {
 974         struct platform_device *pdev = to_platform_device(dev);
 975         struct rockchip_i2c *i2c = platform_get_drvdata(pdev);
 976
 977         mutex_lock(&i2c->suspend_lock);
 978         i2c->suspended = 1;
 979         pinctrl_pm_select_sleep_state(dev);
 980         mutex_unlock(&i2c->suspend_lock);
 981
 982         return 0;
 983 }
 984
 985 static int rockchip_i2c_resume_noirq(struct device *dev)
 986 {
 987         struct platform_device *pdev = to_platform_device(dev);
 988         struct rockchip_i2c *i2c = platform_get_drvdata(pdev);
 989
 990         mutex_lock(&i2c->suspend_lock);
 991         pinctrl_pm_select_default_state(dev);
 992         rockchip_i2c_init_hw(i2c, i2c->scl_rate);
 993         i2c->suspended = 0;
 994         mutex_unlock(&i2c->suspend_lock);
 995
 996         return 0;
 997 }
 998
 999 static const struct dev_pm_ops rockchip_i2c_dev_pm_ops = {
1000         .suspend_noirq = rockchip_i2c_suspend_noirq,
1001         .resume_noirq = rockchip_i2c_resume_noirq,
1002 };
1003
1004 #define ROCKCHIP_I2C_PM_OPS (&rockchip_i2c_dev_pm_ops)
1005 #else
1006 #define ROCKCHIP_I2C_PM_OPS NULL
1007 #endif
1008
1009 static const struct of_device_id rockchip_i2c_of_match[] = {
1010         { .compatible = "rockchip,rk30-i2c", .data = NULL, },
1011         {},
1012 };
1013 MODULE_DEVICE_TABLE(of, rockchip_i2c_of_match);
1014
1015 static struct platform_driver rockchip_i2c_driver = {
1016         .probe          = rockchip_i2c_probe,
1017         .remove         = rockchip_i2c_remove,
1018         .shutdown       = rockchip_i2c_shutdown,
1019         .driver         = {
1020                 .owner  = THIS_MODULE,
1021                 .name   = "rockchip_i2c",
1022                 .pm     = ROCKCHIP_I2C_PM_OPS,
1023                 .of_match_table = of_match_ptr(rockchip_i2c_of_match),
1024         },
1025 };
1026
1027 static int __init rockchip_i2c_init_driver(void)
1028 {
1029         return platform_driver_register(&rockchip_i2c_driver);
1030 }
1031
1032 subsys_initcall(rockchip_i2c_init_driver);
1033
1034 static void __exit rockchip_i2c_exit_driver(void)
1035 {
1036         platform_driver_unregister(&rockchip_i2c_driver);
1037 }
1038
1039 module_exit(rockchip_i2c_exit_driver);
1040
1041 static int detect_read(struct i2c_client *client, char *buf, int len)
1042 {
1043         struct i2c_msg msg;
1044
1045         msg.addr = client->addr;
1046         msg.flags = client->flags | I2C_M_RD;
1047         msg.buf = buf;
1048         msg.len = len;
1049 #ifdef CONFIG_I2C_ROCKCHIP_COMPAT
1050         msg.scl_rate = 100 * 1000;
1051 #endif
1052
1053         return i2c_transfer(client->adapter, &msg, 1);
1054 }
1055
1056 static void detect_set_client(struct i2c_client *client, __u16 addr, int nr)
1057 {
1058         client->flags = 0;
1059         client->addr = addr;
1060         client->adapter = i2c_get_adapter(nr);
1061 }
1062
1063 static void slave_detect(int nr)
1064 {
1065         int ret = 0;
1066         unsigned short addr;
1067         char val[8];
1068         char buf[6 * 0x80 + 20];
1069         struct i2c_client client;
1070
1071         memset(buf, 0, 6 * 0x80 + 20);
1072
1073         sprintf(buf, "I2c%d slave list: ", nr);
1074         do {
1075                 for (addr = 0x01; addr < 0x80; addr++) {
1076                         detect_set_client(&client, addr, nr);
1077                         ret = detect_read(&client, val, 1);
1078                         if (ret > 0)
1079                                 sprintf(buf, "%s  0x%02x", buf, addr);
1080                 }
1081                 printk("%s\n", buf);
1082         }
1083         while (0);
1084 }
1085
1086 static ssize_t i2c_detect_write(struct file *file,
1087                         const char __user *buf, size_t count, loff_t *offset)
1088 {
1089         char nr_buf[8];
1090         int nr = 0, ret;
1091
1092         if (count > 4)
1093                 return -EFAULT;
1094         ret = copy_from_user(nr_buf, buf, count);
1095         if (ret < 0)
1096                 return -EFAULT;
1097
1098         sscanf(nr_buf, "%d", &nr);
1099         if (nr >= 5 || nr < 0)
1100                 return -EFAULT;
1101
1102         slave_detect(nr);
1103
1104         return count;
1105 }
1106
1107 static const struct file_operations i2c_detect_fops = {
1108         .write = i2c_detect_write,
1109 };
1110
1111 static struct miscdevice i2c_detect_device = {
1112         .minor = MISC_DYNAMIC_MINOR,
1113         .name = "i2c_detect",
1114         .fops = &i2c_detect_fops,
1115 };
1116
1117 static int __init i2c_detect_init(void)
1118 {
1119         return misc_register(&i2c_detect_device);
1120 }
1121
1122 static void __exit i2c_detect_exit(void)
1123 {
1124         misc_deregister(&i2c_detect_device);
1125 }
1126
1127 module_init(i2c_detect_init);
1128 module_exit(i2c_detect_exit);
1129
1130 MODULE_DESCRIPTION("Driver for Rockchip I2C Bus");
1131 MODULE_AUTHOR("kfx, kfx@rock-chips.com");
1132 MODULE_LICENSE("GPL");