2 * SuperH Mobile I2C Controller
4 * Copyright (C) 2008 Magnus Damm
6 * Portions of the code based on out-of-tree driver i2c-sh7343.c
7 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/i2c.h>
26 #include <linux/err.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/clk.h>
30 #include <linux/slab.h>
31 #include <linux/of_device.h>
32 #include <linux/i2c/i2c-sh_mobile.h>
34 /* Transmit operation: */
37 /* BUS: S A8 ACK P(*) */
44 /* BUS: S A8 ACK D8(1) ACK P(*) */
45 /* IRQ: DTE WAIT WAIT */
51 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
52 /* IRQ: DTE WAIT WAIT WAIT */
55 /* ICDR: A8 D8(1) D8(2) */
57 /* 3 bytes or more, +---------+ gets repeated */
60 /* Receive operation: */
62 /* 0 byte receive - not supported since slave may hold SDA low */
64 /* 1 byte receive [TX] | [RX] */
65 /* BUS: S A8 ACK | D8(1) ACK P(*) */
66 /* IRQ: DTE WAIT | WAIT DTE */
67 /* ICIC: -DTE | +DTE */
68 /* ICCR: 0x94 0x81 | 0xc0 */
69 /* ICDR: A8 | D8(1) */
71 /* 2 byte receive [TX]| [RX] */
72 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
73 /* IRQ: DTE WAIT | WAIT WAIT DTE */
74 /* ICIC: -DTE | +DTE */
75 /* ICCR: 0x94 0x81 | 0xc0 */
76 /* ICDR: A8 | D8(1) D8(2) */
78 /* 3 byte receive [TX] | [RX] (*) */
79 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
80 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
81 /* ICIC: -DTE | +DTE */
82 /* ICCR: 0x94 0x81 | 0xc0 */
83 /* ICDR: A8 | D8(1) D8(2) D8(3) */
85 /* 4 bytes or more, this part is repeated +---------+ */
88 /* Interrupt order and BUSY flag */
90 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
91 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
93 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
95 /* WAIT IRQ ________________________________/ \___________ */
96 /* TACK IRQ ____________________________________/ \_______ */
97 /* DTE IRQ __________________________________________/ \_ */
98 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
99 /* _______________________________________________ */
102 /* (*) The STOP condition is only sent by the master at the end of the last */
103 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
104 /* only cleared after the STOP condition, so, between messages we have to */
105 /* poll for the DTE bit. */
108 enum sh_mobile_i2c_op {
119 struct sh_mobile_i2c_data {
122 struct i2c_adapter adap;
123 unsigned long bus_speed;
124 unsigned int clks_per_count;
132 wait_queue_head_t wait;
139 struct sh_mobile_dt_config {
143 #define IIC_FLAG_HAS_ICIC67 (1 << 0)
145 #define STANDARD_MODE 100000
146 #define FAST_MODE 400000
148 /* Register offsets */
157 #define ICCR_ICE 0x80
158 #define ICCR_RACK 0x40
159 #define ICCR_TRS 0x10
160 #define ICCR_BBSY 0x04
161 #define ICCR_SCP 0x01
163 #define ICSR_SCLM 0x80
164 #define ICSR_SDAM 0x40
166 #define ICSR_BUSY 0x10
168 #define ICSR_TACK 0x04
169 #define ICSR_WAIT 0x02
170 #define ICSR_DTE 0x01
172 #define ICIC_ICCLB8 0x80
173 #define ICIC_ICCHB8 0x40
174 #define ICIC_ALE 0x08
175 #define ICIC_TACKE 0x04
176 #define ICIC_WAITE 0x02
177 #define ICIC_DTEE 0x01
179 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
184 iowrite8(data, pd->reg + offs);
187 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
189 return ioread8(pd->reg + offs);
192 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
193 unsigned char set, unsigned char clr)
195 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
198 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
201 * Conditional expression:
202 * ICCL >= COUNT_CLK * (tLOW + tf)
204 * SH-Mobile IIC hardware starts counting the LOW period of
205 * the SCL signal (tLOW) as soon as it pulls the SCL line.
206 * In order to meet the tLOW timing spec, we need to take into
207 * account the fall time of SCL signal (tf). Default tf value
208 * should be 0.3 us, for safety.
210 return (((count_khz * (tLOW + tf)) + 5000) / 10000);
213 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
216 * Conditional expression:
217 * ICCH >= COUNT_CLK * (tHIGH + tf)
219 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
220 * and can ignore it. SH-Mobile IIC controller starts counting
221 * the HIGH period of the SCL signal (tHIGH) after the SCL input
222 * voltage increases at VIH.
224 * Afterward it turned out calculating ICCH using only tHIGH spec
225 * will result in violation of the tHD;STA timing spec. We need
226 * to take into account the fall time of SDA signal (tf) at START
227 * condition, in order to meet both tHIGH and tHD;STA specs.
229 return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
232 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
234 unsigned long i2c_clk_khz;
238 /* Get clock rate after clock is enabled */
239 clk_prepare_enable(pd->clk);
240 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
241 clk_disable_unprepare(pd->clk);
242 i2c_clk_khz /= pd->clks_per_count;
244 if (pd->bus_speed == STANDARD_MODE) {
245 tLOW = 47; /* tLOW = 4.7 us */
246 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
247 tf = 3; /* tf = 0.3 us */
248 } else if (pd->bus_speed == FAST_MODE) {
249 tLOW = 13; /* tLOW = 1.3 us */
250 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
251 tf = 3; /* tf = 0.3 us */
253 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
258 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
259 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
261 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
262 if (pd->iccl > max_val || pd->icch > max_val) {
263 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
268 /* one more bit of ICCL in ICIC */
269 if (pd->iccl & 0x100)
270 pd->icic |= ICIC_ICCLB8;
272 pd->icic &= ~ICIC_ICCLB8;
274 /* one more bit of ICCH in ICIC */
275 if (pd->icch & 0x100)
276 pd->icic |= ICIC_ICCHB8;
278 pd->icic &= ~ICIC_ICCHB8;
283 static void activate_ch(struct sh_mobile_i2c_data *pd)
285 /* Wake up device and enable clock */
286 pm_runtime_get_sync(pd->dev);
287 clk_prepare_enable(pd->clk);
289 /* Enable channel and configure rx ack */
290 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
292 /* Mask all interrupts */
296 iic_wr(pd, ICCL, pd->iccl & 0xff);
297 iic_wr(pd, ICCH, pd->icch & 0xff);
300 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
302 /* Clear/disable interrupts */
306 /* Disable channel */
307 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
309 /* Disable clock and mark device as idle */
310 clk_disable_unprepare(pd->clk);
311 pm_runtime_put_sync(pd->dev);
314 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
315 enum sh_mobile_i2c_op op, unsigned char data)
317 unsigned char ret = 0;
320 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
322 spin_lock_irqsave(&pd->lock, flags);
325 case OP_START: /* issue start and trigger DTE interrupt */
326 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
328 case OP_TX_FIRST: /* disable DTE interrupt and write data */
329 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
330 iic_wr(pd, ICDR, data);
332 case OP_TX: /* write data */
333 iic_wr(pd, ICDR, data);
335 case OP_TX_STOP: /* write data and issue a stop afterwards */
336 iic_wr(pd, ICDR, data);
337 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
338 : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
340 case OP_TX_TO_RX: /* select read mode */
341 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
343 case OP_RX: /* just read data */
344 ret = iic_rd(pd, ICDR);
346 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
348 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
349 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
351 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
353 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
354 ret = iic_rd(pd, ICDR);
355 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
359 spin_unlock_irqrestore(&pd->lock, flags);
361 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
365 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
367 return pd->pos == -1;
370 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
372 return pd->pos == pd->msg->len - 1;
375 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
380 *buf = (pd->msg->addr & 0x7f) << 1;
381 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
384 *buf = pd->msg->buf[pd->pos];
388 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
392 if (pd->pos == pd->msg->len)
395 sh_mobile_i2c_get_data(pd, &data);
397 if (sh_mobile_i2c_is_last_byte(pd))
398 i2c_op(pd, OP_TX_STOP, data);
399 else if (sh_mobile_i2c_is_first_byte(pd))
400 i2c_op(pd, OP_TX_FIRST, data);
402 i2c_op(pd, OP_TX, data);
408 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
415 sh_mobile_i2c_get_data(pd, &data);
417 if (sh_mobile_i2c_is_first_byte(pd))
418 i2c_op(pd, OP_TX_FIRST, data);
420 i2c_op(pd, OP_TX, data);
425 i2c_op(pd, OP_TX_TO_RX, 0);
429 real_pos = pd->pos - 2;
431 if (pd->pos == pd->msg->len) {
433 i2c_op(pd, OP_RX_STOP, 0);
436 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
438 data = i2c_op(pd, OP_RX, 0);
441 pd->msg->buf[real_pos] = data;
445 return pd->pos == (pd->msg->len + 2);
448 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
450 struct platform_device *dev = dev_id;
451 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
455 sr = iic_rd(pd, ICSR);
456 pd->sr |= sr; /* remember state */
458 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
459 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
460 pd->pos, pd->msg->len);
462 if (sr & (ICSR_AL | ICSR_TACK)) {
463 /* don't interrupt transaction - continue to issue stop */
464 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
466 } else if (pd->msg->flags & I2C_M_RD)
467 wakeup = sh_mobile_i2c_isr_rx(pd);
469 wakeup = sh_mobile_i2c_isr_tx(pd);
471 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
472 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
479 /* defeat write posting to avoid spurious WAIT interrupts */
485 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
488 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
489 dev_err(pd->dev, "Unsupported zero length i2c read\n");
494 /* Initialize channel registers */
495 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
497 /* Enable channel and configure rx ack */
498 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
501 iic_wr(pd, ICCL, pd->iccl & 0xff);
502 iic_wr(pd, ICCH, pd->icch & 0xff);
509 /* Enable all interrupts to begin with */
510 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
514 static int poll_dte(struct sh_mobile_i2c_data *pd)
518 for (i = 1000; i; i--) {
519 u_int8_t val = iic_rd(pd, ICSR);
530 return i ? 0 : -ETIMEDOUT;
533 static int poll_busy(struct sh_mobile_i2c_data *pd)
537 for (i = 1000; i; i--) {
538 u_int8_t val = iic_rd(pd, ICSR);
540 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
542 /* the interrupt handler may wake us up before the
543 * transfer is finished, so poll the hardware
546 if (!(val & ICSR_BUSY)) {
547 /* handle missing acknowledge and arbitration lost */
559 return i ? 0 : -ETIMEDOUT;
562 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
563 struct i2c_msg *msgs,
566 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
573 /* Process all messages */
574 for (i = 0; i < num; i++) {
575 bool do_start = pd->send_stop || !i;
577 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
579 err = start_ch(pd, msg, do_start);
584 i2c_op(pd, OP_START, 0);
586 /* The interrupt handler takes care of the rest... */
587 k = wait_event_timeout(pd->wait,
588 pd->sr & (ICSR_TACK | SW_DONE),
591 dev_err(pd->dev, "Transfer request timed out\n");
611 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
613 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
616 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
617 .functionality = sh_mobile_i2c_func,
618 .master_xfer = sh_mobile_i2c_xfer,
621 static const struct sh_mobile_dt_config default_dt_config = {
625 static const struct sh_mobile_dt_config rcar_gen2_dt_config = {
629 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
630 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
631 { .compatible = "renesas,iic-r8a7790", .data = &rcar_gen2_dt_config },
632 { .compatible = "renesas,iic-r8a7791", .data = &rcar_gen2_dt_config },
633 { .compatible = "renesas,iic-r8a7792", .data = &rcar_gen2_dt_config },
634 { .compatible = "renesas,iic-r8a7793", .data = &rcar_gen2_dt_config },
635 { .compatible = "renesas,iic-r8a7794", .data = &rcar_gen2_dt_config },
638 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
640 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev)
642 struct resource *res;
646 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
647 for (n = res->start; n <= res->end; n++) {
648 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
649 0, dev_name(&dev->dev), dev);
651 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
658 return k > 0 ? 0 : -ENOENT;
661 static int sh_mobile_i2c_probe(struct platform_device *dev)
663 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
664 struct sh_mobile_i2c_data *pd;
665 struct i2c_adapter *adap;
666 struct resource *res;
670 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
674 pd->clk = devm_clk_get(&dev->dev, NULL);
675 if (IS_ERR(pd->clk)) {
676 dev_err(&dev->dev, "cannot get clock\n");
677 return PTR_ERR(pd->clk);
680 ret = sh_mobile_i2c_hook_irqs(dev);
685 platform_set_drvdata(dev, pd);
687 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
689 pd->reg = devm_ioremap_resource(&dev->dev, res);
691 return PTR_ERR(pd->reg);
693 /* Use platform data bus speed or STANDARD_MODE */
694 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
695 pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
697 pd->clks_per_count = 1;
699 if (dev->dev.of_node) {
700 const struct of_device_id *match;
702 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
704 const struct sh_mobile_dt_config *config;
706 config = match->data;
707 pd->clks_per_count = config->clks_per_count;
710 if (pdata && pdata->bus_speed)
711 pd->bus_speed = pdata->bus_speed;
712 if (pdata && pdata->clks_per_count)
713 pd->clks_per_count = pdata->clks_per_count;
716 /* The IIC blocks on SH-Mobile ARM processors
717 * come with two new bits in ICIC.
719 if (resource_size(res) > 0x17)
720 pd->flags |= IIC_FLAG_HAS_ICIC67;
722 ret = sh_mobile_i2c_init(pd);
726 /* Enable Runtime PM for this device.
728 * Also tell the Runtime PM core to ignore children
729 * for this device since it is valid for us to suspend
730 * this I2C master driver even though the slave devices
731 * on the I2C bus may not be suspended.
733 * The state of the I2C hardware bus is unaffected by
734 * the Runtime PM state.
736 pm_suspend_ignore_children(&dev->dev, true);
737 pm_runtime_enable(&dev->dev);
739 /* setup the private data */
741 i2c_set_adapdata(adap, pd);
743 adap->owner = THIS_MODULE;
744 adap->algo = &sh_mobile_i2c_algorithm;
745 adap->dev.parent = &dev->dev;
748 adap->dev.of_node = dev->dev.of_node;
750 strlcpy(adap->name, dev->name, sizeof(adap->name));
752 spin_lock_init(&pd->lock);
753 init_waitqueue_head(&pd->wait);
755 ret = i2c_add_numbered_adapter(adap);
757 dev_err(&dev->dev, "cannot add numbered adapter\n");
762 "I2C adapter %d with bus speed %lu Hz (L/H=0x%x/0x%x)\n",
763 adap->nr, pd->bus_speed, pd->iccl, pd->icch);
768 static int sh_mobile_i2c_remove(struct platform_device *dev)
770 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
772 i2c_del_adapter(&pd->adap);
773 pm_runtime_disable(&dev->dev);
777 static int sh_mobile_i2c_runtime_nop(struct device *dev)
779 /* Runtime PM callback shared between ->runtime_suspend()
780 * and ->runtime_resume(). Simply returns success.
782 * This driver re-initializes all registers after
783 * pm_runtime_get_sync() anyway so there is no need
784 * to save and restore registers here.
789 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
790 .runtime_suspend = sh_mobile_i2c_runtime_nop,
791 .runtime_resume = sh_mobile_i2c_runtime_nop,
794 static struct platform_driver sh_mobile_i2c_driver = {
796 .name = "i2c-sh_mobile",
797 .owner = THIS_MODULE,
798 .pm = &sh_mobile_i2c_dev_pm_ops,
799 .of_match_table = sh_mobile_i2c_dt_ids,
801 .probe = sh_mobile_i2c_probe,
802 .remove = sh_mobile_i2c_remove,
805 static int __init sh_mobile_i2c_adap_init(void)
807 return platform_driver_register(&sh_mobile_i2c_driver);
810 static void __exit sh_mobile_i2c_adap_exit(void)
812 platform_driver_unregister(&sh_mobile_i2c_driver);
815 subsys_initcall(sh_mobile_i2c_adap_init);
816 module_exit(sh_mobile_i2c_adap_exit);
818 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
819 MODULE_AUTHOR("Magnus Damm");
820 MODULE_LICENSE("GPL v2");
821 MODULE_ALIAS("platform:i2c-sh_mobile");