2 * SuperH Mobile I2C Controller
4 * Copyright (C) 2008 Magnus Damm
6 * Portions of the code based on out-of-tree driver i2c-sh7343.c
7 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/of_i2c.h>
31 #include <linux/err.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/clk.h>
35 #include <linux/slab.h>
36 #include <linux/i2c/i2c-sh_mobile.h>
38 /* Transmit operation: */
48 /* BUS: S A8 ACK D8(1) ACK P */
49 /* IRQ: DTE WAIT WAIT */
55 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P */
56 /* IRQ: DTE WAIT WAIT WAIT */
59 /* ICDR: A8 D8(1) D8(2) */
61 /* 3 bytes or more, +---------+ gets repeated */
64 /* Receive operation: */
66 /* 0 byte receive - not supported since slave may hold SDA low */
68 /* 1 byte receive [TX] | [RX] */
69 /* BUS: S A8 ACK | D8(1) ACK P */
70 /* IRQ: DTE WAIT | WAIT DTE */
71 /* ICIC: -DTE | +DTE */
72 /* ICCR: 0x94 0x81 | 0xc0 */
73 /* ICDR: A8 | D8(1) */
75 /* 2 byte receive [TX]| [RX] */
76 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P */
77 /* IRQ: DTE WAIT | WAIT WAIT DTE */
78 /* ICIC: -DTE | +DTE */
79 /* ICCR: 0x94 0x81 | 0xc0 */
80 /* ICDR: A8 | D8(1) D8(2) */
82 /* 3 byte receive [TX] | [RX] */
83 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
84 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
85 /* ICIC: -DTE | +DTE */
86 /* ICCR: 0x94 0x81 | 0xc0 */
87 /* ICDR: A8 | D8(1) D8(2) D8(3) */
89 /* 4 bytes or more, this part is repeated +---------+ */
92 /* Interrupt order and BUSY flag */
94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
95 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
97 /* S D7 D6 D5 D4 D3 D2 D1 D0 P */
99 /* WAIT IRQ ________________________________/ \___________ */
100 /* TACK IRQ ____________________________________/ \_______ */
101 /* DTE IRQ __________________________________________/ \_ */
102 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
103 /* _______________________________________________ */
107 enum sh_mobile_i2c_op {
118 struct sh_mobile_i2c_data {
121 struct i2c_adapter adap;
122 unsigned long bus_speed;
123 unsigned int clks_per_count;
131 wait_queue_head_t wait;
137 #define IIC_FLAG_HAS_ICIC67 (1 << 0)
139 #define STANDARD_MODE 100000
140 #define FAST_MODE 400000
142 /* Register offsets */
151 #define ICCR_ICE 0x80
152 #define ICCR_RACK 0x40
153 #define ICCR_TRS 0x10
154 #define ICCR_BBSY 0x04
155 #define ICCR_SCP 0x01
157 #define ICSR_SCLM 0x80
158 #define ICSR_SDAM 0x40
160 #define ICSR_BUSY 0x10
162 #define ICSR_TACK 0x04
163 #define ICSR_WAIT 0x02
164 #define ICSR_DTE 0x01
166 #define ICIC_ICCLB8 0x80
167 #define ICIC_ICCHB8 0x40
168 #define ICIC_ALE 0x08
169 #define ICIC_TACKE 0x04
170 #define ICIC_WAITE 0x02
171 #define ICIC_DTEE 0x01
173 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
178 iowrite8(data, pd->reg + offs);
181 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
183 return ioread8(pd->reg + offs);
186 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
187 unsigned char set, unsigned char clr)
189 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
192 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf, int offset)
195 * Conditional expression:
196 * ICCL >= COUNT_CLK * (tLOW + tf)
198 * SH-Mobile IIC hardware starts counting the LOW period of
199 * the SCL signal (tLOW) as soon as it pulls the SCL line.
200 * In order to meet the tLOW timing spec, we need to take into
201 * account the fall time of SCL signal (tf). Default tf value
202 * should be 0.3 us, for safety.
204 return (((count_khz * (tLOW + tf)) + 5000) / 10000) + offset;
207 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf, int offset)
210 * Conditional expression:
211 * ICCH >= COUNT_CLK * (tHIGH + tf)
213 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
214 * and can ignore it. SH-Mobile IIC controller starts counting
215 * the HIGH period of the SCL signal (tHIGH) after the SCL input
216 * voltage increases at VIH.
218 * Afterward it turned out calculating ICCH using only tHIGH spec
219 * will result in violation of the tHD;STA timing spec. We need
220 * to take into account the fall time of SDA signal (tf) at START
221 * condition, in order to meet both tHIGH and tHD;STA specs.
223 return (((count_khz * (tHIGH + tf)) + 5000) / 10000) + offset;
226 static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
228 unsigned long i2c_clk_khz;
232 /* Get clock rate after clock is enabled */
234 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
235 i2c_clk_khz /= pd->clks_per_count;
237 if (pd->bus_speed == STANDARD_MODE) {
238 tLOW = 47; /* tLOW = 4.7 us */
239 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
240 tf = 3; /* tf = 0.3 us */
241 offset = 0; /* No offset */
242 } else if (pd->bus_speed == FAST_MODE) {
243 tLOW = 13; /* tLOW = 1.3 us */
244 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
245 tf = 3; /* tf = 0.3 us */
246 offset = 0; /* No offset */
248 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
253 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf, offset);
254 /* one more bit of ICCL in ICIC */
255 if ((pd->iccl > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67))
256 pd->icic |= ICIC_ICCLB8;
258 pd->icic &= ~ICIC_ICCLB8;
260 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf, offset);
261 /* one more bit of ICCH in ICIC */
262 if ((pd->icch > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67))
263 pd->icic |= ICIC_ICCHB8;
265 pd->icic &= ~ICIC_ICCHB8;
268 clk_disable(pd->clk);
271 static void activate_ch(struct sh_mobile_i2c_data *pd)
273 /* Wake up device and enable clock */
274 pm_runtime_get_sync(pd->dev);
277 /* Enable channel and configure rx ack */
278 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
280 /* Mask all interrupts */
284 iic_wr(pd, ICCL, pd->iccl & 0xff);
285 iic_wr(pd, ICCH, pd->icch & 0xff);
288 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
290 /* Clear/disable interrupts */
294 /* Disable channel */
295 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
297 /* Disable clock and mark device as idle */
298 clk_disable(pd->clk);
299 pm_runtime_put_sync(pd->dev);
302 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
303 enum sh_mobile_i2c_op op, unsigned char data)
305 unsigned char ret = 0;
308 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
310 spin_lock_irqsave(&pd->lock, flags);
313 case OP_START: /* issue start and trigger DTE interrupt */
314 iic_wr(pd, ICCR, 0x94);
316 case OP_TX_FIRST: /* disable DTE interrupt and write data */
317 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
318 iic_wr(pd, ICDR, data);
320 case OP_TX: /* write data */
321 iic_wr(pd, ICDR, data);
323 case OP_TX_STOP: /* write data and issue a stop afterwards */
324 iic_wr(pd, ICDR, data);
325 iic_wr(pd, ICCR, 0x90);
327 case OP_TX_TO_RX: /* select read mode */
328 iic_wr(pd, ICCR, 0x81);
330 case OP_RX: /* just read data */
331 ret = iic_rd(pd, ICDR);
333 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
335 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
336 iic_wr(pd, ICCR, 0xc0);
338 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
340 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
341 ret = iic_rd(pd, ICDR);
342 iic_wr(pd, ICCR, 0xc0);
346 spin_unlock_irqrestore(&pd->lock, flags);
348 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
352 static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
360 static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
362 if (pd->pos == (pd->msg->len - 1))
368 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
373 *buf = (pd->msg->addr & 0x7f) << 1;
374 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
377 *buf = pd->msg->buf[pd->pos];
381 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
385 if (pd->pos == pd->msg->len)
388 sh_mobile_i2c_get_data(pd, &data);
390 if (sh_mobile_i2c_is_last_byte(pd))
391 i2c_op(pd, OP_TX_STOP, data);
392 else if (sh_mobile_i2c_is_first_byte(pd))
393 i2c_op(pd, OP_TX_FIRST, data);
395 i2c_op(pd, OP_TX, data);
401 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
408 sh_mobile_i2c_get_data(pd, &data);
410 if (sh_mobile_i2c_is_first_byte(pd))
411 i2c_op(pd, OP_TX_FIRST, data);
413 i2c_op(pd, OP_TX, data);
418 i2c_op(pd, OP_TX_TO_RX, 0);
422 real_pos = pd->pos - 2;
424 if (pd->pos == pd->msg->len) {
426 i2c_op(pd, OP_RX_STOP, 0);
429 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
431 data = i2c_op(pd, OP_RX, 0);
434 pd->msg->buf[real_pos] = data;
438 return pd->pos == (pd->msg->len + 2);
441 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
443 struct platform_device *dev = dev_id;
444 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
448 sr = iic_rd(pd, ICSR);
449 pd->sr |= sr; /* remember state */
451 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
452 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
453 pd->pos, pd->msg->len);
455 if (sr & (ICSR_AL | ICSR_TACK)) {
456 /* don't interrupt transaction - continue to issue stop */
457 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
459 } else if (pd->msg->flags & I2C_M_RD)
460 wakeup = sh_mobile_i2c_isr_rx(pd);
462 wakeup = sh_mobile_i2c_isr_tx(pd);
464 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
465 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
472 /* defeat write posting to avoid spurious WAIT interrupts */
478 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
480 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
481 dev_err(pd->dev, "Unsupported zero length i2c read\n");
485 /* Initialize channel registers */
486 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
488 /* Enable channel and configure rx ack */
489 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
492 iic_wr(pd, ICCL, pd->iccl & 0xff);
493 iic_wr(pd, ICCH, pd->icch & 0xff);
499 /* Enable all interrupts to begin with */
500 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
504 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
505 struct i2c_msg *msgs,
508 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
512 int i, k, retry_count;
516 /* Process all messages */
517 for (i = 0; i < num; i++) {
520 err = start_ch(pd, msg);
524 i2c_op(pd, OP_START, 0);
526 /* The interrupt handler takes care of the rest... */
527 k = wait_event_timeout(pd->wait,
528 pd->sr & (ICSR_TACK | SW_DONE),
531 dev_err(pd->dev, "Transfer request timed out\n");
535 val = iic_rd(pd, ICSR);
537 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
539 /* the interrupt handler may wake us up before the
540 * transfer is finished, so poll the hardware
543 if (val & ICSR_BUSY) {
549 dev_err(pd->dev, "Polling timed out\n");
553 /* handle missing acknowledge and arbitration lost */
554 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
567 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
569 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
572 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
573 .functionality = sh_mobile_i2c_func,
574 .master_xfer = sh_mobile_i2c_xfer,
577 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
579 struct resource *res;
583 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
584 for (n = res->start; hook && n <= res->end; n++) {
585 if (request_irq(n, sh_mobile_i2c_isr, 0,
586 dev_name(&dev->dev), dev)) {
587 for (n--; n >= res->start; n--)
597 return k > 0 ? 0 : -ENOENT;
605 res = platform_get_resource(dev, IORESOURCE_IRQ, k);
606 for (n = res->start; n <= res->end; n++)
615 static int sh_mobile_i2c_probe(struct platform_device *dev)
617 struct i2c_sh_mobile_platform_data *pdata = dev->dev.platform_data;
618 struct sh_mobile_i2c_data *pd;
619 struct i2c_adapter *adap;
620 struct resource *res;
624 pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
626 dev_err(&dev->dev, "cannot allocate private data\n");
630 pd->clk = clk_get(&dev->dev, NULL);
631 if (IS_ERR(pd->clk)) {
632 dev_err(&dev->dev, "cannot get clock\n");
633 ret = PTR_ERR(pd->clk);
637 ret = sh_mobile_i2c_hook_irqs(dev, 1);
639 dev_err(&dev->dev, "cannot request IRQ\n");
644 platform_set_drvdata(dev, pd);
646 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
648 dev_err(&dev->dev, "cannot find IO resource\n");
653 size = resource_size(res);
655 pd->reg = ioremap(res->start, size);
656 if (pd->reg == NULL) {
657 dev_err(&dev->dev, "cannot map IO\n");
662 /* Use platform data bus speed or STANDARD_MODE */
663 pd->bus_speed = STANDARD_MODE;
664 if (pdata && pdata->bus_speed)
665 pd->bus_speed = pdata->bus_speed;
666 pd->clks_per_count = 1;
667 if (pdata && pdata->clks_per_count)
668 pd->clks_per_count = pdata->clks_per_count;
670 /* The IIC blocks on SH-Mobile ARM processors
671 * come with two new bits in ICIC.
674 pd->flags |= IIC_FLAG_HAS_ICIC67;
676 sh_mobile_i2c_init(pd);
678 /* Enable Runtime PM for this device.
680 * Also tell the Runtime PM core to ignore children
681 * for this device since it is valid for us to suspend
682 * this I2C master driver even though the slave devices
683 * on the I2C bus may not be suspended.
685 * The state of the I2C hardware bus is unaffected by
686 * the Runtime PM state.
688 pm_suspend_ignore_children(&dev->dev, true);
689 pm_runtime_enable(&dev->dev);
691 /* setup the private data */
693 i2c_set_adapdata(adap, pd);
695 adap->owner = THIS_MODULE;
696 adap->algo = &sh_mobile_i2c_algorithm;
697 adap->dev.parent = &dev->dev;
700 adap->dev.of_node = dev->dev.of_node;
702 strlcpy(adap->name, dev->name, sizeof(adap->name));
704 spin_lock_init(&pd->lock);
705 init_waitqueue_head(&pd->wait);
707 ret = i2c_add_numbered_adapter(adap);
709 dev_err(&dev->dev, "cannot add numbered adapter\n");
714 "I2C adapter %d with bus speed %lu Hz (L/H=%x/%x)\n",
715 adap->nr, pd->bus_speed, pd->iccl, pd->icch);
717 of_i2c_register_devices(adap);
723 sh_mobile_i2c_hook_irqs(dev, 0);
731 static int sh_mobile_i2c_remove(struct platform_device *dev)
733 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
735 i2c_del_adapter(&pd->adap);
737 sh_mobile_i2c_hook_irqs(dev, 0);
739 pm_runtime_disable(&dev->dev);
744 static int sh_mobile_i2c_runtime_nop(struct device *dev)
746 /* Runtime PM callback shared between ->runtime_suspend()
747 * and ->runtime_resume(). Simply returns success.
749 * This driver re-initializes all registers after
750 * pm_runtime_get_sync() anyway so there is no need
751 * to save and restore registers here.
756 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
757 .runtime_suspend = sh_mobile_i2c_runtime_nop,
758 .runtime_resume = sh_mobile_i2c_runtime_nop,
761 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
762 { .compatible = "renesas,rmobile-iic", },
765 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
767 static struct platform_driver sh_mobile_i2c_driver = {
769 .name = "i2c-sh_mobile",
770 .owner = THIS_MODULE,
771 .pm = &sh_mobile_i2c_dev_pm_ops,
772 .of_match_table = sh_mobile_i2c_dt_ids,
774 .probe = sh_mobile_i2c_probe,
775 .remove = sh_mobile_i2c_remove,
778 static int __init sh_mobile_i2c_adap_init(void)
780 return platform_driver_register(&sh_mobile_i2c_driver);
783 static void __exit sh_mobile_i2c_adap_exit(void)
785 platform_driver_unregister(&sh_mobile_i2c_driver);
788 subsys_initcall(sh_mobile_i2c_adap_init);
789 module_exit(sh_mobile_i2c_adap_exit);
791 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
792 MODULE_AUTHOR("Magnus Damm");
793 MODULE_LICENSE("GPL v2");
794 MODULE_ALIAS("platform:i2c-sh_mobile");