2 * I2C bus driver for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/slab.h>
13 #include <linux/platform_device.h>
14 #include <linux/i2c.h>
15 #include <linux/of_i2c.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
20 #define SIRFSOC_I2C_CLK_CTRL 0x00
21 #define SIRFSOC_I2C_STATUS 0x0C
22 #define SIRFSOC_I2C_CTRL 0x10
23 #define SIRFSOC_I2C_IO_CTRL 0x14
24 #define SIRFSOC_I2C_SDA_DELAY 0x18
25 #define SIRFSOC_I2C_CMD_START 0x1C
26 #define SIRFSOC_I2C_CMD_BUF 0x30
27 #define SIRFSOC_I2C_DATA_BUF 0x80
29 #define SIRFSOC_I2C_CMD_BUF_MAX 16
30 #define SIRFSOC_I2C_DATA_BUF_MAX 16
32 #define SIRFSOC_I2C_CMD(x) (SIRFSOC_I2C_CMD_BUF + (x)*0x04)
33 #define SIRFSOC_I2C_DATA_MASK(x) (0xFF<<(((x)&3)*8))
34 #define SIRFSOC_I2C_DATA_SHIFT(x) (((x)&3)*8)
36 #define SIRFSOC_I2C_DIV_MASK (0xFFFF)
38 /* I2C status flags */
39 #define SIRFSOC_I2C_STAT_BUSY BIT(0)
40 #define SIRFSOC_I2C_STAT_TIP BIT(1)
41 #define SIRFSOC_I2C_STAT_NACK BIT(2)
42 #define SIRFSOC_I2C_STAT_TR_INT BIT(4)
43 #define SIRFSOC_I2C_STAT_STOP BIT(6)
44 #define SIRFSOC_I2C_STAT_CMD_DONE BIT(8)
45 #define SIRFSOC_I2C_STAT_ERR BIT(9)
46 #define SIRFSOC_I2C_CMD_INDEX (0x1F<<16)
48 /* I2C control flags */
49 #define SIRFSOC_I2C_RESET BIT(0)
50 #define SIRFSOC_I2C_CORE_EN BIT(1)
51 #define SIRFSOC_I2C_MASTER_MODE BIT(2)
52 #define SIRFSOC_I2C_CMD_DONE_EN BIT(11)
53 #define SIRFSOC_I2C_ERR_INT_EN BIT(12)
55 #define SIRFSOC_I2C_SDA_DELAY_MASK (0xFF)
56 #define SIRFSOC_I2C_SCLF_FILTER (3<<8)
58 #define SIRFSOC_I2C_START_CMD BIT(0)
60 #define SIRFSOC_I2C_CMD_RP(x) ((x)&0x7)
61 #define SIRFSOC_I2C_NACK BIT(3)
62 #define SIRFSOC_I2C_WRITE BIT(4)
63 #define SIRFSOC_I2C_READ BIT(5)
64 #define SIRFSOC_I2C_STOP BIT(6)
65 #define SIRFSOC_I2C_START BIT(7)
67 #define SIRFSOC_I2C_DEFAULT_SPEED 100000
72 u32 cmd_ptr; /* Current position in CMD buffer */
73 u8 *buf; /* Buffer passed by user */
74 u32 msg_len; /* Message length */
75 u32 finished_len; /* number of bytes read/written */
76 u32 read_cmd_len; /* number of read cmd sent */
77 int msg_read; /* 1 indicates a read message */
78 int err_status; /* 1 indicates an error on bus */
80 u32 sda_delay; /* For suspend/resume */
82 int last; /* Last message in transfer, STOP cmd can be sent */
84 struct completion done; /* indicates completion of message transfer */
85 struct i2c_adapter adapter;
88 static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
93 for (i = 0; i < siic->read_cmd_len; i++) {
95 data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
96 siic->buf[siic->finished_len++] =
97 (u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
98 SIRFSOC_I2C_DATA_SHIFT(i));
102 static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
107 if (siic->msg_read) {
108 while (((siic->finished_len + i) < siic->msg_len)
109 && (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
110 regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
111 if (((siic->finished_len + i) ==
112 (siic->msg_len - 1)) && siic->last)
113 regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
115 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
119 siic->read_cmd_len = i;
121 while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
122 && (siic->finished_len < siic->msg_len)) {
123 regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
124 if ((siic->finished_len == (siic->msg_len - 1))
126 regval |= SIRFSOC_I2C_STOP;
128 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
129 writel(siic->buf[siic->finished_len++],
130 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
135 /* Trigger the transfer */
136 writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
139 static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
141 struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id;
142 u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
144 if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
145 /* Error conditions */
146 siic->err_status = 1;
147 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
149 if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
150 dev_err(&siic->adapter.dev, "ACK not received\n");
152 dev_err(&siic->adapter.dev, "I2C error\n");
154 complete(&siic->done);
155 } else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
156 /* CMD buffer execution complete */
158 i2c_sirfsoc_read_data(siic);
159 if (siic->finished_len == siic->msg_len)
160 complete(&siic->done);
161 else /* Fill a new CMD buffer for left data */
162 i2c_sirfsoc_queue_cmd(siic);
164 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
170 static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
174 u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE;
176 /* no data and last message -> add STOP */
177 if (siic->last && (msg->len == 0))
178 regval |= SIRFSOC_I2C_STOP;
180 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
182 addr = msg->addr << 1; /* Generate address */
183 if (msg->flags & I2C_M_RD)
186 writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
189 static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg)
191 u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
192 /* timeout waiting for the xfer to finish or fail */
193 int timeout = msecs_to_jiffies((msg->len + 1) * 50);
196 i2c_sirfsoc_set_address(siic, msg);
198 writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN,
199 siic->base + SIRFSOC_I2C_CTRL);
200 i2c_sirfsoc_queue_cmd(siic);
202 if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
203 siic->err_status = 1;
204 dev_err(&siic->adapter.dev, "Transfer timeout\n");
207 writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN),
208 siic->base + SIRFSOC_I2C_CTRL);
209 writel(0, siic->base + SIRFSOC_I2C_CMD_START);
211 if (siic->err_status) {
212 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
213 siic->base + SIRFSOC_I2C_CTRL);
214 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
223 static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
225 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
228 static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
231 struct sirfsoc_i2c *siic = adap->algo_data;
234 clk_enable(siic->clk);
236 for (i = 0; i < num; i++) {
237 siic->buf = msgs[i].buf;
238 siic->msg_len = msgs[i].len;
239 siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
240 siic->err_status = 0;
242 siic->finished_len = 0;
243 siic->last = (i == (num - 1));
245 ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
247 clk_disable(siic->clk);
252 clk_disable(siic->clk);
256 /* I2C algorithms associated with this master controller driver */
257 static const struct i2c_algorithm i2c_sirfsoc_algo = {
258 .master_xfer = i2c_sirfsoc_xfer,
259 .functionality = i2c_sirfsoc_func,
262 static int i2c_sirfsoc_probe(struct platform_device *pdev)
264 struct sirfsoc_i2c *siic;
265 struct i2c_adapter *adap;
266 struct resource *mem_res;
275 clk = clk_get(&pdev->dev, NULL);
278 dev_err(&pdev->dev, "Clock get failed\n");
282 err = clk_prepare(clk);
284 dev_err(&pdev->dev, "Clock prepare failed\n");
288 err = clk_enable(clk);
290 dev_err(&pdev->dev, "Clock enable failed\n");
294 ctrl_speed = clk_get_rate(clk);
296 siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
298 dev_err(&pdev->dev, "Can't allocate driver data\n");
302 adap = &siic->adapter;
303 adap->class = I2C_CLASS_HWMON;
305 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
306 if (mem_res == NULL) {
307 dev_err(&pdev->dev, "Unable to get MEM resource\n");
312 siic->base = devm_request_and_ioremap(&pdev->dev, mem_res);
313 if (siic->base == NULL) {
314 dev_err(&pdev->dev, "IO remap failed!\n");
319 irq = platform_get_irq(pdev, 0);
324 err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
325 dev_name(&pdev->dev), siic);
329 adap->algo = &i2c_sirfsoc_algo;
330 adap->algo_data = siic;
332 adap->dev.of_node = pdev->dev.of_node;
333 adap->dev.parent = &pdev->dev;
336 strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));
338 platform_set_drvdata(pdev, adap);
339 init_completion(&siic->done);
341 /* Controller Initalisation */
343 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
344 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
346 writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
347 siic->base + SIRFSOC_I2C_CTRL);
351 err = of_property_read_u32(pdev->dev.of_node,
352 "clock-frequency", &bitrate);
354 bitrate = SIRFSOC_I2C_DEFAULT_SPEED;
356 if (bitrate < 100000)
358 (2 * ctrl_speed) / (2 * bitrate * 11);
360 regval = ctrl_speed / (bitrate * 5);
362 writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
364 writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
366 writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);
368 err = i2c_add_numbered_adapter(adap);
370 dev_err(&pdev->dev, "Can't add new i2c adapter\n");
376 of_i2c_register_devices(adap);
378 dev_info(&pdev->dev, " I2C adapter ready to operate\n");
392 static int i2c_sirfsoc_remove(struct platform_device *pdev)
394 struct i2c_adapter *adapter = platform_get_drvdata(pdev);
395 struct sirfsoc_i2c *siic = adapter->algo_data;
397 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
398 i2c_del_adapter(adapter);
399 clk_unprepare(siic->clk);
405 static int i2c_sirfsoc_suspend(struct device *dev)
407 struct platform_device *pdev = to_platform_device(dev);
408 struct i2c_adapter *adapter = platform_get_drvdata(pdev);
409 struct sirfsoc_i2c *siic = adapter->algo_data;
411 clk_enable(siic->clk);
412 siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
413 siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
414 clk_disable(siic->clk);
418 static int i2c_sirfsoc_resume(struct device *dev)
420 struct platform_device *pdev = to_platform_device(dev);
421 struct i2c_adapter *adapter = platform_get_drvdata(pdev);
422 struct sirfsoc_i2c *siic = adapter->algo_data;
424 clk_enable(siic->clk);
425 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
426 writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
427 siic->base + SIRFSOC_I2C_CTRL);
428 writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
429 writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
430 clk_disable(siic->clk);
434 static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
435 .suspend = i2c_sirfsoc_suspend,
436 .resume = i2c_sirfsoc_resume,
440 static const struct of_device_id sirfsoc_i2c_of_match[] = {
441 { .compatible = "sirf,prima2-i2c", },
444 MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);
446 static struct platform_driver i2c_sirfsoc_driver = {
448 .name = "sirfsoc_i2c",
449 .owner = THIS_MODULE,
451 .pm = &i2c_sirfsoc_pm_ops,
453 .of_match_table = sirfsoc_i2c_of_match,
455 .probe = i2c_sirfsoc_probe,
456 .remove = i2c_sirfsoc_remove,
458 module_platform_driver(i2c_sirfsoc_driver);
460 MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
461 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
462 "Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
463 MODULE_LICENSE("GPL v2");