drivers/ide/arm/icside.c

   1 /*
   2  * linux/drivers/ide/arm/icside.c
   3  *
   4  * Copyright (c) 1996-2004 Russell King.
   5  *
   6  * Please note that this platform does not support 32-bit IDE IO.
   7  */
   8
   9 #include <linux/string.h>
  10 #include <linux/module.h>
  11 #include <linux/ioport.h>
  12 #include <linux/slab.h>
  13 #include <linux/blkdev.h>
  14 #include <linux/errno.h>
  15 #include <linux/hdreg.h>
  16 #include <linux/ide.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/device.h>
  19 #include <linux/init.h>
  20 #include <linux/scatterlist.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/dma.h>
  24 #include <asm/ecard.h>
  25
  26 #define ICS_IDENT_OFFSET                0x2280
  27
  28 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  29 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  30 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  31 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  32 #define ICS_ARCIN_V5_IDESTEPPING        6
  33
  34 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  35 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  36 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  37 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  38 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  39 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  40 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  41 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  42 #define ICS_ARCIN_V6_IDESTEPPING        6
  43
  44 struct cardinfo {
  45         unsigned int dataoffset;
  46         unsigned int ctrloffset;
  47         unsigned int stepping;
  48 };
  49
  50 static struct cardinfo icside_cardinfo_v5 = {
  51         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  52         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  53         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  54 };
  55
  56 static struct cardinfo icside_cardinfo_v6_1 = {
  57         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  58         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  59         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  60 };
  61
  62 static struct cardinfo icside_cardinfo_v6_2 = {
  63         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  64         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  65         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  66 };
  67
  68 struct icside_state {
  69         unsigned int channel;
  70         unsigned int enabled;
  71         void __iomem *irq_port;
  72         void __iomem *ioc_base;
  73         unsigned int type;
  74         /* parent device... until the IDE core gets one of its own */
  75         struct device *dev;
  76         ide_hwif_t *hwif[2];
  77 };
  78
  79 #define ICS_TYPE_A3IN   0
  80 #define ICS_TYPE_A3USER 1
  81 #define ICS_TYPE_V6     3
  82 #define ICS_TYPE_V5     15
  83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  84
  85 /* ---------------- Version 5 PCB Support Functions --------------------- */
  86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  87  * Purpose  : enable interrupts from card
  88  */
  89 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  90 {
  91         struct icside_state *state = ec->irq_data;
  92
  93         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  94 }
  95
  96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  97  * Purpose  : disable interrupts from card
  98  */
  99 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 100 {
 101         struct icside_state *state = ec->irq_data;
 102
 103         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 104 }
 105
 106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 107         .irqenable      = icside_irqenable_arcin_v5,
 108         .irqdisable     = icside_irqdisable_arcin_v5,
 109 };
 110
 111
 112 /* ---------------- Version 6 PCB Support Functions --------------------- */
 113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 114  * Purpose  : enable interrupts from card
 115  */
 116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 117 {
 118         struct icside_state *state = ec->irq_data;
 119         void __iomem *base = state->irq_port;
 120
 121         state->enabled = 1;
 122
 123         switch (state->channel) {
 124         case 0:
 125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 126                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 127                 break;
 128         case 1:
 129                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 130                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 131                 break;
 132         }
 133 }
 134
 135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 136  * Purpose  : disable interrupts from card
 137  */
 138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 139 {
 140         struct icside_state *state = ec->irq_data;
 141
 142         state->enabled = 0;
 143
 144         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 145         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 146 }
 147
 148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 149  * Purpose  : detect an active interrupt from card
 150  */
 151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 152 {
 153         struct icside_state *state = ec->irq_data;
 154
 155         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 156                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 157 }
 158
 159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 160         .irqenable      = icside_irqenable_arcin_v6,
 161         .irqdisable     = icside_irqdisable_arcin_v6,
 162         .irqpending     = icside_irqpending_arcin_v6,
 163 };
 164
 165 /*
 166  * Handle routing of interrupts.  This is called before
 167  * we write the command to the drive.
 168  */
 169 static void icside_maskproc(ide_drive_t *drive, int mask)
 170 {
 171         ide_hwif_t *hwif = HWIF(drive);
 172         struct icside_state *state = hwif->hwif_data;
 173         unsigned long flags;
 174
 175         local_irq_save(flags);
 176
 177         state->channel = hwif->channel;
 178
 179         if (state->enabled && !mask) {
 180                 switch (hwif->channel) {
 181                 case 0:
 182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 184                         break;
 185                 case 1:
 186                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 187                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 188                         break;
 189                 }
 190         } else {
 191                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 192                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 193         }
 194
 195         local_irq_restore(flags);
 196 }
 197
 198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 199 /*
 200  * SG-DMA support.
 201  *
 202  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 203  * There is only one DMA controller per card, which means that only
 204  * one drive can be accessed at one time.  NOTE! We do not enforce that
 205  * here, but we rely on the main IDE driver spotting that both
 206  * interfaces use the same IRQ, which should guarantee this.
 207  */
 208
 209 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
 210 {
 211         ide_hwif_t *hwif = drive->hwif;
 212         struct icside_state *state = hwif->hwif_data;
 213         struct scatterlist *sg = hwif->sg_table;
 214
 215         ide_map_sg(drive, rq);
 216
 217         if (rq_data_dir(rq) == READ)
 218                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 219         else
 220                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 221
 222         hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
 223                                     hwif->sg_dma_direction);
 224 }
 225
 226 /*
 227  * Configure the IOMD to give the appropriate timings for the transfer
 228  * mode being requested.  We take the advice of the ATA standards, and
 229  * calculate the cycle time based on the transfer mode, and the EIDE
 230  * MW DMA specs that the drive provides in the IDENTIFY command.
 231  *
 232  * We have the following IOMD DMA modes to choose from:
 233  *
 234  *      Type    Active          Recovery        Cycle
 235  *      A       250 (250)       312 (550)       562 (800)
 236  *      B       187             250             437
 237  *      C       125 (125)       125 (375)       250 (500)
 238  *      D       62              125             187
 239  *
 240  * (figures in brackets are actual measured timings)
 241  *
 242  * However, we also need to take care of the read/write active and
 243  * recovery timings:
 244  *
 245  *                      Read    Write
 246  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 247  *      MW0     215     50      215     480     A
 248  *      MW1     80      50      50      150     C
 249  *      MW2     70      25      25      120     C
 250  */
 251 static int icside_set_speed(ide_drive_t *drive, const u8 xfer_mode)
 252 {
 253         int on = 0, cycle_time = 0, use_dma_info = 0;
 254
 255         switch (xfer_mode) {
 256         case XFER_MW_DMA_2:
 257                 cycle_time = 250;
 258                 use_dma_info = 1;
 259                 break;
 260
 261         case XFER_MW_DMA_1:
 262                 cycle_time = 250;
 263                 use_dma_info = 1;
 264                 break;
 265
 266         case XFER_MW_DMA_0:
 267                 cycle_time = 480;
 268                 break;
 269
 270         case XFER_SW_DMA_2:
 271         case XFER_SW_DMA_1:
 272         case XFER_SW_DMA_0:
 273                 cycle_time = 480;
 274                 break;
 275         }
 276
 277         /*
 278          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 279          * take care to note the values in the ID...
 280          */
 281         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 282                 cycle_time = drive->id->eide_dma_time;
 283
 284         drive->drive_data = cycle_time;
 285
 286         if (cycle_time && ide_config_drive_speed(drive, xfer_mode) == 0)
 287                 on = 1;
 288         else
 289                 drive->drive_data = 480;
 290
 291         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 292                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 293
 294         drive->current_speed = xfer_mode;
 295
 296         return on;
 297 }
 298
 299 static void icside_dma_host_off(ide_drive_t *drive)
 300 {
 301 }
 302
 303 static void icside_dma_off_quietly(ide_drive_t *drive)
 304 {
 305         drive->using_dma = 0;
 306 }
 307
 308 static void icside_dma_host_on(ide_drive_t *drive)
 309 {
 310 }
 311
 312 static int icside_dma_on(ide_drive_t *drive)
 313 {
 314         drive->using_dma = 1;
 315
 316         return 0;
 317 }
 318
 319 static int icside_dma_check(ide_drive_t *drive)
 320 {
 321         struct hd_driveid *id = drive->id;
 322         ide_hwif_t *hwif = HWIF(drive);
 323         int xfer_mode = XFER_PIO_2;
 324         int on;
 325
 326         if (!(id->capability & 1) || !hwif->autodma)
 327                 goto out;
 328
 329         /*
 330          * Consult the list of known "bad" drives
 331          */
 332         if (__ide_dma_bad_drive(drive))
 333                 goto out;
 334
 335         /*
 336          * Enable DMA on any drive that has multiword DMA
 337          */
 338         if (id->field_valid & 2) {
 339                 xfer_mode = ide_max_dma_mode(drive);
 340                 goto out;
 341         }
 342
 343         /*
 344          * Consult the list of known "good" drives
 345          */
 346         if (__ide_dma_good_drive(drive)) {
 347                 if (id->eide_dma_time > 150)
 348                         goto out;
 349                 xfer_mode = XFER_MW_DMA_1;
 350         }
 351
 352 out:
 353         on = icside_set_speed(drive, xfer_mode);
 354
 355         return on ? 0 : -1;
 356 }
 357
 358 static int icside_dma_end(ide_drive_t *drive)
 359 {
 360         ide_hwif_t *hwif = HWIF(drive);
 361         struct icside_state *state = hwif->hwif_data;
 362
 363         drive->waiting_for_dma = 0;
 364
 365         disable_dma(hwif->hw.dma);
 366
 367         /* Teardown mappings after DMA has completed. */
 368         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
 369                      hwif->sg_dma_direction);
 370
 371         return get_dma_residue(hwif->hw.dma) != 0;
 372 }
 373
 374 static void icside_dma_start(ide_drive_t *drive)
 375 {
 376         ide_hwif_t *hwif = HWIF(drive);
 377
 378         /* We can not enable DMA on both channels simultaneously. */
 379         BUG_ON(dma_channel_active(hwif->hw.dma));
 380         enable_dma(hwif->hw.dma);
 381 }
 382
 383 static int icside_dma_setup(ide_drive_t *drive)
 384 {
 385         ide_hwif_t *hwif = HWIF(drive);
 386         struct request *rq = hwif->hwgroup->rq;
 387         unsigned int dma_mode;
 388
 389         if (rq_data_dir(rq))
 390                 dma_mode = DMA_MODE_WRITE;
 391         else
 392                 dma_mode = DMA_MODE_READ;
 393
 394         /*
 395          * We can not enable DMA on both channels.
 396          */
 397         BUG_ON(dma_channel_active(hwif->hw.dma));
 398
 399         icside_build_sglist(drive, rq);
 400
 401         /*
 402          * Ensure that we have the right interrupt routed.
 403          */
 404         icside_maskproc(drive, 0);
 405
 406         /*
 407          * Route the DMA signals to the correct interface.
 408          */
 409         writeb(hwif->select_data, hwif->config_data);
 410
 411         /*
 412          * Select the correct timing for this drive.
 413          */
 414         set_dma_speed(hwif->hw.dma, drive->drive_data);
 415
 416         /*
 417          * Tell the DMA engine about the SG table and
 418          * data direction.
 419          */
 420         set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
 421         set_dma_mode(hwif->hw.dma, dma_mode);
 422
 423         drive->waiting_for_dma = 1;
 424
 425         return 0;
 426 }
 427
 428 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
 429 {
 430         /* issue cmd to drive */
 431         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
 432 }
 433
 434 static int icside_dma_test_irq(ide_drive_t *drive)
 435 {
 436         ide_hwif_t *hwif = HWIF(drive);
 437         struct icside_state *state = hwif->hwif_data;
 438
 439         return readb(state->irq_port +
 440                      (hwif->channel ?
 441                         ICS_ARCIN_V6_INTRSTAT_2 :
 442                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 443 }
 444
 445 static void icside_dma_timeout(ide_drive_t *drive)
 446 {
 447         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 448
 449         if (icside_dma_test_irq(drive))
 450                 return;
 451
 452         ide_dump_status(drive, "DMA timeout", HWIF(drive)->INB(IDE_STATUS_REG));
 453
 454         icside_dma_end(drive);
 455 }
 456
 457 static void icside_dma_lost_irq(ide_drive_t *drive)
 458 {
 459         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 460 }
 461
 462 static void icside_dma_init(ide_hwif_t *hwif)
 463 {
 464         printk("    %s: SG-DMA", hwif->name);
 465
 466         hwif->atapi_dma         = 1;
 467         hwif->mwdma_mask        = 7; /* MW0..2 */
 468         hwif->swdma_mask        = 7; /* SW0..2 */
 469
 470         hwif->dmatable_cpu      = NULL;
 471         hwif->dmatable_dma      = 0;
 472         hwif->speedproc         = icside_set_speed;
 473         hwif->autodma           = 1;
 474
 475         hwif->ide_dma_check     = icside_dma_check;
 476         hwif->dma_host_off      = icside_dma_host_off;
 477         hwif->dma_off_quietly   = icside_dma_off_quietly;
 478         hwif->dma_host_on       = icside_dma_host_on;
 479         hwif->ide_dma_on        = icside_dma_on;
 480         hwif->dma_setup         = icside_dma_setup;
 481         hwif->dma_exec_cmd      = icside_dma_exec_cmd;
 482         hwif->dma_start         = icside_dma_start;
 483         hwif->ide_dma_end       = icside_dma_end;
 484         hwif->ide_dma_test_irq  = icside_dma_test_irq;
 485         hwif->dma_timeout       = icside_dma_timeout;
 486         hwif->dma_lost_irq      = icside_dma_lost_irq;
 487
 488         hwif->drives[0].autodma = hwif->autodma;
 489         hwif->drives[1].autodma = hwif->autodma;
 490
 491         printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
 492 }
 493 #else
 494 #define icside_dma_init(hwif)   (0)
 495 #endif
 496
 497 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
 498 {
 499         ide_hwif_t *hwif;
 500         int index;
 501
 502         for (index = 0; index < MAX_HWIFS; ++index) {
 503                 hwif = &ide_hwifs[index];
 504                 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
 505                         goto found;
 506         }
 507
 508         for (index = 0; index < MAX_HWIFS; ++index) {
 509                 hwif = &ide_hwifs[index];
 510                 if (!hwif->io_ports[IDE_DATA_OFFSET])
 511                         goto found;
 512         }
 513
 514         hwif = NULL;
 515 found:
 516         return hwif;
 517 }
 518
 519 static ide_hwif_t *
 520 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
 521 {
 522         unsigned long port = (unsigned long)base + info->dataoffset;
 523         ide_hwif_t *hwif;
 524
 525         hwif = icside_find_hwif(port);
 526         if (hwif) {
 527                 int i;
 528
 529                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
 530
 531                 /*
 532                  * Ensure we're using MMIO
 533                  */
 534                 default_hwif_mmiops(hwif);
 535                 hwif->mmio = 1;
 536
 537                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 538                         hwif->hw.io_ports[i] = port;
 539                         hwif->io_ports[i] = port;
 540                         port += 1 << info->stepping;
 541                 }
 542                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 543                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 544                 hwif->hw.irq  = ec->irq;
 545                 hwif->irq     = ec->irq;
 546                 hwif->noprobe = 0;
 547                 hwif->chipset = ide_acorn;
 548                 hwif->gendev.parent = &ec->dev;
 549         }
 550
 551         return hwif;
 552 }
 553
 554 static int __init
 555 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 556 {
 557         ide_hwif_t *hwif;
 558         void __iomem *base;
 559
 560         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
 561         if (!base)
 562                 return -ENOMEM;
 563
 564         state->irq_port = base;
 565
 566         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 567         ec->irqmask  = 1;
 568
 569         ecard_setirq(ec, &icside_ops_arcin_v5, state);
 570
 571         /*
 572          * Be on the safe side - disable interrupts
 573          */
 574         icside_irqdisable_arcin_v5(ec, 0);
 575
 576         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
 577         if (!hwif)
 578                 return -ENODEV;
 579
 580         state->hwif[0] = hwif;
 581
 582         probe_hwif_init(hwif);
 583
 584         ide_proc_register_port(hwif);
 585
 586         return 0;
 587 }
 588
 589 static int __init
 590 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 591 {
 592         ide_hwif_t *hwif, *mate;
 593         void __iomem *ioc_base, *easi_base;
 594         unsigned int sel = 0;
 595         int ret;
 596
 597         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 598         if (!ioc_base) {
 599                 ret = -ENOMEM;
 600                 goto out;
 601         }
 602
 603         easi_base = ioc_base;
 604
 605         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 606                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
 607                 if (!easi_base) {
 608                         ret = -ENOMEM;
 609                         goto out;
 610                 }
 611
 612                 /*
 613                  * Enable access to the EASI region.
 614                  */
 615                 sel = 1 << 5;
 616         }
 617
 618         writeb(sel, ioc_base);
 619
 620         ecard_setirq(ec, &icside_ops_arcin_v6, state);
 621
 622         state->irq_port   = easi_base;
 623         state->ioc_base   = ioc_base;
 624
 625         /*
 626          * Be on the safe side - disable interrupts
 627          */
 628         icside_irqdisable_arcin_v6(ec, 0);
 629
 630         /*
 631          * Find and register the interfaces.
 632          */
 633         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
 634         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
 635
 636         if (!hwif || !mate) {
 637                 ret = -ENODEV;
 638                 goto out;
 639         }
 640
 641         state->hwif[0]    = hwif;
 642         state->hwif[1]    = mate;
 643
 644         hwif->maskproc    = icside_maskproc;
 645         hwif->channel     = 0;
 646         hwif->hwif_data   = state;
 647         hwif->mate        = mate;
 648         hwif->serialized  = 1;
 649         hwif->config_data = (unsigned long)ioc_base;
 650         hwif->select_data = sel;
 651         hwif->hw.dma      = ec->dma;
 652
 653         mate->maskproc    = icside_maskproc;
 654         mate->channel     = 1;
 655         mate->hwif_data   = state;
 656         mate->mate        = hwif;
 657         mate->serialized  = 1;
 658         mate->config_data = (unsigned long)ioc_base;
 659         mate->select_data = sel | 1;
 660         mate->hw.dma      = ec->dma;
 661
 662         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 663                 icside_dma_init(hwif);
 664                 icside_dma_init(mate);
 665         }
 666
 667         probe_hwif_init(hwif);
 668         probe_hwif_init(mate);
 669
 670         ide_proc_register_port(hwif);
 671         ide_proc_register_port(mate);
 672
 673         return 0;
 674
 675  out:
 676         return ret;
 677 }
 678
 679 static int __devinit
 680 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 681 {
 682         struct icside_state *state;
 683         void __iomem *idmem;
 684         int ret;
 685
 686         ret = ecard_request_resources(ec);
 687         if (ret)
 688                 goto out;
 689
 690         state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
 691         if (!state) {
 692                 ret = -ENOMEM;
 693                 goto release;
 694         }
 695
 696         state->type     = ICS_TYPE_NOTYPE;
 697         state->dev      = &ec->dev;
 698
 699         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 700         if (idmem) {
 701                 unsigned int type;
 702
 703                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 704                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 705                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 706                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 707                 ecardm_iounmap(ec, idmem);
 708
 709                 state->type = type;
 710         }
 711
 712         switch (state->type) {
 713         case ICS_TYPE_A3IN:
 714                 dev_warn(&ec->dev, "A3IN unsupported\n");
 715                 ret = -ENODEV;
 716                 break;
 717
 718         case ICS_TYPE_A3USER:
 719                 dev_warn(&ec->dev, "A3USER unsupported\n");
 720                 ret = -ENODEV;
 721                 break;
 722
 723         case ICS_TYPE_V5:
 724                 ret = icside_register_v5(state, ec);
 725                 break;
 726
 727         case ICS_TYPE_V6:
 728                 ret = icside_register_v6(state, ec);
 729                 break;
 730
 731         default:
 732                 dev_warn(&ec->dev, "unknown interface type\n");
 733                 ret = -ENODEV;
 734                 break;
 735         }
 736
 737         if (ret == 0) {
 738                 ecard_set_drvdata(ec, state);
 739                 goto out;
 740         }
 741
 742         kfree(state);
 743  release:
 744         ecard_release_resources(ec);
 745  out:
 746         return ret;
 747 }
 748
 749 static void __devexit icside_remove(struct expansion_card *ec)
 750 {
 751         struct icside_state *state = ecard_get_drvdata(ec);
 752
 753         switch (state->type) {
 754         case ICS_TYPE_V5:
 755                 /* FIXME: tell IDE to stop using the interface */
 756
 757                 /* Disable interrupts */
 758                 icside_irqdisable_arcin_v5(ec, 0);
 759                 break;
 760
 761         case ICS_TYPE_V6:
 762                 /* FIXME: tell IDE to stop using the interface */
 763                 if (ec->dma != NO_DMA)
 764                         free_dma(ec->dma);
 765
 766                 /* Disable interrupts */
 767                 icside_irqdisable_arcin_v6(ec, 0);
 768
 769                 /* Reset the ROM pointer/EASI selection */
 770                 writeb(0, state->ioc_base);
 771                 break;
 772         }
 773
 774         ecard_set_drvdata(ec, NULL);
 775
 776         kfree(state);
 777         ecard_release_resources(ec);
 778 }
 779
 780 static void icside_shutdown(struct expansion_card *ec)
 781 {
 782         struct icside_state *state = ecard_get_drvdata(ec);
 783         unsigned long flags;
 784
 785         /*
 786          * Disable interrupts from this card.  We need to do
 787          * this before disabling EASI since we may be accessing
 788          * this register via that region.
 789          */
 790         local_irq_save(flags);
 791         ec->ops->irqdisable(ec, 0);
 792         local_irq_restore(flags);
 793
 794         /*
 795          * Reset the ROM pointer so that we can read the ROM
 796          * after a soft reboot.  This also disables access to
 797          * the IDE taskfile via the EASI region.
 798          */
 799         if (state->ioc_base)
 800                 writeb(0, state->ioc_base);
 801 }
 802
 803 static const struct ecard_id icside_ids[] = {
 804         { MANU_ICS,  PROD_ICS_IDE  },
 805         { MANU_ICS2, PROD_ICS2_IDE },
 806         { 0xffff, 0xffff }
 807 };
 808
 809 static struct ecard_driver icside_driver = {
 810         .probe          = icside_probe,
 811         .remove         = __devexit_p(icside_remove),
 812         .shutdown       = icside_shutdown,
 813         .id_table       = icside_ids,
 814         .drv = {
 815                 .name   = "icside",
 816         },
 817 };
 818
 819 static int __init icside_init(void)
 820 {
 821         return ecard_register_driver(&icside_driver);
 822 }
 823
 824 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 825 MODULE_LICENSE("GPL");
 826 MODULE_DESCRIPTION("ICS IDE driver");
 827
 828 module_init(icside_init);