2 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
3 * Due to massive hardware bugs, UltraDMA is only supported
4 * on the 646U2 and not on the 646U.
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
10 * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
13 #include <linux/module.h>
14 #include <linux/types.h>
15 #include <linux/pci.h>
16 #include <linux/ide.h>
17 #include <linux/init.h>
21 #define DRV_NAME "cmd64x"
26 #define cmdprintk(x...) printk(x)
28 #define cmdprintk(x...)
32 * CMD64x specific registers definition.
35 #define CFR_INTR_CH0 0x04
43 #define ARTTIM23_DIS_RA2 0x04
44 #define ARTTIM23_DIS_RA3 0x08
45 #define ARTTIM23_INTR_CH1 0x10
52 #define MRDMODE_INTR_CH0 0x04
53 #define MRDMODE_INTR_CH1 0x08
54 #define UDIDETCR0 0x73
58 #define UDIDETCR1 0x7B
61 static u8 quantize_timing(int timing, int quant)
63 return (timing + quant - 1) / quant;
67 * This routine calculates active/recovery counts and then writes them into
68 * the chipset registers.
70 static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
72 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
73 int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
74 u8 cycle_count, active_count, recovery_count, drwtim;
75 static const u8 recovery_values[] =
76 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
77 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
79 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
80 cycle_time, active_time);
82 cycle_count = quantize_timing( cycle_time, clock_time);
83 active_count = quantize_timing(active_time, clock_time);
84 recovery_count = cycle_count - active_count;
87 * In case we've got too long recovery phase, try to lengthen
90 if (recovery_count > 16) {
91 active_count += recovery_count - 16;
94 if (active_count > 16) /* shouldn't actually happen... */
97 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
98 cycle_count, active_count, recovery_count);
101 * Convert values to internal chipset representation
103 recovery_count = recovery_values[recovery_count];
104 active_count &= 0x0f;
106 /* Program the active/recovery counts into the DRWTIM register */
107 drwtim = (active_count << 4) | recovery_count;
108 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
109 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
113 * This routine writes into the chipset registers
114 * PIO setup/active/recovery timings.
116 static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
118 ide_hwif_t *hwif = drive->hwif;
119 struct pci_dev *dev = to_pci_dev(hwif->dev);
120 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
121 unsigned int cycle_time;
122 u8 setup_count, arttim = 0;
124 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
125 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
127 cycle_time = ide_pio_cycle_time(drive, pio);
129 program_cycle_times(drive, cycle_time, t->active);
131 setup_count = quantize_timing(t->setup,
132 1000 / (ide_pci_clk ? ide_pci_clk : 33));
135 * The primary channel has individual address setup timing registers
136 * for each drive and the hardware selects the slowest timing itself.
137 * The secondary channel has one common register and we have to select
138 * the slowest address setup timing ourselves.
141 ide_drive_t *pair = ide_get_pair_dev(drive);
143 drive->drive_data = setup_count;
146 setup_count = max_t(u8, setup_count, pair->drive_data);
149 if (setup_count > 5) /* shouldn't actually happen... */
151 cmdprintk("Final address setup count: %d\n", setup_count);
154 * Program the address setup clocks into the ARTTIM registers.
155 * Avoid clearing the secondary channel's interrupt bit.
157 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
159 arttim &= ~ARTTIM23_INTR_CH1;
161 arttim |= setup_values[setup_count];
162 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
163 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
167 * Attempts to set drive's PIO mode.
168 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
171 static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
174 * Filter out the prefetch control values
175 * to prevent PIO5 from being programmed
177 if (pio == 8 || pio == 9)
180 cmd64x_tune_pio(drive, pio);
183 static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
185 ide_hwif_t *hwif = drive->hwif;
186 struct pci_dev *dev = to_pci_dev(hwif->dev);
187 u8 unit = drive->dn & 0x01;
188 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
190 if (speed >= XFER_SW_DMA_0) {
191 (void) pci_read_config_byte(dev, pciU, ®U);
192 regU &= ~(unit ? 0xCA : 0x35);
197 regU |= unit ? 0x0A : 0x05;
200 regU |= unit ? 0x4A : 0x15;
203 regU |= unit ? 0x8A : 0x25;
206 regU |= unit ? 0x42 : 0x11;
209 regU |= unit ? 0x82 : 0x21;
212 regU |= unit ? 0xC2 : 0x31;
215 program_cycle_times(drive, 120, 70);
218 program_cycle_times(drive, 150, 80);
221 program_cycle_times(drive, 480, 215);
225 if (speed >= XFER_SW_DMA_0)
226 (void) pci_write_config_byte(dev, pciU, regU);
229 static void cmd648_clear_irq(ide_drive_t *drive)
231 ide_hwif_t *hwif = drive->hwif;
232 struct pci_dev *dev = to_pci_dev(hwif->dev);
233 unsigned long base = pci_resource_start(dev, 4);
234 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
236 u8 mrdmode = inb(base + 1);
238 /* clear the interrupt bit */
239 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
243 static void cmd64x_clear_irq(ide_drive_t *drive)
245 ide_hwif_t *hwif = drive->hwif;
246 struct pci_dev *dev = to_pci_dev(hwif->dev);
247 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
248 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
252 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
253 /* clear the interrupt bit */
254 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
257 static int cmd648_dma_test_irq(ide_drive_t *drive)
259 ide_hwif_t *hwif = drive->hwif;
260 unsigned long base = hwif->dma_base - (hwif->channel * 8);
261 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
263 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
264 u8 mrdmode = inb(base + 1);
267 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
268 drive->name, dma_stat, mrdmode, irq_mask);
270 if (!(mrdmode & irq_mask))
273 /* return 1 if INTR asserted */
280 static int cmd64x_dma_test_irq(ide_drive_t *drive)
282 ide_hwif_t *hwif = drive->hwif;
283 struct pci_dev *dev = to_pci_dev(hwif->dev);
284 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
285 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
287 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
290 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
293 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
294 drive->name, dma_stat, irq_stat, irq_mask);
296 if (!(irq_stat & irq_mask))
299 /* return 1 if INTR asserted */
307 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
308 * event order for DMA transfers.
311 static int cmd646_1_dma_end(ide_drive_t *drive)
313 ide_hwif_t *hwif = drive->hwif;
314 u8 dma_stat = 0, dma_cmd = 0;
317 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
318 /* read DMA command state */
319 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
321 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
322 /* clear the INTR & ERROR bits */
323 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
324 /* verify good DMA status */
325 return (dma_stat & 7) != 4;
328 static int init_chipset_cmd64x(struct pci_dev *dev)
332 /* Set a good latency timer and cache line size value. */
333 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
334 /* FIXME: pci_set_master() to ensure a good latency timer value */
337 * Enable interrupts, select MEMORY READ LINE for reads.
339 * NOTE: although not mentioned in the PCI0646U specs,
340 * bits 0-1 are write only and won't be read back as
341 * set or not -- PCI0646U2 specs clarify this point.
343 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
345 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
350 static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
352 struct pci_dev *dev = to_pci_dev(hwif->dev);
353 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
355 switch (dev->device) {
356 case PCI_DEVICE_ID_CMD_648:
357 case PCI_DEVICE_ID_CMD_649:
358 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
359 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
361 return ATA_CBL_PATA40;
365 static const struct ide_port_ops cmd64x_port_ops = {
366 .set_pio_mode = cmd64x_set_pio_mode,
367 .set_dma_mode = cmd64x_set_dma_mode,
368 .clear_irq = cmd64x_clear_irq,
369 .cable_detect = cmd64x_cable_detect,
372 static const struct ide_port_ops cmd648_port_ops = {
373 .set_pio_mode = cmd64x_set_pio_mode,
374 .set_dma_mode = cmd64x_set_dma_mode,
375 .clear_irq = cmd648_clear_irq,
376 .cable_detect = cmd64x_cable_detect,
379 static const struct ide_dma_ops cmd64x_dma_ops = {
380 .dma_host_set = ide_dma_host_set,
381 .dma_setup = ide_dma_setup,
382 .dma_start = ide_dma_start,
383 .dma_end = ide_dma_end,
384 .dma_test_irq = cmd64x_dma_test_irq,
385 .dma_lost_irq = ide_dma_lost_irq,
386 .dma_timer_expiry = ide_dma_sff_timer_expiry,
387 .dma_sff_read_status = ide_dma_sff_read_status,
390 static const struct ide_dma_ops cmd646_rev1_dma_ops = {
391 .dma_host_set = ide_dma_host_set,
392 .dma_setup = ide_dma_setup,
393 .dma_start = ide_dma_start,
394 .dma_end = cmd646_1_dma_end,
395 .dma_test_irq = ide_dma_test_irq,
396 .dma_lost_irq = ide_dma_lost_irq,
397 .dma_timer_expiry = ide_dma_sff_timer_expiry,
398 .dma_sff_read_status = ide_dma_sff_read_status,
401 static const struct ide_dma_ops cmd648_dma_ops = {
402 .dma_host_set = ide_dma_host_set,
403 .dma_setup = ide_dma_setup,
404 .dma_start = ide_dma_start,
405 .dma_end = ide_dma_end,
406 .dma_test_irq = cmd648_dma_test_irq,
407 .dma_lost_irq = ide_dma_lost_irq,
408 .dma_timer_expiry = ide_dma_sff_timer_expiry,
409 .dma_sff_read_status = ide_dma_sff_read_status,
412 static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
415 .init_chipset = init_chipset_cmd64x,
416 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
417 .port_ops = &cmd64x_port_ops,
418 .dma_ops = &cmd64x_dma_ops,
419 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
420 IDE_HFLAG_ABUSE_PREFETCH,
421 .pio_mask = ATA_PIO5,
422 .mwdma_mask = ATA_MWDMA2,
423 .udma_mask = 0x00, /* no udma */
427 .init_chipset = init_chipset_cmd64x,
428 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
429 .port_ops = &cmd648_port_ops,
430 .dma_ops = &cmd648_dma_ops,
431 .host_flags = IDE_HFLAG_SERIALIZE |
432 IDE_HFLAG_ABUSE_PREFETCH,
433 .pio_mask = ATA_PIO5,
434 .mwdma_mask = ATA_MWDMA2,
435 .udma_mask = ATA_UDMA2,
439 .init_chipset = init_chipset_cmd64x,
440 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
441 .port_ops = &cmd648_port_ops,
442 .dma_ops = &cmd648_dma_ops,
443 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
444 .pio_mask = ATA_PIO5,
445 .mwdma_mask = ATA_MWDMA2,
446 .udma_mask = ATA_UDMA4,
450 .init_chipset = init_chipset_cmd64x,
451 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
452 .port_ops = &cmd648_port_ops,
453 .dma_ops = &cmd648_dma_ops,
454 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
455 .pio_mask = ATA_PIO5,
456 .mwdma_mask = ATA_MWDMA2,
457 .udma_mask = ATA_UDMA5,
461 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
463 struct ide_port_info d;
464 u8 idx = id->driver_data;
466 d = cmd64x_chipsets[idx];
470 * UltraDMA only supported on PCI646U and PCI646U2, which
471 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
472 * Actually, although the CMD tech support people won't
473 * tell me the details, the 0x03 revision cannot support
474 * UDMA correctly without hardware modifications, and even
475 * then it only works with Quantum disks due to some
476 * hold time assumptions in the 646U part which are fixed
479 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
481 if (dev->revision < 5) {
484 * The original PCI0646 didn't have the primary
485 * channel enable bit, it appeared starting with
486 * PCI0646U (i.e. revision ID 3).
488 if (dev->revision < 3) {
489 d.enablebits[0].reg = 0;
490 d.port_ops = &cmd64x_port_ops;
491 if (dev->revision == 1)
492 d.dma_ops = &cmd646_rev1_dma_ops;
494 d.dma_ops = &cmd64x_dma_ops;
499 return ide_pci_init_one(dev, &d, NULL);
502 static const struct pci_device_id cmd64x_pci_tbl[] = {
503 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
504 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
505 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
506 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
509 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
511 static struct pci_driver cmd64x_pci_driver = {
512 .name = "CMD64x_IDE",
513 .id_table = cmd64x_pci_tbl,
514 .probe = cmd64x_init_one,
515 .remove = ide_pci_remove,
516 .suspend = ide_pci_suspend,
517 .resume = ide_pci_resume,
520 static int __init cmd64x_ide_init(void)
522 return ide_pci_register_driver(&cmd64x_pci_driver);
525 static void __exit cmd64x_ide_exit(void)
527 pci_unregister_driver(&cmd64x_pci_driver);
530 module_init(cmd64x_ide_init);
531 module_exit(cmd64x_ide_exit);
533 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
534 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
535 MODULE_LICENSE("GPL");