drivers/ide/icside.c

   1 /*
   2  * Copyright (c) 1996-2004 Russell King.
   3  *
   4  * Please note that this platform does not support 32-bit IDE IO.
   5  */
   6
   7 #include <linux/string.h>
   8 #include <linux/module.h>
   9 #include <linux/ioport.h>
  10 #include <linux/slab.h>
  11 #include <linux/blkdev.h>
  12 #include <linux/errno.h>
  13 #include <linux/ide.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/device.h>
  16 #include <linux/init.h>
  17 #include <linux/scatterlist.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/dma.h>
  21 #include <asm/ecard.h>
  22
  23 #define DRV_NAME "icside"
  24
  25 #define ICS_IDENT_OFFSET                0x2280
  26
  27 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  28 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  29 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  30 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  31 #define ICS_ARCIN_V5_IDESTEPPING        6
  32
  33 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  34 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  35 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  36 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  37 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  38 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  39 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  40 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  41 #define ICS_ARCIN_V6_IDESTEPPING        6
  42
  43 struct cardinfo {
  44         unsigned int dataoffset;
  45         unsigned int ctrloffset;
  46         unsigned int stepping;
  47 };
  48
  49 static struct cardinfo icside_cardinfo_v5 = {
  50         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  51         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  52         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  53 };
  54
  55 static struct cardinfo icside_cardinfo_v6_1 = {
  56         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  57         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  58         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  59 };
  60
  61 static struct cardinfo icside_cardinfo_v6_2 = {
  62         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  63         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  64         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  65 };
  66
  67 struct icside_state {
  68         void __iomem *irq_port;
  69         void __iomem *ioc_base;
  70         unsigned int sel;
  71         unsigned int type;
  72         struct ide_host *host;
  73 };
  74
  75 #define ICS_TYPE_A3IN   0
  76 #define ICS_TYPE_A3USER 1
  77 #define ICS_TYPE_V6     3
  78 #define ICS_TYPE_V5     15
  79 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  80
  81 /* ---------------- Version 5 PCB Support Functions --------------------- */
  82 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  83  * Purpose  : enable interrupts from card
  84  */
  85 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  86 {
  87         struct icside_state *state = ec->irq_data;
  88
  89         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  90 }
  91
  92 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  93  * Purpose  : disable interrupts from card
  94  */
  95 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  96 {
  97         struct icside_state *state = ec->irq_data;
  98
  99         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 100 }
 101
 102 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 103         .irqenable      = icside_irqenable_arcin_v5,
 104         .irqdisable     = icside_irqdisable_arcin_v5,
 105 };
 106
 107
 108 /* ---------------- Version 6 PCB Support Functions --------------------- */
 109 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 110  * Purpose  : enable interrupts from card
 111  */
 112 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 113 {
 114         struct icside_state *state = ec->irq_data;
 115         void __iomem *base = state->irq_port;
 116
 117         writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 118         readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 119
 120         writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 121         readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 122 }
 123
 124 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 125  * Purpose  : disable interrupts from card
 126  */
 127 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 128 {
 129         struct icside_state *state = ec->irq_data;
 130
 131         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 132         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 133 }
 134
 135 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 136  * Purpose  : detect an active interrupt from card
 137  */
 138 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 139 {
 140         struct icside_state *state = ec->irq_data;
 141
 142         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 143                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 144 }
 145
 146 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 147         .irqenable      = icside_irqenable_arcin_v6,
 148         .irqdisable     = icside_irqdisable_arcin_v6,
 149         .irqpending     = icside_irqpending_arcin_v6,
 150 };
 151
 152 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 153 /*
 154  * SG-DMA support.
 155  *
 156  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 157  * There is only one DMA controller per card, which means that only
 158  * one drive can be accessed at one time.  NOTE! We do not enforce that
 159  * here, but we rely on the main IDE driver spotting that both
 160  * interfaces use the same IRQ, which should guarantee this.
 161  */
 162
 163 /*
 164  * Configure the IOMD to give the appropriate timings for the transfer
 165  * mode being requested.  We take the advice of the ATA standards, and
 166  * calculate the cycle time based on the transfer mode, and the EIDE
 167  * MW DMA specs that the drive provides in the IDENTIFY command.
 168  *
 169  * We have the following IOMD DMA modes to choose from:
 170  *
 171  *      Type    Active          Recovery        Cycle
 172  *      A       250 (250)       312 (550)       562 (800)
 173  *      B       187             250             437
 174  *      C       125 (125)       125 (375)       250 (500)
 175  *      D       62              125             187
 176  *
 177  * (figures in brackets are actual measured timings)
 178  *
 179  * However, we also need to take care of the read/write active and
 180  * recovery timings:
 181  *
 182  *                      Read    Write
 183  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 184  *      MW0     215     50      215     480     A
 185  *      MW1     80      50      50      150     C
 186  *      MW2     70      25      25      120     C
 187  */
 188 static void icside_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 189 {
 190         unsigned long cycle_time;
 191         int use_dma_info = 0;
 192         const u8 xfer_mode = drive->dma_mode;
 193
 194         switch (xfer_mode) {
 195         case XFER_MW_DMA_2:
 196                 cycle_time = 250;
 197                 use_dma_info = 1;
 198                 break;
 199
 200         case XFER_MW_DMA_1:
 201                 cycle_time = 250;
 202                 use_dma_info = 1;
 203                 break;
 204
 205         case XFER_MW_DMA_0:
 206                 cycle_time = 480;
 207                 break;
 208
 209         case XFER_SW_DMA_2:
 210         case XFER_SW_DMA_1:
 211         case XFER_SW_DMA_0:
 212                 cycle_time = 480;
 213                 break;
 214         }
 215
 216         /*
 217          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 218          * take care to note the values in the ID...
 219          */
 220         if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time)
 221                 cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME];
 222
 223         ide_set_drivedata(drive, (void *)cycle_time);
 224
 225         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 226                 ide_xfer_verbose(xfer_mode),
 227                 2000 / (unsigned long)ide_get_drivedata(drive));
 228 }
 229
 230 static const struct ide_port_ops icside_v6_port_ops = {
 231         .set_dma_mode           = icside_set_dma_mode,
 232 };
 233
 234 static void icside_dma_host_set(ide_drive_t *drive, int on)
 235 {
 236 }
 237
 238 static int icside_dma_end(ide_drive_t *drive)
 239 {
 240         ide_hwif_t *hwif = drive->hwif;
 241         struct expansion_card *ec = ECARD_DEV(hwif->dev);
 242
 243         disable_dma(ec->dma);
 244
 245         return get_dma_residue(ec->dma) != 0;
 246 }
 247
 248 static void icside_dma_start(ide_drive_t *drive)
 249 {
 250         ide_hwif_t *hwif = drive->hwif;
 251         struct expansion_card *ec = ECARD_DEV(hwif->dev);
 252
 253         /* We can not enable DMA on both channels simultaneously. */
 254         BUG_ON(dma_channel_active(ec->dma));
 255         enable_dma(ec->dma);
 256 }
 257
 258 static int icside_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
 259 {
 260         ide_hwif_t *hwif = drive->hwif;
 261         struct expansion_card *ec = ECARD_DEV(hwif->dev);
 262         struct icside_state *state = ecard_get_drvdata(ec);
 263         unsigned int dma_mode;
 264
 265         if (cmd->tf_flags & IDE_TFLAG_WRITE)
 266                 dma_mode = DMA_MODE_WRITE;
 267         else
 268                 dma_mode = DMA_MODE_READ;
 269
 270         /*
 271          * We can not enable DMA on both channels.
 272          */
 273         BUG_ON(dma_channel_active(ec->dma));
 274
 275         /*
 276          * Route the DMA signals to the correct interface.
 277          */
 278         writeb(state->sel | hwif->channel, state->ioc_base);
 279
 280         /*
 281          * Select the correct timing for this drive.
 282          */
 283         set_dma_speed(ec->dma, (unsigned long)ide_get_drivedata(drive));
 284
 285         /*
 286          * Tell the DMA engine about the SG table and
 287          * data direction.
 288          */
 289         set_dma_sg(ec->dma, hwif->sg_table, cmd->sg_nents);
 290         set_dma_mode(ec->dma, dma_mode);
 291
 292         return 0;
 293 }
 294
 295 static int icside_dma_test_irq(ide_drive_t *drive)
 296 {
 297         ide_hwif_t *hwif = drive->hwif;
 298         struct expansion_card *ec = ECARD_DEV(hwif->dev);
 299         struct icside_state *state = ecard_get_drvdata(ec);
 300
 301         return readb(state->irq_port +
 302                      (hwif->channel ?
 303                         ICS_ARCIN_V6_INTRSTAT_2 :
 304                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 305 }
 306
 307 static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 308 {
 309         hwif->dmatable_cpu      = NULL;
 310         hwif->dmatable_dma      = 0;
 311
 312         return 0;
 313 }
 314
 315 static const struct ide_dma_ops icside_v6_dma_ops = {
 316         .dma_host_set           = icside_dma_host_set,
 317         .dma_setup              = icside_dma_setup,
 318         .dma_start              = icside_dma_start,
 319         .dma_end                = icside_dma_end,
 320         .dma_test_irq           = icside_dma_test_irq,
 321         .dma_lost_irq           = ide_dma_lost_irq,
 322 };
 323 #else
 324 #define icside_v6_dma_ops NULL
 325 #endif
 326
 327 static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 328 {
 329         return -EOPNOTSUPP;
 330 }
 331
 332 static void icside_setup_ports(struct ide_hw *hw, void __iomem *base,
 333                                struct cardinfo *info, struct expansion_card *ec)
 334 {
 335         unsigned long port = (unsigned long)base + info->dataoffset;
 336
 337         hw->io_ports.data_addr   = port;
 338         hw->io_ports.error_addr  = port + (1 << info->stepping);
 339         hw->io_ports.nsect_addr  = port + (2 << info->stepping);
 340         hw->io_ports.lbal_addr   = port + (3 << info->stepping);
 341         hw->io_ports.lbam_addr   = port + (4 << info->stepping);
 342         hw->io_ports.lbah_addr   = port + (5 << info->stepping);
 343         hw->io_ports.device_addr = port + (6 << info->stepping);
 344         hw->io_ports.status_addr = port + (7 << info->stepping);
 345         hw->io_ports.ctl_addr    = (unsigned long)base + info->ctrloffset;
 346
 347         hw->irq = ec->irq;
 348         hw->dev = &ec->dev;
 349 }
 350
 351 static const struct ide_port_info icside_v5_port_info = {
 352         .host_flags             = IDE_HFLAG_NO_DMA,
 353         .chipset                = ide_acorn,
 354 };
 355
 356 static int __devinit
 357 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 358 {
 359         void __iomem *base;
 360         struct ide_host *host;
 361         struct ide_hw hw, *hws[] = { &hw };
 362         int ret;
 363
 364         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
 365         if (!base)
 366                 return -ENOMEM;
 367
 368         state->irq_port = base;
 369
 370         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 371         ec->irqmask  = 1;
 372
 373         ecard_setirq(ec, &icside_ops_arcin_v5, state);
 374
 375         /*
 376          * Be on the safe side - disable interrupts
 377          */
 378         icside_irqdisable_arcin_v5(ec, 0);
 379
 380         icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);
 381
 382         host = ide_host_alloc(&icside_v5_port_info, hws, 1);
 383         if (host == NULL)
 384                 return -ENODEV;
 385
 386         state->host = host;
 387
 388         ecard_set_drvdata(ec, state);
 389
 390         ret = ide_host_register(host, &icside_v5_port_info, hws);
 391         if (ret)
 392                 goto err_free;
 393
 394         return 0;
 395 err_free:
 396         ide_host_free(host);
 397         ecard_set_drvdata(ec, NULL);
 398         return ret;
 399 }
 400
 401 static const struct ide_port_info icside_v6_port_info __initdata = {
 402         .init_dma               = icside_dma_off_init,
 403         .dma_ops                = &icside_v6_dma_ops,
 404         .host_flags             = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
 405         .mwdma_mask             = ATA_MWDMA2,
 406         .swdma_mask             = ATA_SWDMA2,
 407         .chipset                = ide_acorn,
 408 };
 409
 410 static int __devinit
 411 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 412 {
 413         void __iomem *ioc_base, *easi_base;
 414         struct ide_host *host;
 415         unsigned int sel = 0;
 416         int ret;
 417         struct ide_hw hw[2], *hws[] = { &hw[0], &hw[1] };
 418         struct ide_port_info d = icside_v6_port_info;
 419
 420         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 421         if (!ioc_base) {
 422                 ret = -ENOMEM;
 423                 goto out;
 424         }
 425
 426         easi_base = ioc_base;
 427
 428         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 429                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
 430                 if (!easi_base) {
 431                         ret = -ENOMEM;
 432                         goto out;
 433                 }
 434
 435                 /*
 436                  * Enable access to the EASI region.
 437                  */
 438                 sel = 1 << 5;
 439         }
 440
 441         writeb(sel, ioc_base);
 442
 443         ecard_setirq(ec, &icside_ops_arcin_v6, state);
 444
 445         state->irq_port   = easi_base;
 446         state->ioc_base   = ioc_base;
 447         state->sel        = sel;
 448
 449         /*
 450          * Be on the safe side - disable interrupts
 451          */
 452         icside_irqdisable_arcin_v6(ec, 0);
 453
 454         icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
 455         icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);
 456
 457         host = ide_host_alloc(&d, hws, 2);
 458         if (host == NULL)
 459                 return -ENODEV;
 460
 461         state->host = host;
 462
 463         ecard_set_drvdata(ec, state);
 464
 465         if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
 466                 d.init_dma = icside_dma_init;
 467                 d.port_ops = &icside_v6_port_ops;
 468                 d.dma_ops = NULL;
 469         }
 470
 471         ret = ide_host_register(host, &d, hws);
 472         if (ret)
 473                 goto err_free;
 474
 475         return 0;
 476 err_free:
 477         ide_host_free(host);
 478         if (d.dma_ops)
 479                 free_dma(ec->dma);
 480         ecard_set_drvdata(ec, NULL);
 481 out:
 482         return ret;
 483 }
 484
 485 static int __devinit
 486 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 487 {
 488         struct icside_state *state;
 489         void __iomem *idmem;
 490         int ret;
 491
 492         ret = ecard_request_resources(ec);
 493         if (ret)
 494                 goto out;
 495
 496         state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
 497         if (!state) {
 498                 ret = -ENOMEM;
 499                 goto release;
 500         }
 501
 502         state->type     = ICS_TYPE_NOTYPE;
 503
 504         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 505         if (idmem) {
 506                 unsigned int type;
 507
 508                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 509                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 510                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 511                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 512                 ecardm_iounmap(ec, idmem);
 513
 514                 state->type = type;
 515         }
 516
 517         switch (state->type) {
 518         case ICS_TYPE_A3IN:
 519                 dev_warn(&ec->dev, "A3IN unsupported\n");
 520                 ret = -ENODEV;
 521                 break;
 522
 523         case ICS_TYPE_A3USER:
 524                 dev_warn(&ec->dev, "A3USER unsupported\n");
 525                 ret = -ENODEV;
 526                 break;
 527
 528         case ICS_TYPE_V5:
 529                 ret = icside_register_v5(state, ec);
 530                 break;
 531
 532         case ICS_TYPE_V6:
 533                 ret = icside_register_v6(state, ec);
 534                 break;
 535
 536         default:
 537                 dev_warn(&ec->dev, "unknown interface type\n");
 538                 ret = -ENODEV;
 539                 break;
 540         }
 541
 542         if (ret == 0)
 543                 goto out;
 544
 545         kfree(state);
 546  release:
 547         ecard_release_resources(ec);
 548  out:
 549         return ret;
 550 }
 551
 552 static void __devexit icside_remove(struct expansion_card *ec)
 553 {
 554         struct icside_state *state = ecard_get_drvdata(ec);
 555
 556         switch (state->type) {
 557         case ICS_TYPE_V5:
 558                 /* FIXME: tell IDE to stop using the interface */
 559
 560                 /* Disable interrupts */
 561                 icside_irqdisable_arcin_v5(ec, 0);
 562                 break;
 563
 564         case ICS_TYPE_V6:
 565                 /* FIXME: tell IDE to stop using the interface */
 566                 if (ec->dma != NO_DMA)
 567                         free_dma(ec->dma);
 568
 569                 /* Disable interrupts */
 570                 icside_irqdisable_arcin_v6(ec, 0);
 571
 572                 /* Reset the ROM pointer/EASI selection */
 573                 writeb(0, state->ioc_base);
 574                 break;
 575         }
 576
 577         ecard_set_drvdata(ec, NULL);
 578
 579         kfree(state);
 580         ecard_release_resources(ec);
 581 }
 582
 583 static void icside_shutdown(struct expansion_card *ec)
 584 {
 585         struct icside_state *state = ecard_get_drvdata(ec);
 586         unsigned long flags;
 587
 588         /*
 589          * Disable interrupts from this card.  We need to do
 590          * this before disabling EASI since we may be accessing
 591          * this register via that region.
 592          */
 593         local_irq_save(flags);
 594         ec->ops->irqdisable(ec, 0);
 595         local_irq_restore(flags);
 596
 597         /*
 598          * Reset the ROM pointer so that we can read the ROM
 599          * after a soft reboot.  This also disables access to
 600          * the IDE taskfile via the EASI region.
 601          */
 602         if (state->ioc_base)
 603                 writeb(0, state->ioc_base);
 604 }
 605
 606 static const struct ecard_id icside_ids[] = {
 607         { MANU_ICS,  PROD_ICS_IDE  },
 608         { MANU_ICS2, PROD_ICS2_IDE },
 609         { 0xffff, 0xffff }
 610 };
 611
 612 static struct ecard_driver icside_driver = {
 613         .probe          = icside_probe,
 614         .remove         = __devexit_p(icside_remove),
 615         .shutdown       = icside_shutdown,
 616         .id_table       = icside_ids,
 617         .drv = {
 618                 .name   = "icside",
 619         },
 620 };
 621
 622 static int __init icside_init(void)
 623 {
 624         return ecard_register_driver(&icside_driver);
 625 }
 626
 627 static void __exit icside_exit(void)
 628 {
 629         ecard_remove_driver(&icside_driver);
 630 }
 631
 632 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 633 MODULE_LICENSE("GPL");
 634 MODULE_DESCRIPTION("ICS IDE driver");
 635
 636 module_init(icside_init);
 637 module_exit(icside_exit);