2 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
3 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
5 * CYPRESS CY82C693 chipset IDE controller
7 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
8 * Writing the driver was quite simple, since most of the job is
9 * done by the generic pci-ide support.
10 * The hard part was finding the CY82C693's datasheet on Cypress's
11 * web page :-(. But Altavista solved this problem :-).
15 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
16 * a large and fast disk - the results look great, so I'd say the
17 * driver is working fine :-)
18 * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
19 * - this is my first linux driver, so there's probably a lot of room
20 * for optimizations and bug fixing, so feel free to do it.
21 * - if using PIO mode it's a good idea to set the PIO mode and
22 * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
23 * - I had some problems with my IBM DHEA with PIO modes < 2
24 * (lost interrupts) ?????
25 * - first tests with DMA look okay, they seem to work, but there is a
26 * problem with sound - the BusMaster IDE TimeOut should fixed this
29 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
30 * ASK@1999-01-23: v0.33 made a few minor code clean ups
31 * removed DMA clock speed setting by default
33 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
34 * added support to set DMA Controller Clock Speed
35 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
37 * ASK@1998-10-29: v0.3 added support to set DMA modes
38 * ASK@1998-10-28: v0.2 added support to set PIO modes
39 * ASK@1998-10-27: v0.1 first version - chipset detection
43 #include <linux/module.h>
44 #include <linux/types.h>
45 #include <linux/pci.h>
46 #include <linux/ide.h>
47 #include <linux/init.h>
51 #define DRV_NAME "cy82c693"
54 * The following are used to debug the driver.
56 #define CY82C693_DEBUG_LOGS 0
57 #define CY82C693_DEBUG_INFO 0
60 * NOTE: the value for busmaster timeout is tricky and I got it by
61 * trial and error! By using a to low value will cause DMA timeouts
62 * and drop IDE performance, and by using a to high value will cause
63 * audio playback to scatter.
64 * If you know a better value or how to calc it, please let me know.
67 /* twice the value written in cy82c693ub datasheet */
68 #define BUSMASTER_TIMEOUT 0x50
70 * the value above was tested on my machine and it seems to work okay
73 /* here are the offset definitions for the registers */
74 #define CY82_IDE_CMDREG 0x04
75 #define CY82_IDE_ADDRSETUP 0x48
76 #define CY82_IDE_MASTER_IOR 0x4C
77 #define CY82_IDE_MASTER_IOW 0x4D
78 #define CY82_IDE_SLAVE_IOR 0x4E
79 #define CY82_IDE_SLAVE_IOW 0x4F
80 #define CY82_IDE_MASTER_8BIT 0x50
81 #define CY82_IDE_SLAVE_8BIT 0x51
83 #define CY82_INDEX_PORT 0x22
84 #define CY82_DATA_PORT 0x23
86 #define CY82_INDEX_CHANNEL0 0x30
87 #define CY82_INDEX_CHANNEL1 0x31
88 #define CY82_INDEX_TIMEOUT 0x32
90 /* the min and max PCI bus speed in MHz - from datasheet */
91 #define CY82C963_MIN_BUS_SPEED 25
92 #define CY82C963_MAX_BUS_SPEED 33
94 /* the struct for the PIO mode timings */
95 typedef struct pio_clocks_s {
96 u8 address_time; /* Address setup (clocks) */
97 u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
98 u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
99 u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
103 * calc clocks using bus_speed
104 * returns (rounded up) time in bus clocks for time in ns
106 static int calc_clk(int time, int bus_speed)
110 clocks = (time*bus_speed+999)/1000 - 1;
122 * compute the values for the clock registers for PIO
123 * mode and pci_clk [MHz] speed
125 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
126 * for mode 3 and 4 drives 8 and 16-bit timings are the same
129 static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
131 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
133 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
135 /* we don't check against CY82C693's min and max speed,
136 * so you can play with the idebus=xx parameter
139 /* let's calc the address setup time clocks */
140 p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed);
142 /* let's calc the active and recovery time clocks */
143 clk1 = calc_clk(t->active, bus_speed);
145 /* calc recovery timing */
146 clk2 = t->cycle - t->active - t->setup;
148 clk2 = calc_clk(clk2, bus_speed);
150 clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */
152 /* note: we use the same values for 16bit IOR and IOW
153 * those are all the same, since I don't have other
154 * timings than those from ide-lib.c
157 p_pclk->time_16r = (u8)clk1;
158 p_pclk->time_16w = (u8)clk1;
160 /* what are good values for 8bit ?? */
161 p_pclk->time_8 = (u8)clk1;
165 * set DMA mode a specific channel for CY82C693
168 static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
170 ide_hwif_t *hwif = drive->hwif;
171 u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
173 index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
175 #if CY82C693_DEBUG_LOGS
176 /* for debug let's show the previous values */
178 outb(index, CY82_INDEX_PORT);
179 data = inb(CY82_DATA_PORT);
181 printk(KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
182 drive->name, HWIF(drive)->channel, drive->select.b.unit,
183 (data&0x3), ((data>>2)&1));
184 #endif /* CY82C693_DEBUG_LOGS */
186 data = (mode & 3) | (single << 2);
188 outb(index, CY82_INDEX_PORT);
189 outb(data, CY82_DATA_PORT);
191 #if CY82C693_DEBUG_INFO
192 printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
193 drive->name, HWIF(drive)->channel, drive->select.b.unit,
195 #endif /* CY82C693_DEBUG_INFO */
198 * note: below we set the value for Bus Master IDE TimeOut Register
199 * I'm not absolutly sure what this does, but it solved my problem
200 * with IDE DMA and sound, so I now can play sound and work with
201 * my IDE driver at the same time :-)
203 * If you know the correct (best) value for this register please
207 data = BUSMASTER_TIMEOUT;
208 outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
209 outb(data, CY82_DATA_PORT);
211 #if CY82C693_DEBUG_INFO
212 printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
214 #endif /* CY82C693_DEBUG_INFO */
217 static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
219 ide_hwif_t *hwif = HWIF(drive);
220 struct pci_dev *dev = to_pci_dev(hwif->dev);
222 unsigned int addrCtrl;
224 /* select primary or secondary channel */
225 if (hwif->index > 0) { /* drive is on the secondary channel */
226 dev = pci_get_slot(dev->bus, dev->devfn+1);
228 printk(KERN_ERR "%s: tune_drive: "
229 "Cannot find secondary interface!\n",
235 #if CY82C693_DEBUG_LOGS
236 /* for debug let's show the register values */
238 if (drive->select.b.unit == 0) {
240 * get master drive registers
241 * address setup control register
244 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
247 /* now let's get the remaining registers */
248 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
249 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
250 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
253 * set slave drive registers
254 * address setup control register
257 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
262 /* now let's get the remaining registers */
263 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
264 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
265 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
268 printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
269 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
270 drive->name, hwif->channel, drive->select.b.unit,
271 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
272 #endif /* CY82C693_DEBUG_LOGS */
274 /* let's calc the values for this PIO mode */
275 compute_clocks(pio, &pclk);
277 /* now let's write the clocks registers */
278 if (drive->select.b.unit == 0) {
281 * address setup control register
284 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
287 addrCtrl |= (unsigned int)pclk.address_time;
288 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
290 /* now let's set the remaining registers */
291 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
292 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
293 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
299 * address setup control register
302 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
305 addrCtrl |= ((unsigned int)pclk.address_time<<4);
306 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
308 /* now let's set the remaining registers */
309 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
310 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
311 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
317 #if CY82C693_DEBUG_INFO
318 printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
319 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
320 drive->name, hwif->channel, drive->select.b.unit,
321 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
322 #endif /* CY82C693_DEBUG_INFO */
325 static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
327 static ide_hwif_t *primary;
328 struct pci_dev *dev = to_pci_dev(hwif->dev);
330 if (PCI_FUNC(dev->devfn) == 1)
333 hwif->mate = primary;
338 static const struct ide_port_ops cy82c693_port_ops = {
339 .set_pio_mode = cy82c693_set_pio_mode,
340 .set_dma_mode = cy82c693_set_dma_mode,
343 static const struct ide_port_info cy82c693_chipset __devinitdata = {
345 .init_iops = init_iops_cy82c693,
346 .port_ops = &cy82c693_port_ops,
347 .chipset = ide_cy82c693,
348 .host_flags = IDE_HFLAG_SINGLE,
349 .pio_mask = ATA_PIO4,
350 .swdma_mask = ATA_SWDMA2,
351 .mwdma_mask = ATA_MWDMA2,
354 static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
356 struct pci_dev *dev2;
359 /* CY82C693 is more than only a IDE controller.
360 Function 1 is primary IDE channel, function 2 - secondary. */
361 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
362 PCI_FUNC(dev->devfn) == 1) {
363 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
364 ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
371 static void __devexit cy82c693_remove(struct pci_dev *dev)
373 struct ide_host *host = pci_get_drvdata(dev);
374 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
380 static const struct pci_device_id cy82c693_pci_tbl[] = {
381 { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
384 MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
386 static struct pci_driver driver = {
387 .name = "Cypress_IDE",
388 .id_table = cy82c693_pci_tbl,
389 .probe = cy82c693_init_one,
390 .remove = __devexit_p(cy82c693_remove),
391 .suspend = ide_pci_suspend,
392 .resume = ide_pci_resume,
395 static int __init cy82c693_ide_init(void)
397 return ide_pci_register_driver(&driver);
400 static void __exit cy82c693_ide_exit(void)
402 pci_unregister_driver(&driver);
405 module_init(cy82c693_ide_init);
406 module_exit(cy82c693_ide_exit);
408 MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
409 MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
410 MODULE_LICENSE("GPL");