2 * linux/drivers/ide/pci/hpt366.c Version 1.01 Dec 23, 2006
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2006 MontaVista Software, Inc.
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
21 * Note that final HPT370 support was done by force extraction of GPL.
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
56 * Alan Cox <alan@redhat.com>
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * does not allow for this speed anyway
65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * their primary channel is kind of virtual, it isn't tied to any pins)
67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
68 * HPT37x chip family; save space by introducing the separate transfer mode
69 * table in which the mode lookup is done
70 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
71 * the wrong PCI frequency since DPLL has already been calibrated by BIOS
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the rate masking/filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * supported DMA mode, and the chip settings table pointer filled, then, at
103 * the init_chipset stage, allocate per-chip instance and fill it with the
104 * rest of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A
110 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
111 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
112 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
113 * the register setting lists into the table indexed by the clock selected
114 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
117 #include <linux/types.h>
118 #include <linux/module.h>
119 #include <linux/kernel.h>
120 #include <linux/delay.h>
121 #include <linux/timer.h>
122 #include <linux/mm.h>
123 #include <linux/ioport.h>
124 #include <linux/blkdev.h>
125 #include <linux/hdreg.h>
127 #include <linux/interrupt.h>
128 #include <linux/pci.h>
129 #include <linux/init.h>
130 #include <linux/ide.h>
132 #include <asm/uaccess.h>
136 /* various tuning parameters */
137 #define HPT_RESET_STATE_ENGINE
138 #undef HPT_DELAY_INTERRUPT
139 #define HPT_SERIALIZE_IO 0
141 static const char *quirk_drives[] = {
142 "QUANTUM FIREBALLlct08 08",
143 "QUANTUM FIREBALLP KA6.4",
144 "QUANTUM FIREBALLP LM20.4",
145 "QUANTUM FIREBALLP LM20.5",
149 static const char *bad_ata100_5[] = {
168 static const char *bad_ata66_4[] = {
187 static const char *bad_ata66_3[] = {
192 static const char *bad_ata33[] = {
193 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
194 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
195 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
197 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
198 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
199 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
203 static u8 xfer_speeds[] = {
223 /* Key for bus clock timings
226 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
228 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
230 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
232 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
234 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
235 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
236 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
238 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
239 * task file register access.
242 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
247 static u32 forty_base_hpt36x[] = {
248 /* XFER_UDMA_6 */ 0x900fd943,
249 /* XFER_UDMA_5 */ 0x900fd943,
250 /* XFER_UDMA_4 */ 0x900fd943,
251 /* XFER_UDMA_3 */ 0x900ad943,
252 /* XFER_UDMA_2 */ 0x900bd943,
253 /* XFER_UDMA_1 */ 0x9008d943,
254 /* XFER_UDMA_0 */ 0x9008d943,
256 /* XFER_MW_DMA_2 */ 0xa008d943,
257 /* XFER_MW_DMA_1 */ 0xa010d955,
258 /* XFER_MW_DMA_0 */ 0xa010d9fc,
260 /* XFER_PIO_4 */ 0xc008d963,
261 /* XFER_PIO_3 */ 0xc010d974,
262 /* XFER_PIO_2 */ 0xc010d997,
263 /* XFER_PIO_1 */ 0xc010d9c7,
264 /* XFER_PIO_0 */ 0xc018d9d9
267 static u32 thirty_three_base_hpt36x[] = {
268 /* XFER_UDMA_6 */ 0x90c9a731,
269 /* XFER_UDMA_5 */ 0x90c9a731,
270 /* XFER_UDMA_4 */ 0x90c9a731,
271 /* XFER_UDMA_3 */ 0x90cfa731,
272 /* XFER_UDMA_2 */ 0x90caa731,
273 /* XFER_UDMA_1 */ 0x90cba731,
274 /* XFER_UDMA_0 */ 0x90c8a731,
276 /* XFER_MW_DMA_2 */ 0xa0c8a731,
277 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
278 /* XFER_MW_DMA_0 */ 0xa0c8a797,
280 /* XFER_PIO_4 */ 0xc0c8a731,
281 /* XFER_PIO_3 */ 0xc0c8a742,
282 /* XFER_PIO_2 */ 0xc0d0a753,
283 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
284 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
287 static u32 twenty_five_base_hpt36x[] = {
288 /* XFER_UDMA_6 */ 0x90c98521,
289 /* XFER_UDMA_5 */ 0x90c98521,
290 /* XFER_UDMA_4 */ 0x90c98521,
291 /* XFER_UDMA_3 */ 0x90cf8521,
292 /* XFER_UDMA_2 */ 0x90cf8521,
293 /* XFER_UDMA_1 */ 0x90cb8521,
294 /* XFER_UDMA_0 */ 0x90cb8521,
296 /* XFER_MW_DMA_2 */ 0xa0ca8521,
297 /* XFER_MW_DMA_1 */ 0xa0ca8532,
298 /* XFER_MW_DMA_0 */ 0xa0ca8575,
300 /* XFER_PIO_4 */ 0xc0ca8521,
301 /* XFER_PIO_3 */ 0xc0ca8532,
302 /* XFER_PIO_2 */ 0xc0ca8542,
303 /* XFER_PIO_1 */ 0xc0d08572,
304 /* XFER_PIO_0 */ 0xc0d08585
307 static u32 thirty_three_base_hpt37x[] = {
308 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
309 /* XFER_UDMA_5 */ 0x12446231,
310 /* XFER_UDMA_4 */ 0x12446231,
311 /* XFER_UDMA_3 */ 0x126c6231,
312 /* XFER_UDMA_2 */ 0x12486231,
313 /* XFER_UDMA_1 */ 0x124c6233,
314 /* XFER_UDMA_0 */ 0x12506297,
316 /* XFER_MW_DMA_2 */ 0x22406c31,
317 /* XFER_MW_DMA_1 */ 0x22406c33,
318 /* XFER_MW_DMA_0 */ 0x22406c97,
320 /* XFER_PIO_4 */ 0x06414e31,
321 /* XFER_PIO_3 */ 0x06414e42,
322 /* XFER_PIO_2 */ 0x06414e53,
323 /* XFER_PIO_1 */ 0x06814e93,
324 /* XFER_PIO_0 */ 0x06814ea7
327 static u32 fifty_base_hpt37x[] = {
328 /* XFER_UDMA_6 */ 0x12848242,
329 /* XFER_UDMA_5 */ 0x12848242,
330 /* XFER_UDMA_4 */ 0x12ac8242,
331 /* XFER_UDMA_3 */ 0x128c8242,
332 /* XFER_UDMA_2 */ 0x120c8242,
333 /* XFER_UDMA_1 */ 0x12148254,
334 /* XFER_UDMA_0 */ 0x121882ea,
336 /* XFER_MW_DMA_2 */ 0x22808242,
337 /* XFER_MW_DMA_1 */ 0x22808254,
338 /* XFER_MW_DMA_0 */ 0x228082ea,
340 /* XFER_PIO_4 */ 0x0a81f442,
341 /* XFER_PIO_3 */ 0x0a81f443,
342 /* XFER_PIO_2 */ 0x0a81f454,
343 /* XFER_PIO_1 */ 0x0ac1f465,
344 /* XFER_PIO_0 */ 0x0ac1f48a
347 static u32 sixty_six_base_hpt37x[] = {
348 /* XFER_UDMA_6 */ 0x1c869c62,
349 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
350 /* XFER_UDMA_4 */ 0x1c8a9c62,
351 /* XFER_UDMA_3 */ 0x1c8e9c62,
352 /* XFER_UDMA_2 */ 0x1c929c62,
353 /* XFER_UDMA_1 */ 0x1c9a9c62,
354 /* XFER_UDMA_0 */ 0x1c829c62,
356 /* XFER_MW_DMA_2 */ 0x2c829c62,
357 /* XFER_MW_DMA_1 */ 0x2c829c66,
358 /* XFER_MW_DMA_0 */ 0x2c829d2e,
360 /* XFER_PIO_4 */ 0x0c829c62,
361 /* XFER_PIO_3 */ 0x0c829c84,
362 /* XFER_PIO_2 */ 0x0c829ca6,
363 /* XFER_PIO_1 */ 0x0d029d26,
364 /* XFER_PIO_0 */ 0x0d029d5e
367 #define HPT366_DEBUG_DRIVE_INFO 0
368 #define HPT374_ALLOW_ATA133_6 1
369 #define HPT371_ALLOW_ATA133_6 1
370 #define HPT302_ALLOW_ATA133_6 1
371 #define HPT372_ALLOW_ATA133_6 1
372 #define HPT370_ALLOW_ATA100_5 0
373 #define HPT366_ALLOW_ATA66_4 1
374 #define HPT366_ALLOW_ATA66_3 1
375 #define HPT366_MAX_DEVS 8
377 /* Supported ATA clock frequencies */
388 * Hold all the HighPoint chip information in one place.
392 u8 chip_type; /* Chip type */
393 u8 max_mode; /* Speeds allowed */
394 u8 dpll_clk; /* DPLL clock in MHz */
395 u8 pci_clk; /* PCI clock in MHz */
396 u32 **settings; /* Chipset settings table */
399 /* Supported HighPoint chips */
414 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
415 twenty_five_base_hpt36x,
416 thirty_three_base_hpt36x,
422 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
424 thirty_three_base_hpt37x,
427 sixty_six_base_hpt37x
430 static struct hpt_info hpt36x __devinitdata = {
432 .max_mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1,
433 .dpll_clk = 0, /* no DPLL */
434 .settings = hpt36x_settings
437 static struct hpt_info hpt370 __devinitdata = {
439 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2,
441 .settings = hpt37x_settings
444 static struct hpt_info hpt370a __devinitdata = {
445 .chip_type = HPT370A,
446 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2,
448 .settings = hpt37x_settings
451 static struct hpt_info hpt374 __devinitdata = {
453 .max_mode = HPT374_ALLOW_ATA133_6 ? 4 : 3,
455 .settings = hpt37x_settings
458 static struct hpt_info hpt372 __devinitdata = {
460 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
462 .settings = hpt37x_settings
465 static struct hpt_info hpt372a __devinitdata = {
466 .chip_type = HPT372A,
467 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
469 .settings = hpt37x_settings
472 static struct hpt_info hpt302 __devinitdata = {
474 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3,
476 .settings = hpt37x_settings
479 static struct hpt_info hpt371 __devinitdata = {
481 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3,
483 .settings = hpt37x_settings
486 static struct hpt_info hpt372n __devinitdata = {
487 .chip_type = HPT372N,
488 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
490 .settings = hpt37x_settings
493 static struct hpt_info hpt302n __devinitdata = {
494 .chip_type = HPT302N,
495 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3,
499 static struct hpt_info hpt371n __devinitdata = {
500 .chip_type = HPT371N,
501 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3,
503 .settings = hpt37x_settings
506 static int check_in_drive_list(ide_drive_t *drive, const char **list)
508 struct hd_driveid *id = drive->id;
511 if (!strcmp(*list++,id->model))
516 static u8 hpt3xx_ratemask(ide_drive_t *drive)
518 struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev);
519 u8 mode = info->max_mode;
521 if (!eighty_ninty_three(drive) && mode)
522 mode = min(mode, (u8)1);
527 * Note for the future; the SATA hpt37x we must set
528 * either PIO or UDMA modes 0,4,5
531 static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
533 struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev);
534 u8 chip_type = info->chip_type;
535 u8 mode = hpt3xx_ratemask(drive);
537 if (drive->media != ide_disk)
538 return min(speed, (u8)XFER_PIO_4);
542 speed = min_t(u8, speed, XFER_UDMA_6);
545 speed = min_t(u8, speed, XFER_UDMA_5);
546 if (chip_type >= HPT374)
548 if (!check_in_drive_list(drive, bad_ata100_5))
549 goto check_bad_ata33;
552 speed = min_t(u8, speed, XFER_UDMA_4);
555 * CHECK ME, Does this need to be changed to HPT374 ??
557 if (chip_type >= HPT370)
558 goto check_bad_ata33;
559 if (HPT366_ALLOW_ATA66_4 &&
560 !check_in_drive_list(drive, bad_ata66_4))
561 goto check_bad_ata33;
563 speed = min_t(u8, speed, XFER_UDMA_3);
564 if (HPT366_ALLOW_ATA66_3 &&
565 !check_in_drive_list(drive, bad_ata66_3))
566 goto check_bad_ata33;
569 speed = min_t(u8, speed, XFER_UDMA_2);
572 if (chip_type >= HPT370A)
574 if (!check_in_drive_list(drive, bad_ata33))
579 speed = min_t(u8, speed, XFER_MW_DMA_2);
585 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
590 * Lookup the transfer mode table to get the index into
593 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
595 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
596 if (xfer_speeds[i] == speed)
599 * NOTE: info->settings only points to the pointer
600 * to the list of the actual register values
602 return (*info->settings)[i];
605 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
607 ide_hwif_t *hwif = HWIF(drive);
608 struct pci_dev *dev = hwif->pci_dev;
609 struct hpt_info *info = pci_get_drvdata(dev);
610 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
611 u8 itr_addr = drive->dn ? 0x44 : 0x40;
612 u32 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
613 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
614 u32 new_itr = get_speed_setting(speed, info);
618 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
619 * to avoid problems handling I/O errors later
621 pci_read_config_dword(dev, itr_addr, &old_itr);
622 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
623 new_itr &= ~0xc0000000;
625 pci_write_config_dword(dev, itr_addr, new_itr);
627 return ide_config_drive_speed(drive, speed);
630 static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
632 ide_hwif_t *hwif = HWIF(drive);
633 struct pci_dev *dev = hwif->pci_dev;
634 struct hpt_info *info = pci_get_drvdata(dev);
635 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
636 u8 itr_addr = 0x40 + (drive->dn * 4);
637 u32 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
638 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
639 u32 new_itr = get_speed_setting(speed, info);
642 pci_read_config_dword(dev, itr_addr, &old_itr);
643 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
645 if (speed < XFER_MW_DMA_0)
646 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
647 pci_write_config_dword(dev, itr_addr, new_itr);
649 return ide_config_drive_speed(drive, speed);
652 static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
654 ide_hwif_t *hwif = HWIF(drive);
655 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
657 if (info->chip_type >= HPT370)
658 return hpt37x_tune_chipset(drive, speed);
659 else /* hpt368: hpt_minimum_revision(dev, 2) */
660 return hpt36x_tune_chipset(drive, speed);
663 static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
665 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
666 (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
670 * This allows the configuration of ide_pci chipset registers
671 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
672 * after the drive is reported by the OS. Initially designed for
673 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
676 static int config_chipset_for_dma(ide_drive_t *drive)
678 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
683 (void) hpt3xx_tune_chipset(drive, speed);
684 return ide_dma_enable(drive);
687 static int hpt3xx_quirkproc(ide_drive_t *drive)
689 struct hd_driveid *id = drive->id;
690 const char **list = quirk_drives;
693 if (strstr(id->model, *list++))
698 static void hpt3xx_intrproc(ide_drive_t *drive)
700 ide_hwif_t *hwif = HWIF(drive);
702 if (drive->quirk_list)
704 /* drives in the quirk_list may not like intr setups/cleanups */
705 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
708 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
710 ide_hwif_t *hwif = HWIF(drive);
711 struct pci_dev *dev = hwif->pci_dev;
712 struct hpt_info *info = pci_get_drvdata(dev);
714 if (drive->quirk_list) {
715 if (info->chip_type >= HPT370) {
718 pci_read_config_byte(dev, 0x5a, &scr1);
719 if (((scr1 & 0x10) >> 4) != mask) {
724 pci_write_config_byte(dev, 0x5a, scr1);
728 disable_irq(hwif->irq);
730 enable_irq (hwif->irq);
733 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
737 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
739 drive->init_speed = 0;
741 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
744 if (ide_use_fast_pio(drive))
745 hpt3xx_tune_drive(drive, 255);
751 * This is specific to the HPT366 UDMA chipset
752 * by HighPoint|Triones Technologies, Inc.
754 static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
756 struct pci_dev *dev = HWIF(drive)->pci_dev;
757 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
759 pci_read_config_byte(dev, 0x50, &mcr1);
760 pci_read_config_byte(dev, 0x52, &mcr3);
761 pci_read_config_byte(dev, 0x5a, &scr1);
762 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
763 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
765 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
766 return __ide_dma_lostirq(drive);
769 static void hpt370_clear_engine(ide_drive_t *drive)
771 ide_hwif_t *hwif = HWIF(drive);
773 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
777 static void hpt370_irq_timeout(ide_drive_t *drive)
779 ide_hwif_t *hwif = HWIF(drive);
783 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
784 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
786 /* get DMA command mode */
787 dma_cmd = hwif->INB(hwif->dma_command);
789 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
790 hpt370_clear_engine(drive);
793 static void hpt370_ide_dma_start(ide_drive_t *drive)
795 #ifdef HPT_RESET_STATE_ENGINE
796 hpt370_clear_engine(drive);
798 ide_dma_start(drive);
801 static int hpt370_ide_dma_end(ide_drive_t *drive)
803 ide_hwif_t *hwif = HWIF(drive);
804 u8 dma_stat = hwif->INB(hwif->dma_status);
806 if (dma_stat & 0x01) {
809 dma_stat = hwif->INB(hwif->dma_status);
811 hpt370_irq_timeout(drive);
813 return __ide_dma_end(drive);
816 static int hpt370_ide_dma_timeout(ide_drive_t *drive)
818 hpt370_irq_timeout(drive);
819 return __ide_dma_timeout(drive);
822 /* returns 1 if DMA IRQ issued, 0 otherwise */
823 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
825 ide_hwif_t *hwif = HWIF(drive);
829 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
831 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
835 dma_stat = inb(hwif->dma_status);
836 /* return 1 if INTR asserted */
840 if (!drive->waiting_for_dma)
841 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
842 drive->name, __FUNCTION__);
846 static int hpt374_ide_dma_end(ide_drive_t *drive)
848 ide_hwif_t *hwif = HWIF(drive);
849 struct pci_dev *dev = hwif->pci_dev;
850 u8 mcr = 0, mcr_addr = hwif->select_data;
851 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
853 pci_read_config_byte(dev, 0x6a, &bwsr);
854 pci_read_config_byte(dev, mcr_addr, &mcr);
856 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
857 return __ide_dma_end(drive);
861 * hpt3xxn_set_clock - perform clock switching dance
862 * @hwif: hwif to switch
863 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
865 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
868 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
870 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
872 if ((scr2 & 0x7f) == mode)
875 /* Tristate the bus */
876 hwif->OUTB(0x80, hwif->dma_master + 0x73);
877 hwif->OUTB(0x80, hwif->dma_master + 0x77);
879 /* Switch clock and reset channels */
880 hwif->OUTB(mode, hwif->dma_master + 0x7b);
881 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
884 * Reset the state machines.
885 * NOTE: avoid accidentally enabling the disabled channels.
887 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
888 hwif->dma_master + 0x70);
889 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
890 hwif->dma_master + 0x74);
893 hwif->OUTB(0x00, hwif->dma_master + 0x79);
895 /* Reconnect channels to bus */
896 hwif->OUTB(0x00, hwif->dma_master + 0x73);
897 hwif->OUTB(0x00, hwif->dma_master + 0x77);
901 * hpt3xxn_rw_disk - prepare for I/O
902 * @drive: drive for command
903 * @rq: block request structure
905 * This is called when a disk I/O is issued to HPT3xxN.
906 * We need it because of the clock switching.
909 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
911 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
915 * Set/get power state for a drive.
916 * NOTE: affects both drives on each channel.
918 * When we turn the power back on, we need to re-initialize things.
920 #define TRISTATE_BIT 0x8000
922 static int hpt3xx_busproc(ide_drive_t *drive, int state)
924 ide_hwif_t *hwif = HWIF(drive);
925 struct pci_dev *dev = hwif->pci_dev;
926 u8 mcr_addr = hwif->select_data + 2;
927 u8 resetmask = hwif->channel ? 0x80 : 0x40;
931 hwif->bus_state = state;
933 /* Grab the status. */
934 pci_read_config_word(dev, mcr_addr, &mcr);
935 pci_read_config_byte(dev, 0x59, &bsr2);
938 * Set the state. We don't set it if we don't need to do so.
939 * Make sure that the drive knows that it has failed if it's off.
943 if (!(bsr2 & resetmask))
945 hwif->drives[0].failures = hwif->drives[1].failures = 0;
947 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
948 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
951 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
953 mcr &= ~TRISTATE_BIT;
955 case BUSSTATE_TRISTATE:
956 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
964 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
965 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
967 pci_write_config_word(dev, mcr_addr, mcr);
968 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
973 * hpt37x_calibrate_dpll - calibrate the DPLL
976 * Perform a calibration cycle on the DPLL.
977 * Returns 1 if this succeeds
979 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
981 u32 dpll = (f_high << 16) | f_low | 0x100;
985 pci_write_config_dword(dev, 0x5c, dpll);
987 /* Wait for oscillator ready */
988 for(i = 0; i < 0x5000; ++i) {
990 pci_read_config_byte(dev, 0x5b, &scr2);
994 /* See if it stays ready (we'll just bail out if it's not yet) */
995 for(i = 0; i < 0x1000; ++i) {
996 pci_read_config_byte(dev, 0x5b, &scr2);
997 /* DPLL destabilized? */
1001 /* Turn off tuning, we have the DPLL set */
1002 pci_read_config_dword (dev, 0x5c, &dpll);
1003 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
1007 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1009 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
1010 unsigned long io_base = pci_resource_start(dev, 4);
1011 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
1012 enum ata_clock clock;
1015 printk(KERN_ERR "%s: out of memory!\n", name);
1020 * Copy everything from a static "template" structure
1021 * to just allocated per-chip hpt_info structure.
1023 *info = *(struct hpt_info *)pci_get_drvdata(dev);
1026 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1027 * We don't seem to be using it.
1029 if (dev->resource[PCI_ROM_RESOURCE].start)
1030 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1031 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1033 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1034 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1035 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1036 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1039 * First, try to estimate the PCI clock frequency...
1041 if (info->chip_type >= HPT370) {
1046 /* Interrupt force enable. */
1047 pci_read_config_byte(dev, 0x5a, &scr1);
1049 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1052 * HighPoint does this for HPT372A.
1053 * NOTE: This register is only writeable via I/O space.
1055 if (info->chip_type == HPT372A)
1056 outb(0x0e, io_base + 0x9c);
1059 * Default to PCI clock. Make sure MA15/16 are set to output
1060 * to prevent drives having problems with 40-pin cables.
1062 pci_write_config_byte(dev, 0x5b, 0x23);
1065 * We'll have to read f_CNT value in order to determine
1066 * the PCI clock frequency according to the following ratio:
1068 * f_CNT = Fpci * 192 / Fdpll
1070 * First try reading the register in which the HighPoint BIOS
1071 * saves f_CNT value before reprogramming the DPLL from its
1072 * default setting (which differs for the various chips).
1073 * NOTE: This register is only accessible via I/O space.
1075 * In case the signature check fails, we'll have to resort to
1076 * reading the f_CNT register itself in hopes that nobody has
1077 * touched the DPLL yet...
1079 temp = inl(io_base + 0x90);
1080 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1083 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1086 /* Calculate the average value of f_CNT. */
1087 for (temp = i = 0; i < 128; i++) {
1088 pci_read_config_word(dev, 0x78, &f_cnt);
1089 temp += f_cnt & 0x1ff;
1094 f_cnt = temp & 0x1ff;
1096 dpll_clk = info->dpll_clk;
1097 pci_clk = (f_cnt * dpll_clk) / 192;
1099 /* Clamp PCI clock to bands. */
1102 else if(pci_clk < 45)
1104 else if(pci_clk < 55)
1109 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1110 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1114 pci_read_config_dword(dev, 0x40, &itr1);
1116 /* Detect PCI clock by looking at cmd_high_time. */
1117 switch((itr1 >> 8) & 0x07) {
1131 /* Let's assume we'll use PCI clock for the ATA clock... */
1134 clock = ATA_CLOCK_25MHZ;
1138 clock = ATA_CLOCK_33MHZ;
1141 clock = ATA_CLOCK_40MHZ;
1144 clock = ATA_CLOCK_50MHZ;
1147 clock = ATA_CLOCK_66MHZ;
1152 * Only try the DPLL if we don't have a table for the PCI clock that
1153 * we are running at for HPT370/A, always use it for anything newer...
1155 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1156 * We also don't like using the DPLL because this causes glitches
1157 * on PRST-/SRST- when the state engine gets reset...
1159 if (info->chip_type >= HPT374 || info->settings[clock] == NULL) {
1160 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1164 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1165 * supported/enabled, use 50 MHz DPLL clock otherwise...
1167 if (info->max_mode == 0x04) {
1169 clock = ATA_CLOCK_66MHZ;
1170 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1172 clock = ATA_CLOCK_50MHZ;
1175 if (info->settings[clock] == NULL) {
1176 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1181 /* Select the DPLL clock. */
1182 pci_write_config_byte(dev, 0x5b, 0x21);
1185 * Adjust the DPLL based upon PCI clock, enable it,
1186 * and wait for stabilization...
1188 f_low = (pci_clk * 48) / dpll_clk;
1190 for (adjust = 0; adjust < 8; adjust++) {
1191 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1195 * See if it'll settle at a fractionally different clock
1198 f_low -= adjust >> 1;
1200 f_low += adjust >> 1;
1203 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1208 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1210 /* Mark the fact that we're not using the DPLL. */
1213 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1217 * Advance the table pointer to a slot which points to the list
1218 * of the register values settings matching the clock being used.
1220 info->settings += clock;
1222 /* Store the clock frequencies. */
1223 info->dpll_clk = dpll_clk;
1224 info->pci_clk = pci_clk;
1226 /* Point to this chip's own instance of the hpt_info structure. */
1227 pci_set_drvdata(dev, info);
1229 if (info->chip_type >= HPT370) {
1233 * Reset the state engines.
1234 * NOTE: Avoid accidentally enabling the disabled channels.
1236 pci_read_config_byte (dev, 0x50, &mcr1);
1237 pci_read_config_byte (dev, 0x54, &mcr4);
1238 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1239 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1244 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1245 * the MISC. register to stretch the UltraDMA Tss timing.
1246 * NOTE: This register is only writeable via I/O space.
1248 if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1250 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1255 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1257 struct pci_dev *dev = hwif->pci_dev;
1258 struct hpt_info *info = pci_get_drvdata(dev);
1259 int serialize = HPT_SERIALIZE_IO;
1260 u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02;
1261 u8 chip_type = info->chip_type;
1262 u8 new_mcr, old_mcr = 0;
1264 /* Cache the channel's MISC. control registers' offset */
1265 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1267 hwif->tuneproc = &hpt3xx_tune_drive;
1268 hwif->speedproc = &hpt3xx_tune_chipset;
1269 hwif->quirkproc = &hpt3xx_quirkproc;
1270 hwif->intrproc = &hpt3xx_intrproc;
1271 hwif->maskproc = &hpt3xx_maskproc;
1272 hwif->busproc = &hpt3xx_busproc;
1275 * HPT3xxN chips have some complications:
1277 * - on 33 MHz PCI we must clock switch
1278 * - on 66 MHz PCI we must NOT use the PCI clock
1280 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1282 * Clock is shared between the channels,
1283 * so we'll have to serialize them... :-(
1286 hwif->rw_disk = &hpt3xxn_rw_disk;
1289 /* Serialize access to this device if needed */
1290 if (serialize && hwif->mate)
1291 hwif->serialized = hwif->mate->serialized = 1;
1294 * Disable the "fast interrupt" prediction. Don't hold off
1295 * on interrupts. (== 0x01 despite what the docs say)
1297 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1299 if (info->chip_type >= HPT374)
1300 new_mcr = old_mcr & ~0x07;
1301 else if (info->chip_type >= HPT370) {
1305 #ifdef HPT_DELAY_INTERRUPT
1310 } else /* HPT366 and HPT368 */
1311 new_mcr = old_mcr & ~0x80;
1313 if (new_mcr != old_mcr)
1314 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1316 if (!hwif->dma_base) {
1317 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1321 hwif->ultra_mask = 0x7f;
1322 hwif->mwdma_mask = 0x07;
1325 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1326 * address lines to access an external EEPROM. To read valid
1327 * cable detect state the pins must be enabled as inputs.
1329 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1331 * HPT374 PCI function 1
1332 * - set bit 15 of reg 0x52 to enable TCBLID as input
1333 * - set bit 15 of reg 0x56 to enable FCBLID as input
1335 u8 mcr_addr = hwif->select_data + 2;
1338 pci_read_config_word (dev, mcr_addr, &mcr);
1339 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1340 /* now read cable id register */
1341 pci_read_config_byte (dev, 0x5a, &scr1);
1342 pci_write_config_word(dev, mcr_addr, mcr);
1343 } else if (chip_type >= HPT370) {
1345 * HPT370/372 and 374 pcifn 0
1346 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1350 pci_read_config_byte (dev, 0x5b, &scr2);
1351 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1352 /* now read cable id register */
1353 pci_read_config_byte (dev, 0x5a, &scr1);
1354 pci_write_config_byte(dev, 0x5b, scr2);
1356 pci_read_config_byte (dev, 0x5a, &scr1);
1358 if (!hwif->udma_four)
1359 hwif->udma_four = (scr1 & ata66) ? 0 : 1;
1361 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1363 if (chip_type >= HPT374) {
1364 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1365 hwif->ide_dma_end = &hpt374_ide_dma_end;
1366 } else if (chip_type >= HPT370) {
1367 hwif->dma_start = &hpt370_ide_dma_start;
1368 hwif->ide_dma_end = &hpt370_ide_dma_end;
1369 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1371 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1375 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1378 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1380 struct pci_dev *dev = hwif->pci_dev;
1381 u8 masterdma = 0, slavedma = 0;
1382 u8 dma_new = 0, dma_old = 0;
1383 unsigned long flags;
1385 dma_old = hwif->INB(dmabase + 2);
1387 local_irq_save(flags);
1390 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1391 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1393 if (masterdma & 0x30) dma_new |= 0x20;
1394 if ( slavedma & 0x30) dma_new |= 0x40;
1395 if (dma_new != dma_old)
1396 hwif->OUTB(dma_new, dmabase + 2);
1398 local_irq_restore(flags);
1400 ide_setup_dma(hwif, dmabase, 8);
1403 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1405 struct pci_dev *dev2;
1407 if (PCI_FUNC(dev->devfn) & 1)
1410 pci_set_drvdata(dev, &hpt374);
1412 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1415 pci_set_drvdata(dev2, &hpt374);
1417 if (dev2->irq != dev->irq) {
1418 /* FIXME: we need a core pci_set_interrupt() */
1419 dev2->irq = dev->irq;
1420 printk(KERN_WARNING "%s: PCI config space interrupt "
1421 "fixed.\n", d->name);
1423 ret = ide_setup_pci_devices(dev, dev2, d);
1428 return ide_setup_pci_device(dev, d);
1431 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1433 pci_set_drvdata(dev, &hpt372n);
1435 return ide_setup_pci_device(dev, d);
1438 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1440 struct hpt_info *info;
1441 u8 rev = 0, mcr1 = 0;
1443 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1446 d->name = "HPT371N";
1453 * HPT371 chips physically have only one channel, the secondary one,
1454 * but the primary channel registers do exist! Go figure...
1455 * So, we manually disable the non-existing channel here
1456 * (if the BIOS hasn't done this already).
1458 pci_read_config_byte(dev, 0x50, &mcr1);
1460 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1462 pci_set_drvdata(dev, info);
1464 return ide_setup_pci_device(dev, d);
1467 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1469 struct hpt_info *info;
1472 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1475 d->name = "HPT372N";
1480 pci_set_drvdata(dev, info);
1482 return ide_setup_pci_device(dev, d);
1485 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1487 struct hpt_info *info;
1490 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1493 d->name = "HPT302N";
1498 pci_set_drvdata(dev, info);
1500 return ide_setup_pci_device(dev, d);
1503 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1505 struct pci_dev *dev2;
1507 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1508 "HPT370", "HPT370A", "HPT372",
1510 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1511 &hpt370, &hpt370a, &hpt372,
1514 if (PCI_FUNC(dev->devfn) & 1)
1517 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1522 d->name = chipset_names[rev];
1524 pci_set_drvdata(dev, info[rev]);
1531 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1532 u8 pin1 = 0, pin2 = 0;
1535 pci_set_drvdata(dev2, info[rev]);
1537 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1538 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1539 if (pin1 != pin2 && dev->irq == dev2->irq) {
1540 d->bootable = ON_BOARD;
1541 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1542 d->name, pin1, pin2);
1544 ret = ide_setup_pci_devices(dev, dev2, d);
1550 return ide_setup_pci_device(dev, d);
1553 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1556 .init_setup = init_setup_hpt366,
1557 .init_chipset = init_chipset_hpt366,
1558 .init_hwif = init_hwif_hpt366,
1559 .init_dma = init_dma_hpt366,
1562 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1563 .bootable = OFF_BOARD,
1567 .init_setup = init_setup_hpt372a,
1568 .init_chipset = init_chipset_hpt366,
1569 .init_hwif = init_hwif_hpt366,
1570 .init_dma = init_dma_hpt366,
1573 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1574 .bootable = OFF_BOARD,
1578 .init_setup = init_setup_hpt302,
1579 .init_chipset = init_chipset_hpt366,
1580 .init_hwif = init_hwif_hpt366,
1581 .init_dma = init_dma_hpt366,
1584 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1585 .bootable = OFF_BOARD,
1589 .init_setup = init_setup_hpt371,
1590 .init_chipset = init_chipset_hpt366,
1591 .init_hwif = init_hwif_hpt366,
1592 .init_dma = init_dma_hpt366,
1595 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1596 .bootable = OFF_BOARD,
1600 .init_setup = init_setup_hpt374,
1601 .init_chipset = init_chipset_hpt366,
1602 .init_hwif = init_hwif_hpt366,
1603 .init_dma = init_dma_hpt366,
1604 .channels = 2, /* 4 */
1606 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1607 .bootable = OFF_BOARD,
1611 .init_setup = init_setup_hpt372n,
1612 .init_chipset = init_chipset_hpt366,
1613 .init_hwif = init_hwif_hpt366,
1614 .init_dma = init_dma_hpt366,
1615 .channels = 2, /* 4 */
1617 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1618 .bootable = OFF_BOARD,
1624 * hpt366_init_one - called when an HPT366 is found
1625 * @dev: the hpt366 device
1626 * @id: the matching pci id
1628 * Called when the PCI registration layer (or the IDE initialization)
1629 * finds a device matching our IDE device tables.
1631 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1632 * structure depending on the chip's revision, we'd better pass a local
1633 * copy down the call chain...
1635 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1637 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1639 return d.init_setup(dev, &d);
1642 static struct pci_device_id hpt366_pci_tbl[] = {
1643 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1644 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1645 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1646 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1647 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1648 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1651 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1653 static struct pci_driver driver = {
1654 .name = "HPT366_IDE",
1655 .id_table = hpt366_pci_tbl,
1656 .probe = hpt366_init_one,
1659 static int __init hpt366_ide_init(void)
1661 return ide_pci_register_driver(&driver);
1664 module_init(hpt366_ide_init);
1666 MODULE_AUTHOR("Andre Hedrick");
1667 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1668 MODULE_LICENSE("GPL");