2 * Promise TX2/TX4/TX2000/133 IDE driver
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2006 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
24 #include <linux/ioport.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/ide.h>
35 #ifdef CONFIG_PPC_PMAC
37 #include <asm/pci-bridge.h>
40 #define PDC202_DEBUG_CABLE 0
45 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
47 #define DBG(fmt, args...)
50 static const char *pdc_quirk_drives[] = {
51 "QUANTUM FIREBALLlct08 08",
52 "QUANTUM FIREBALLP KA6.4",
53 "QUANTUM FIREBALLP KA9.1",
54 "QUANTUM FIREBALLP LM20.4",
55 "QUANTUM FIREBALLP KX13.6",
56 "QUANTUM FIREBALLP KX20.5",
57 "QUANTUM FIREBALLP KX27.3",
58 "QUANTUM FIREBALLP LM20.5",
62 static u8 max_dma_rate(struct pci_dev *pdev)
66 switch(pdev->device) {
67 case PCI_DEVICE_ID_PROMISE_20277:
68 case PCI_DEVICE_ID_PROMISE_20276:
69 case PCI_DEVICE_ID_PROMISE_20275:
70 case PCI_DEVICE_ID_PROMISE_20271:
71 case PCI_DEVICE_ID_PROMISE_20269:
74 case PCI_DEVICE_ID_PROMISE_20270:
75 case PCI_DEVICE_ID_PROMISE_20268:
86 * get_indexed_reg - Get indexed register
87 * @hwif: for the port address
88 * @index: index of the indexed register
90 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
94 outb(index, hwif->dma_vendor1);
95 value = inb(hwif->dma_vendor3);
97 DBG("index[%02X] value[%02X]\n", index, value);
102 * set_indexed_reg - Set indexed register
103 * @hwif: for the port address
104 * @index: index of the indexed register
106 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
108 outb(index, hwif->dma_vendor1);
109 outb(value, hwif->dma_vendor3);
110 DBG("index[%02X] value[%02X]\n", index, value);
114 * ATA Timing Tables based on 133 MHz PLL output clock.
116 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
117 * the timing registers automatically when "set features" command is
118 * issued to the device. However, if the PLL output clock is 133 MHz,
119 * the following tables must be used.
121 static struct pio_timing {
122 u8 reg0c, reg0d, reg13;
124 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
125 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
126 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
127 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
128 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
131 static struct mwdma_timing {
133 } mwdma_timings [] = {
134 { 0xdf, 0x5f }, /* MWDMA mode 0 */
135 { 0x6b, 0x27 }, /* MWDMA mode 1 */
136 { 0x69, 0x25 }, /* MWDMA mode 2 */
139 static struct udma_timing {
140 u8 reg10, reg11, reg12;
141 } udma_timings [] = {
142 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
143 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
144 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
145 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
146 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
147 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
148 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
151 static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
153 ide_hwif_t *hwif = HWIF(drive);
154 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
157 speed = ide_rate_filter(drive, speed);
160 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
161 * automatically set the timing registers based on 100 MHz PLL output.
163 err = ide_config_drive_speed(drive, speed);
166 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
167 * chips, we must override the default register settings...
169 if (max_dma_rate(hwif->pci_dev) == 4) {
170 u8 mode = speed & 0x07;
180 set_indexed_reg(hwif, 0x10 + adj,
181 udma_timings[mode].reg10);
182 set_indexed_reg(hwif, 0x11 + adj,
183 udma_timings[mode].reg11);
184 set_indexed_reg(hwif, 0x12 + adj,
185 udma_timings[mode].reg12);
191 set_indexed_reg(hwif, 0x0e + adj,
192 mwdma_timings[mode].reg0e);
193 set_indexed_reg(hwif, 0x0f + adj,
194 mwdma_timings[mode].reg0f);
201 set_indexed_reg(hwif, 0x0c + adj,
202 pio_timings[mode].reg0c);
203 set_indexed_reg(hwif, 0x0d + adj,
204 pio_timings[mode].reg0d);
205 set_indexed_reg(hwif, 0x13 + adj,
206 pio_timings[mode].reg13);
209 printk(KERN_ERR "pdc202xx_new: "
210 "Unknown speed %d ignored\n", speed);
212 } else if (speed == XFER_UDMA_2) {
213 /* Set tHOLD bit to 0 if using UDMA mode 2 */
214 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
216 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
222 static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
224 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
225 (void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
228 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
230 return get_indexed_reg(hwif, 0x0b) & 0x04;
233 static int config_chipset_for_dma(ide_drive_t *drive)
235 struct hd_driveid *id = drive->id;
236 ide_hwif_t *hwif = HWIF(drive);
237 u8 ultra_66 = (id->dma_ultra & 0x0078) ? 1 : 0;
238 u8 cable = pdcnew_cable_detect(hwif);
241 if (ultra_66 && cable) {
242 printk(KERN_WARNING "Warning: %s channel "
243 "requires an 80-pin cable for operation.\n",
244 hwif->channel ? "Secondary" : "Primary");
245 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
248 if (id->capability & 4) {
250 * Set IORDY_EN & PREFETCH_EN (this seems to have
251 * NO real effect since this register is reloaded
252 * by hardware when the transfer mode is selected)
254 u8 tmp, adj = (drive->dn & 1) ? 0x08 : 0x00;
256 tmp = get_indexed_reg(hwif, 0x13 + adj);
257 set_indexed_reg(hwif, 0x13 + adj, tmp | 0x03);
260 speed = ide_max_dma_mode(drive);
265 (void) hwif->speedproc(drive, speed);
266 return ide_dma_enable(drive);
269 static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
271 drive->init_speed = 0;
273 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
276 if (ide_use_fast_pio(drive))
277 pdcnew_tune_drive(drive, 255);
282 static int pdcnew_quirkproc(ide_drive_t *drive)
284 const char **list, *model = drive->id->model;
286 for (list = pdc_quirk_drives; *list != NULL; list++)
287 if (strstr(model, *list) != NULL)
292 static void pdcnew_reset(ide_drive_t *drive)
295 * Deleted this because it is redundant from the caller.
297 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
298 HWIF(drive)->channel ? "Secondary" : "Primary");
302 * read_counter - Read the byte count registers
303 * @dma_base: for the port address
305 static long __devinit read_counter(u32 dma_base)
307 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
308 u8 cnt0, cnt1, cnt2, cnt3;
309 long count = 0, last;
315 /* Read the current count */
316 outb(0x20, pri_dma_base + 0x01);
317 cnt0 = inb(pri_dma_base + 0x03);
318 outb(0x21, pri_dma_base + 0x01);
319 cnt1 = inb(pri_dma_base + 0x03);
320 outb(0x20, sec_dma_base + 0x01);
321 cnt2 = inb(sec_dma_base + 0x03);
322 outb(0x21, sec_dma_base + 0x01);
323 cnt3 = inb(sec_dma_base + 0x03);
325 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
328 * The 30-bit decrementing counter is read in 4 pieces.
329 * Incorrect value may be read when the most significant bytes
332 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
334 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
335 cnt0, cnt1, cnt2, cnt3);
341 * detect_pll_input_clock - Detect the PLL input clock in Hz.
342 * @dma_base: for the port address
343 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
345 static long __devinit detect_pll_input_clock(unsigned long dma_base)
347 long start_count, end_count;
351 start_count = read_counter(dma_base);
353 /* Start the test mode */
354 outb(0x01, dma_base + 0x01);
355 scr1 = inb(dma_base + 0x03);
356 DBG("scr1[%02X]\n", scr1);
357 outb(scr1 | 0x40, dma_base + 0x03);
359 /* Let the counter run for 10 ms. */
362 end_count = read_counter(dma_base);
364 /* Stop the test mode */
365 outb(0x01, dma_base + 0x01);
366 scr1 = inb(dma_base + 0x03);
367 DBG("scr1[%02X]\n", scr1);
368 outb(scr1 & ~0x40, dma_base + 0x03);
371 * Calculate the input clock in Hz
372 * (the clock counter is 30 bit wide and counts down)
374 pll_input = ((start_count - end_count) & 0x3ffffff) * 100;
376 DBG("start[%ld] end[%ld]\n", start_count, end_count);
381 #ifdef CONFIG_PPC_PMAC
382 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
384 struct device_node *np = pci_device_to_OF_node(pdev);
385 unsigned int class_rev = 0;
388 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
391 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
394 if (class_rev >= 0x03) {
395 /* Setup chip magic config stuff (from darwin) */
396 pci_read_config_byte (pdev, 0x40, &conf);
397 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
400 #endif /* CONFIG_PPC_PMAC */
402 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
404 unsigned long dma_base = pci_resource_start(dev, 4);
405 unsigned long sec_dma_base = dma_base + 0x08;
406 long pll_input, pll_output, ratio;
408 u8 pll_ctl0, pll_ctl1;
410 if (dev->resource[PCI_ROM_RESOURCE].start) {
411 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
412 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
413 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
414 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
417 #ifdef CONFIG_PPC_PMAC
418 apple_kiwi_init(dev);
421 /* Calculate the required PLL output frequency */
422 switch(max_dma_rate(dev)) {
423 case 4: /* it's 133 MHz for Ultra133 chips */
424 pll_output = 133333333;
426 case 3: /* and 100 MHz for Ultra100 chips */
428 pll_output = 100000000;
433 * Detect PLL input clock.
434 * On some systems, where PCI bus is running at non-standard clock rate
435 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
436 * PDC20268 and newer chips employ PLL circuit to help correct timing
439 pll_input = detect_pll_input_clock(dma_base);
440 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
443 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
444 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
450 DBG("pll_output is %ld Hz\n", pll_output);
452 /* Show the current clock value of PLL control register
453 * (maybe already configured by the BIOS)
455 outb(0x02, sec_dma_base + 0x01);
456 pll_ctl0 = inb(sec_dma_base + 0x03);
457 outb(0x03, sec_dma_base + 0x01);
458 pll_ctl1 = inb(sec_dma_base + 0x03);
460 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
464 * Calculate the ratio of F, R and NO
465 * POUT = (F + 2) / (( R + 2) * NO)
467 ratio = pll_output / (pll_input / 1000);
468 if (ratio < 8600L) { /* 8.6x */
469 /* Using NO = 0x01, R = 0x0d */
471 } else if (ratio < 12900L) { /* 12.9x */
472 /* Using NO = 0x01, R = 0x08 */
474 } else if (ratio < 16100L) { /* 16.1x */
475 /* Using NO = 0x01, R = 0x06 */
477 } else if (ratio < 64000L) { /* 64x */
481 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
485 f = (ratio * (r + 2)) / 1000 - 2;
487 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
489 if (unlikely(f < 0 || f > 127)) {
491 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
498 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
500 outb(0x02, sec_dma_base + 0x01);
501 outb(pll_ctl0, sec_dma_base + 0x03);
502 outb(0x03, sec_dma_base + 0x01);
503 outb(pll_ctl1, sec_dma_base + 0x03);
505 /* Wait the PLL circuit to be stable */
510 * Show the current clock value of PLL control register
512 outb(0x02, sec_dma_base + 0x01);
513 pll_ctl0 = inb(sec_dma_base + 0x03);
514 outb(0x03, sec_dma_base + 0x01);
515 pll_ctl1 = inb(sec_dma_base + 0x03);
517 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
524 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
528 hwif->tuneproc = &pdcnew_tune_drive;
529 hwif->quirkproc = &pdcnew_quirkproc;
530 hwif->speedproc = &pdcnew_tune_chipset;
531 hwif->resetproc = &pdcnew_reset;
533 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
537 hwif->ultra_mask = hwif->cds->udma_mask;
538 hwif->mwdma_mask = 0x07;
540 hwif->err_stops_fifo = 1;
542 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
544 if (!hwif->udma_four)
545 hwif->udma_four = pdcnew_cable_detect(hwif) ? 0 : 1;
549 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
551 #if PDC202_DEBUG_CABLE
552 printk(KERN_DEBUG "%s: %s-pin cable\n",
553 hwif->name, hwif->udma_four ? "80" : "40");
554 #endif /* PDC202_DEBUG_CABLE */
557 static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
559 return ide_setup_pci_device(dev, d);
562 static int __devinit init_setup_pdc20270(struct pci_dev *dev,
565 struct pci_dev *findev = NULL;
568 if ((dev->bus->self &&
569 dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
570 (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
571 if (PCI_SLOT(dev->devfn) & 2)
574 while ((findev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
575 if ((findev->vendor == dev->vendor) &&
576 (findev->device == dev->device) &&
577 (PCI_SLOT(findev->devfn) & 2)) {
578 if (findev->irq != dev->irq) {
579 findev->irq = dev->irq;
581 ret = ide_setup_pci_devices(dev, findev, d);
587 return ide_setup_pci_device(dev, d);
590 static int __devinit init_setup_pdc20276(struct pci_dev *dev,
593 if ((dev->bus->self) &&
594 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
595 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
596 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
597 printk(KERN_INFO "ide: Skipping Promise PDC20276 "
598 "attached to I2O RAID controller.\n");
601 return ide_setup_pci_device(dev, d);
604 static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
607 .init_setup = init_setup_pdcnew,
608 .init_chipset = init_chipset_pdcnew,
609 .init_hwif = init_hwif_pdc202new,
612 .bootable = OFF_BOARD,
613 .udma_mask = 0x3f, /* udma0-5 */
616 .init_setup = init_setup_pdcnew,
617 .init_chipset = init_chipset_pdcnew,
618 .init_hwif = init_hwif_pdc202new,
621 .bootable = OFF_BOARD,
622 .udma_mask = 0x7f, /* udma0-6*/
625 .init_setup = init_setup_pdc20270,
626 .init_chipset = init_chipset_pdcnew,
627 .init_hwif = init_hwif_pdc202new,
630 .bootable = OFF_BOARD,
631 .udma_mask = 0x3f, /* udma0-5 */
634 .init_setup = init_setup_pdcnew,
635 .init_chipset = init_chipset_pdcnew,
636 .init_hwif = init_hwif_pdc202new,
639 .bootable = OFF_BOARD,
640 .udma_mask = 0x7f, /* udma0-6*/
643 .init_setup = init_setup_pdcnew,
644 .init_chipset = init_chipset_pdcnew,
645 .init_hwif = init_hwif_pdc202new,
648 .bootable = OFF_BOARD,
649 .udma_mask = 0x7f, /* udma0-6*/
652 .init_setup = init_setup_pdc20276,
653 .init_chipset = init_chipset_pdcnew,
654 .init_hwif = init_hwif_pdc202new,
657 .bootable = OFF_BOARD,
658 .udma_mask = 0x7f, /* udma0-6*/
661 .init_setup = init_setup_pdcnew,
662 .init_chipset = init_chipset_pdcnew,
663 .init_hwif = init_hwif_pdc202new,
666 .bootable = OFF_BOARD,
667 .udma_mask = 0x7f, /* udma0-6*/
672 * pdc202new_init_one - called when a pdc202xx is found
673 * @dev: the pdc202new device
674 * @id: the matching pci id
676 * Called when the PCI registration layer (or the IDE initialization)
677 * finds a device matching our IDE device tables.
680 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
682 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
684 return d->init_setup(dev, d);
687 static struct pci_device_id pdc202new_pci_tbl[] = {
688 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
689 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
690 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
691 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
692 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
693 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
694 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
697 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
699 static struct pci_driver driver = {
700 .name = "Promise_IDE",
701 .id_table = pdc202new_pci_tbl,
702 .probe = pdc202new_init_one,
705 static int __init pdc202new_ide_init(void)
707 return ide_pci_register_driver(&driver);
710 module_init(pdc202new_ide_init);
712 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
713 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
714 MODULE_LICENSE("GPL");