2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.36 Sept 11, 2002
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc.
7 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
8 * compiled into the kernel if you have more than one card installed.
9 * Note that BIOS v1.29 is reported to fix the problem. Since this is
10 * safe chipset tuning, including this support is harmless
12 * Promise Ultra66 cards with BIOS v1.11 this
13 * compiled into the kernel if you have more than one card installed.
15 * Promise Ultra100 cards.
17 * The latest chipset code will support the following ::
18 * Three Ultra33 controllers and 12 drives.
19 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
20 * The 8/4 ratio is a BIOS code limit by promise.
22 * UNLESS you enable "CONFIG_PDC202XX_BURST"
27 * Portions Copyright (C) 1999 Promise Technology, Inc.
28 * Author: Frank Tiernan (frankt@promise.com)
29 * Released under terms of General Public License
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/timer.h>
38 #include <linux/ioport.h>
39 #include <linux/blkdev.h>
40 #include <linux/hdreg.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/ide.h>
49 #define PDC202_DEBUG_CABLE 0
50 #define PDC202XX_DEBUG_DRIVE_INFO 0
52 static const char *pdc_quirk_drives[] = {
53 "QUANTUM FIREBALLlct08 08",
54 "QUANTUM FIREBALLP KA6.4",
55 "QUANTUM FIREBALLP KA9.1",
56 "QUANTUM FIREBALLP LM20.4",
57 "QUANTUM FIREBALLP KX13.6",
58 "QUANTUM FIREBALLP KX20.5",
59 "QUANTUM FIREBALLP KX27.3",
60 "QUANTUM FIREBALLP LM20.5",
65 #define SYNC_ERRDY_EN 0xC0
67 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
68 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
69 #define IORDY_EN 0x20 /* PIO: IOREADY */
70 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
72 #define PA3 0x08 /* PIO"A" timing */
73 #define PA2 0x04 /* PIO"A" timing */
74 #define PA1 0x02 /* PIO"A" timing */
75 #define PA0 0x01 /* PIO"A" timing */
79 #define MB2 0x80 /* DMA"B" timing */
80 #define MB1 0x40 /* DMA"B" timing */
81 #define MB0 0x20 /* DMA"B" timing */
83 #define PB4 0x10 /* PIO_FORCE 1:0 */
85 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
86 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
87 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
88 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
91 #define IORDYp_NO_SPEED 0x4F
92 #define SPEED_DIS 0x0F
99 #define MC3 0x08 /* DMA"C" timing */
100 #define MC2 0x04 /* DMA"C" timing */
101 #define MC1 0x02 /* DMA"C" timing */
102 #define MC0 0x01 /* DMA"C" timing */
104 static u8 pdc202xx_ratemask (ide_drive_t *drive)
108 switch(HWIF(drive)->pci_dev->device) {
109 case PCI_DEVICE_ID_PROMISE_20267:
110 case PCI_DEVICE_ID_PROMISE_20265:
113 case PCI_DEVICE_ID_PROMISE_20263:
114 case PCI_DEVICE_ID_PROMISE_20262:
117 case PCI_DEVICE_ID_PROMISE_20246:
122 if (!eighty_ninty_three(drive))
123 mode = min(mode, (u8)1);
127 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
129 ide_hwif_t *hwif = HWIF(drive);
130 struct pci_dev *dev = hwif->pci_dev;
131 u8 drive_pci = 0x60 + (drive->dn << 2);
132 u8 speed = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
136 u8 TA = 0, TB = 0, TC = 0;
138 if (drive->media != ide_disk &&
139 drive->media != ide_cdrom && speed < XFER_SW_DMA_0)
142 pci_read_config_dword(dev, drive_pci, &drive_conf);
143 pci_read_config_byte(dev, (drive_pci), &AP);
144 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
145 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
146 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
148 if (speed < XFER_SW_DMA_0) {
149 if ((AP & 0x0F) || (BP & 0x07)) {
150 /* clear PIO modes of lower 8421 bits of A Register */
151 pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
152 pci_read_config_byte(dev, (drive_pci), &AP);
154 /* clear PIO modes of lower 421 bits of B Register */
155 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
156 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
158 pci_read_config_byte(dev, (drive_pci), &AP);
159 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
162 if ((BP & 0xF0) && (CP & 0x0F)) {
163 /* clear DMA modes of upper 842 bits of B Register */
164 /* clear PIO forced mode upper 1 bit of B Register */
165 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
166 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
168 /* clear DMA modes of lower 8421 bits of C Register */
169 pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
170 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
174 pci_read_config_byte(dev, (drive_pci), &AP);
175 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
176 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
179 case XFER_UDMA_6: speed = XFER_UDMA_5;
181 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
182 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
184 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
186 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
187 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
189 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
190 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
191 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
192 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
193 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
194 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
195 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
197 default: TA = 0x09; TB = 0x13; break;
200 if (speed < XFER_SW_DMA_0) {
201 pci_write_config_byte(dev, (drive_pci), AP|TA);
202 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
204 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
205 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
208 #if PDC202XX_DEBUG_DRIVE_INFO
209 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
210 drive->name, ide_xfer_verbose(speed),
211 drive->dn, drive_conf);
212 pci_read_config_dword(dev, drive_pci, &drive_conf);
213 printk("0x%08x\n", drive_conf);
214 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
216 return (ide_config_drive_speed(drive, speed));
220 static void pdc202xx_tune_drive(ide_drive_t *drive, u8 pio)
222 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
223 pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
226 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
228 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
229 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
230 return (CIS & mask) ? 1 : 0;
234 * Set the control register to use the 66MHz system
235 * clock for UDMA 3/4/5 mode operation when necessary.
237 * It may also be possible to leave the 66MHz clock on
238 * and readjust the timing parameters.
240 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
242 unsigned long clock_reg = hwif->dma_master + 0x11;
243 u8 clock = inb(clock_reg);
245 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
248 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
250 unsigned long clock_reg = hwif->dma_master + 0x11;
251 u8 clock = inb(clock_reg);
253 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
256 static int config_chipset_for_dma (ide_drive_t *drive)
258 struct hd_driveid *id = drive->id;
259 ide_hwif_t *hwif = HWIF(drive);
260 struct pci_dev *dev = hwif->pci_dev;
262 u8 drive_pci = 0x60 + (drive->dn << 2);
263 u8 test1 = 0, test2 = 0, speed = -1;
264 u8 AP = 0, cable = 0;
266 u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
267 (id->dma_ultra & 0x0008)) ? 1 : 0;
269 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
270 cable = pdc202xx_old_cable_detect(hwif);
274 if (ultra_66 && cable) {
275 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
276 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
279 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
280 pdc_old_disable_66MHz_clock(drive->hwif);
282 drive_pci = 0x60 + (drive->dn << 2);
283 pci_read_config_dword(dev, drive_pci, &drive_conf);
284 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
287 pci_read_config_byte(dev, drive_pci, &test1);
288 if (!(test1 & SYNC_ERRDY_EN)) {
289 if (drive->select.b.unit & 0x01) {
290 pci_read_config_byte(dev, drive_pci - 4, &test2);
291 if ((test2 & SYNC_ERRDY_EN) &&
292 !(test1 & SYNC_ERRDY_EN)) {
293 pci_write_config_byte(dev, drive_pci,
294 test1|SYNC_ERRDY_EN);
297 pci_write_config_byte(dev, drive_pci,
298 test1|SYNC_ERRDY_EN);
304 pci_read_config_byte(dev, (drive_pci), &AP);
305 if (id->capability & 4) /* IORDY_EN */
306 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
307 pci_read_config_byte(dev, (drive_pci), &AP);
308 if (drive->media == ide_disk) /* PREFETCH_EN */
309 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
311 speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
314 /* restore original pci-config space */
315 pci_write_config_dword(dev, drive_pci, drive_conf);
319 (void) hwif->speedproc(drive, speed);
320 return ide_dma_enable(drive);
323 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
325 ide_hwif_t *hwif = HWIF(drive);
327 drive->init_speed = 0;
329 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
330 return hwif->ide_dma_on(drive);
332 if (ide_use_fast_pio(drive))
333 pdc202xx_tune_drive(drive, 255);
335 return hwif->ide_dma_off_quietly(drive);
338 static int pdc202xx_quirkproc (ide_drive_t *drive)
340 const char **list, *model = drive->id->model;
342 for (list = pdc_quirk_drives; *list != NULL; list++)
343 if (strstr(model, *list) != NULL)
348 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
350 if (drive->current_speed > XFER_UDMA_2)
351 pdc_old_enable_66MHz_clock(drive->hwif);
352 if (drive->media != ide_disk || drive->addressing == 1) {
353 struct request *rq = HWGROUP(drive)->rq;
354 ide_hwif_t *hwif = HWIF(drive);
355 unsigned long high_16 = hwif->dma_master;
356 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
358 u8 clock = inb(high_16 + 0x11);
360 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
361 word_count = (rq->nr_sectors << 8);
362 word_count = (rq_data_dir(rq) == READ) ?
363 word_count | 0x05000000 :
364 word_count | 0x06000000;
365 outl(word_count, atapi_reg);
367 ide_dma_start(drive);
370 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
372 if (drive->media != ide_disk || drive->addressing == 1) {
373 ide_hwif_t *hwif = HWIF(drive);
374 unsigned long high_16 = hwif->dma_master;
375 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
378 outl(0, atapi_reg); /* zero out extra */
379 clock = inb(high_16 + 0x11);
380 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
382 if (drive->current_speed > XFER_UDMA_2)
383 pdc_old_disable_66MHz_clock(drive->hwif);
384 return __ide_dma_end(drive);
387 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
389 ide_hwif_t *hwif = HWIF(drive);
390 unsigned long high_16 = hwif->dma_master;
391 u8 dma_stat = inb(hwif->dma_status);
392 u8 sc1d = inb(high_16 + 0x001d);
395 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
396 if ((sc1d & 0x50) == 0x50)
398 else if ((sc1d & 0x40) == 0x40)
399 return (dma_stat & 4) == 4;
401 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
402 if ((sc1d & 0x05) == 0x05)
404 else if ((sc1d & 0x04) == 0x04)
405 return (dma_stat & 4) == 4;
408 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
411 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
413 if (HWIF(drive)->resetproc != NULL)
414 HWIF(drive)->resetproc(drive);
415 return __ide_dma_lostirq(drive);
418 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
420 if (HWIF(drive)->resetproc != NULL)
421 HWIF(drive)->resetproc(drive);
422 return __ide_dma_timeout(drive);
425 static void pdc202xx_reset_host (ide_hwif_t *hwif)
427 unsigned long high_16 = hwif->dma_master;
428 u8 udma_speed_flag = inb(high_16 | 0x001f);
430 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
432 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
433 mdelay(2000); /* 2 seconds ?! */
435 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
436 hwif->channel ? "Secondary" : "Primary");
439 static void pdc202xx_reset (ide_drive_t *drive)
441 ide_hwif_t *hwif = HWIF(drive);
442 ide_hwif_t *mate = hwif->mate;
444 pdc202xx_reset_host(hwif);
445 pdc202xx_reset_host(mate);
446 pdc202xx_tune_drive(drive, 255);
449 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
452 /* This doesn't appear needed */
453 if (dev->resource[PCI_ROM_RESOURCE].start) {
454 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
455 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
456 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
457 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
463 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
465 struct pci_dev *dev = hwif->pci_dev;
467 /* PDC20265 has problems with large LBA48 requests */
468 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
469 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
473 hwif->tuneproc = &pdc202xx_tune_drive;
474 hwif->quirkproc = &pdc202xx_quirkproc;
476 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
477 hwif->resetproc = &pdc202xx_reset;
479 hwif->speedproc = &pdc202xx_tune_chipset;
481 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
483 hwif->ultra_mask = 0x3f;
484 hwif->mwdma_mask = 0x07;
485 hwif->swdma_mask = 0x07;
488 hwif->err_stops_fifo = 1;
490 hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
491 hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
492 hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
494 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
495 if (!(hwif->udma_four))
496 hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
497 hwif->dma_start = &pdc202xx_old_ide_dma_start;
498 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
500 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
504 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
505 #if PDC202_DEBUG_CABLE
506 printk(KERN_DEBUG "%s: %s-pin cable\n",
507 hwif->name, hwif->udma_four ? "80" : "40");
508 #endif /* PDC202_DEBUG_CABLE */
511 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
513 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
516 ide_setup_dma(hwif, dmabase, 8);
520 udma_speed_flag = inb(dmabase | 0x1f);
521 primary_mode = inb(dmabase | 0x1a);
522 secondary_mode = inb(dmabase | 0x1b);
523 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
525 "Secondary %s Mode.\n", hwif->cds->name,
526 (udma_speed_flag & 1) ? "EN" : "DIS",
527 (primary_mode & 1) ? "MASTER" : "PCI",
528 (secondary_mode & 1) ? "MASTER" : "PCI" );
530 #ifdef CONFIG_PDC202XX_BURST
531 if (!(udma_speed_flag & 1)) {
532 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
533 hwif->cds->name, udma_speed_flag,
534 (udma_speed_flag|1));
535 outb(udma_speed_flag | 1, dmabase | 0x1f);
536 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
538 #endif /* CONFIG_PDC202XX_BURST */
540 ide_setup_dma(hwif, dmabase, 8);
543 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
546 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
547 u8 irq = 0, irq2 = 0;
548 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
550 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
552 pci_write_config_byte(dev,
553 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
554 printk(KERN_INFO "%s: pci-config space interrupt "
555 "mirror fixed.\n", d->name);
558 return ide_setup_pci_device(dev, d);
561 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
564 if ((dev->bus->self) &&
565 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
566 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
567 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
568 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
569 "attached to I2O RAID controller.\n");
572 return ide_setup_pci_device(dev, d);
575 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
578 return ide_setup_pci_device(dev, d);
581 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
584 .init_setup = init_setup_pdc202ata4,
585 .init_chipset = init_chipset_pdc202xx,
586 .init_hwif = init_hwif_pdc202xx,
587 .init_dma = init_dma_pdc202xx,
590 .bootable = OFF_BOARD,
594 .init_setup = init_setup_pdc202ata4,
595 .init_chipset = init_chipset_pdc202xx,
596 .init_hwif = init_hwif_pdc202xx,
597 .init_dma = init_dma_pdc202xx,
600 .bootable = OFF_BOARD,
604 .init_setup = init_setup_pdc202ata4,
605 .init_chipset = init_chipset_pdc202xx,
606 .init_hwif = init_hwif_pdc202xx,
607 .init_dma = init_dma_pdc202xx,
610 .bootable = OFF_BOARD,
614 .init_setup = init_setup_pdc20265,
615 .init_chipset = init_chipset_pdc202xx,
616 .init_hwif = init_hwif_pdc202xx,
617 .init_dma = init_dma_pdc202xx,
620 .bootable = OFF_BOARD,
624 .init_setup = init_setup_pdc202xx,
625 .init_chipset = init_chipset_pdc202xx,
626 .init_hwif = init_hwif_pdc202xx,
627 .init_dma = init_dma_pdc202xx,
630 .bootable = OFF_BOARD,
636 * pdc202xx_init_one - called when a PDC202xx is found
637 * @dev: the pdc202xx device
638 * @id: the matching pci id
640 * Called when the PCI registration layer (or the IDE initialization)
641 * finds a device matching our IDE device tables.
644 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
646 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
648 return d->init_setup(dev, d);
651 static struct pci_device_id pdc202xx_pci_tbl[] = {
652 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
653 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
654 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
655 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
656 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
659 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
661 static struct pci_driver driver = {
662 .name = "Promise_Old_IDE",
663 .id_table = pdc202xx_pci_tbl,
664 .probe = pdc202xx_init_one,
667 static int __init pdc202xx_ide_init(void)
669 return ide_pci_register_driver(&driver);
672 module_init(pdc202xx_ide_init);
674 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
675 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
676 MODULE_LICENSE("GPL");