2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2010, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
53 /* un-comment DEBUG to enable pr_debug() statements */
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/clockchips.h>
59 #include <trace/events/power.h>
60 #include <linux/sched.h>
61 #include <linux/notifier.h>
62 #include <linux/cpu.h>
63 #include <linux/module.h>
64 #include <asm/cpu_device_id.h>
65 #include <asm/mwait.h>
68 #define INTEL_IDLE_VERSION "0.4"
69 #define PREFIX "intel_idle: "
71 static struct cpuidle_driver intel_idle_driver = {
75 /* intel_idle.max_cstate=0 disables driver */
76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
78 static unsigned int mwait_substates;
80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
81 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
82 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
85 struct cpuidle_state *state_table;
88 * Hardware C-state auto-demotion may not always be optimal.
89 * Indicate which enable bits to clear here.
91 unsigned long auto_demotion_disable_flags;
92 bool disable_promotion_to_c1e;
95 static const struct idle_cpu *icpu;
96 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
97 static int intel_idle(struct cpuidle_device *dev,
98 struct cpuidle_driver *drv, int index);
99 static int intel_idle_cpu_init(int cpu);
101 static struct cpuidle_state *cpuidle_state_table;
104 * Set this flag for states where the HW flushes the TLB for us
105 * and so we don't need cross-calls to keep it consistent.
106 * If this flag is set, SW flushes the TLB, so even if the
107 * HW doesn't do the flushing, this flag is safe to use.
109 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
112 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
113 * the C-state (top nibble) and sub-state (bottom nibble)
114 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
116 * We store the hint at the top of our "flags" for each state.
118 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
119 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
122 * States are indexed by the cstate number,
123 * which is also the index into the MWAIT hint array.
124 * Thus C0 is a dummy.
126 static struct cpuidle_state nehalem_cstates[CPUIDLE_STATE_MAX] = {
129 .desc = "MWAIT 0x00",
130 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
132 .target_residency = 6,
133 .enter = &intel_idle },
136 .desc = "MWAIT 0x01",
137 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
139 .target_residency = 20,
140 .enter = &intel_idle },
143 .desc = "MWAIT 0x10",
144 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
146 .target_residency = 80,
147 .enter = &intel_idle },
150 .desc = "MWAIT 0x20",
151 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
153 .target_residency = 800,
154 .enter = &intel_idle },
159 static struct cpuidle_state snb_cstates[CPUIDLE_STATE_MAX] = {
162 .desc = "MWAIT 0x00",
163 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
165 .target_residency = 2,
166 .enter = &intel_idle },
169 .desc = "MWAIT 0x01",
170 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
172 .target_residency = 20,
173 .enter = &intel_idle },
176 .desc = "MWAIT 0x10",
177 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
179 .target_residency = 211,
180 .enter = &intel_idle },
183 .desc = "MWAIT 0x20",
184 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
186 .target_residency = 345,
187 .enter = &intel_idle },
190 .desc = "MWAIT 0x30",
191 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
193 .target_residency = 345,
194 .enter = &intel_idle },
199 static struct cpuidle_state ivb_cstates[CPUIDLE_STATE_MAX] = {
202 .desc = "MWAIT 0x00",
203 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
205 .target_residency = 1,
206 .enter = &intel_idle },
209 .desc = "MWAIT 0x01",
210 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
212 .target_residency = 20,
213 .enter = &intel_idle },
216 .desc = "MWAIT 0x10",
217 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
219 .target_residency = 156,
220 .enter = &intel_idle },
223 .desc = "MWAIT 0x20",
224 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
226 .target_residency = 300,
227 .enter = &intel_idle },
230 .desc = "MWAIT 0x30",
231 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
233 .target_residency = 300,
234 .enter = &intel_idle },
239 static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = {
242 .desc = "MWAIT 0x00",
243 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
245 .target_residency = 2,
246 .enter = &intel_idle },
249 .desc = "MWAIT 0x01",
250 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
252 .target_residency = 20,
253 .enter = &intel_idle },
256 .desc = "MWAIT 0x10",
257 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
259 .target_residency = 100,
260 .enter = &intel_idle },
263 .desc = "MWAIT 0x20",
264 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
266 .target_residency = 400,
267 .enter = &intel_idle },
270 .desc = "MWAIT 0x32",
271 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
273 .target_residency = 500,
274 .enter = &intel_idle },
277 .desc = "MWAIT 0x40",
278 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
280 .target_residency = 900,
281 .enter = &intel_idle },
284 .desc = "MWAIT 0x50",
285 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
287 .target_residency = 1800,
288 .enter = &intel_idle },
291 .desc = "MWAIT 0x60",
292 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
293 .exit_latency = 2600,
294 .target_residency = 7700,
295 .enter = &intel_idle },
300 static struct cpuidle_state atom_cstates[CPUIDLE_STATE_MAX] = {
303 .desc = "MWAIT 0x00",
304 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
306 .target_residency = 20,
307 .enter = &intel_idle },
310 .desc = "MWAIT 0x10",
311 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
313 .target_residency = 80,
314 .enter = &intel_idle },
317 .desc = "MWAIT 0x30",
318 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
320 .target_residency = 400,
321 .enter = &intel_idle },
324 .desc = "MWAIT 0x52",
325 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
327 .target_residency = 560,
328 .enter = &intel_idle },
335 * @dev: cpuidle_device
336 * @drv: cpuidle driver
337 * @index: index of cpuidle state
339 * Must be called under local_irq_disable().
341 static int intel_idle(struct cpuidle_device *dev,
342 struct cpuidle_driver *drv, int index)
344 unsigned long ecx = 1; /* break on interrupt flag */
345 struct cpuidle_state *state = &drv->states[index];
346 unsigned long eax = flg2MWAIT(state->flags);
348 int cpu = smp_processor_id();
350 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
353 * leave_mm() to avoid costly and often unnecessary wakeups
354 * for flushing the user TLB's associated with the active mm.
356 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
359 if (!(lapic_timer_reliable_states & (1 << (cstate))))
360 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
362 if (!current_set_polling_and_test()) {
364 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
365 clflush((void *)¤t_thread_info()->flags);
367 __monitor((void *)¤t_thread_info()->flags, 0, 0);
373 if (!(lapic_timer_reliable_states & (1 << (cstate))))
374 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
379 static void __setup_broadcast_timer(void *arg)
381 unsigned long reason = (unsigned long)arg;
382 int cpu = smp_processor_id();
385 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
387 clockevents_notify(reason, &cpu);
390 static int cpu_hotplug_notify(struct notifier_block *n,
391 unsigned long action, void *hcpu)
393 int hotcpu = (unsigned long)hcpu;
394 struct cpuidle_device *dev;
396 switch (action & 0xf) {
399 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
400 smp_call_function_single(hotcpu, __setup_broadcast_timer,
404 * Some systems can hotplug a cpu at runtime after
405 * the kernel has booted, we have to initialize the
406 * driver in this case
408 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
409 if (!dev->registered)
410 intel_idle_cpu_init(hotcpu);
417 static struct notifier_block cpu_hotplug_notifier = {
418 .notifier_call = cpu_hotplug_notify,
421 static void auto_demotion_disable(void *dummy)
423 unsigned long long msr_bits;
425 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
426 msr_bits &= ~(icpu->auto_demotion_disable_flags);
427 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
429 static void c1e_promotion_disable(void *dummy)
431 unsigned long long msr_bits;
433 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
435 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
438 static const struct idle_cpu idle_cpu_nehalem = {
439 .state_table = nehalem_cstates,
440 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
441 .disable_promotion_to_c1e = true,
444 static const struct idle_cpu idle_cpu_atom = {
445 .state_table = atom_cstates,
448 static const struct idle_cpu idle_cpu_lincroft = {
449 .state_table = atom_cstates,
450 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
453 static const struct idle_cpu idle_cpu_snb = {
454 .state_table = snb_cstates,
455 .disable_promotion_to_c1e = true,
458 static const struct idle_cpu idle_cpu_ivb = {
459 .state_table = ivb_cstates,
460 .disable_promotion_to_c1e = true,
463 static const struct idle_cpu idle_cpu_hsw = {
464 .state_table = hsw_cstates,
465 .disable_promotion_to_c1e = true,
468 #define ICPU(model, cpu) \
469 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
471 static const struct x86_cpu_id intel_idle_ids[] = {
472 ICPU(0x1a, idle_cpu_nehalem),
473 ICPU(0x1e, idle_cpu_nehalem),
474 ICPU(0x1f, idle_cpu_nehalem),
475 ICPU(0x25, idle_cpu_nehalem),
476 ICPU(0x2c, idle_cpu_nehalem),
477 ICPU(0x2e, idle_cpu_nehalem),
478 ICPU(0x1c, idle_cpu_atom),
479 ICPU(0x26, idle_cpu_lincroft),
480 ICPU(0x2f, idle_cpu_nehalem),
481 ICPU(0x2a, idle_cpu_snb),
482 ICPU(0x2d, idle_cpu_snb),
483 ICPU(0x3a, idle_cpu_ivb),
484 ICPU(0x3e, idle_cpu_ivb),
485 ICPU(0x3c, idle_cpu_hsw),
486 ICPU(0x3f, idle_cpu_hsw),
487 ICPU(0x45, idle_cpu_hsw),
488 ICPU(0x46, idle_cpu_hsw),
491 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
496 static int intel_idle_probe(void)
498 unsigned int eax, ebx, ecx;
499 const struct x86_cpu_id *id;
501 if (max_cstate == 0) {
502 pr_debug(PREFIX "disabled\n");
506 id = x86_match_cpu(intel_idle_ids);
508 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
509 boot_cpu_data.x86 == 6)
510 pr_debug(PREFIX "does not run on family %d model %d\n",
511 boot_cpu_data.x86, boot_cpu_data.x86_model);
515 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
518 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
520 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
521 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
525 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
527 icpu = (const struct idle_cpu *)id->driver_data;
528 cpuidle_state_table = icpu->state_table;
530 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
531 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
533 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
535 pr_debug(PREFIX "v" INTEL_IDLE_VERSION
536 " model 0x%X\n", boot_cpu_data.x86_model);
538 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
539 lapic_timer_reliable_states);
544 * intel_idle_cpuidle_devices_uninit()
545 * unregister, free cpuidle_devices
547 static void intel_idle_cpuidle_devices_uninit(void)
550 struct cpuidle_device *dev;
552 for_each_online_cpu(i) {
553 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
554 cpuidle_unregister_device(dev);
557 free_percpu(intel_idle_cpuidle_devices);
561 * intel_idle_cpuidle_driver_init()
562 * allocate, initialize cpuidle_states
564 static int intel_idle_cpuidle_driver_init(void)
567 struct cpuidle_driver *drv = &intel_idle_driver;
569 drv->state_count = 1;
571 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
572 int num_substates, mwait_hint, mwait_cstate, mwait_substate;
574 if (cpuidle_state_table[cstate].enter == NULL)
577 if (cstate + 1 > max_cstate) {
578 printk(PREFIX "max_cstate %d reached\n",
583 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
584 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
585 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint);
587 /* does the state exist in CPUID.MWAIT? */
588 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
589 & MWAIT_SUBSTATE_MASK;
591 /* if sub-state in table is not enumerated by CPUID */
592 if ((mwait_substate + 1) > num_substates)
595 if (((mwait_cstate + 1) > 2) &&
596 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
597 mark_tsc_unstable("TSC halts in idle"
598 " states deeper than C2");
600 drv->states[drv->state_count] = /* structure copy */
601 cpuidle_state_table[cstate];
603 drv->state_count += 1;
606 if (icpu->auto_demotion_disable_flags)
607 on_each_cpu(auto_demotion_disable, NULL, 1);
609 if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */
610 on_each_cpu(c1e_promotion_disable, NULL, 1);
617 * intel_idle_cpu_init()
618 * allocate, initialize, register cpuidle_devices
619 * @cpu: cpu/core to initialize
621 static int intel_idle_cpu_init(int cpu)
624 struct cpuidle_device *dev;
626 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
628 dev->state_count = 1;
630 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
631 int num_substates, mwait_hint, mwait_cstate, mwait_substate;
633 if (cpuidle_state_table[cstate].enter == NULL)
636 if (cstate + 1 > max_cstate) {
637 printk(PREFIX "max_cstate %d reached\n", max_cstate);
641 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
642 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
643 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint);
645 /* does the state exist in CPUID.MWAIT? */
646 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
647 & MWAIT_SUBSTATE_MASK;
649 /* if sub-state in table is not enumerated by CPUID */
650 if ((mwait_substate + 1) > num_substates)
653 dev->state_count += 1;
658 if (cpuidle_register_device(dev)) {
659 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
660 intel_idle_cpuidle_devices_uninit();
664 if (icpu->auto_demotion_disable_flags)
665 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
670 static int __init intel_idle_init(void)
674 /* Do not load intel_idle at all for now if idle= is passed */
675 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
678 retval = intel_idle_probe();
682 intel_idle_cpuidle_driver_init();
683 retval = cpuidle_register_driver(&intel_idle_driver);
685 struct cpuidle_driver *drv = cpuidle_get_driver();
686 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
687 drv ? drv->name : "none");
691 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
692 if (intel_idle_cpuidle_devices == NULL)
695 for_each_online_cpu(i) {
696 retval = intel_idle_cpu_init(i);
698 cpuidle_unregister_driver(&intel_idle_driver);
702 register_cpu_notifier(&cpu_hotplug_notifier);
707 static void __exit intel_idle_exit(void)
709 intel_idle_cpuidle_devices_uninit();
710 cpuidle_unregister_driver(&intel_idle_driver);
713 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
714 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
715 unregister_cpu_notifier(&cpu_hotplug_notifier);
720 module_init(intel_idle_init);
721 module_exit(intel_idle_exit);
723 module_param(max_cstate, int, 0444);
725 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
726 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
727 MODULE_LICENSE("GPL");