drivers/iio/accel/bmc150-accel.c

   1 /*
   2  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
   3  *  - BMC150
   4  *  - BMI055
   5  *  - BMA255
   6  *  - BMA250E
   7  *  - BMA222E
   8  *  - BMA280
   9  *
  10  * Copyright (c) 2014, Intel Corporation.
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms and conditions of the GNU General Public License,
  14  * version 2, as published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/i2c.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/acpi.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/pm.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/iio/iio.h>
  32 #include <linux/iio/sysfs.h>
  33 #include <linux/iio/buffer.h>
  34 #include <linux/iio/events.h>
  35 #include <linux/iio/trigger.h>
  36 #include <linux/iio/trigger_consumer.h>
  37 #include <linux/iio/triggered_buffer.h>
  38
  39 #define BMC150_ACCEL_DRV_NAME                   "bmc150_accel"
  40 #define BMC150_ACCEL_IRQ_NAME                   "bmc150_accel_event"
  41
  42 #define BMC150_ACCEL_REG_CHIP_ID                0x00
  43
  44 #define BMC150_ACCEL_REG_INT_STATUS_2           0x0B
  45 #define BMC150_ACCEL_ANY_MOTION_MASK            0x07
  46 #define BMC150_ACCEL_ANY_MOTION_BIT_X           BIT(0)
  47 #define BMC150_ACCEL_ANY_MOTION_BIT_Y           BIT(1)
  48 #define BMC150_ACCEL_ANY_MOTION_BIT_Z           BIT(2)
  49 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN        BIT(3)
  50
  51 #define BMC150_ACCEL_REG_PMU_LPW                0x11
  52 #define BMC150_ACCEL_PMU_MODE_MASK              0xE0
  53 #define BMC150_ACCEL_PMU_MODE_SHIFT             5
  54 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK     0x17
  55 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT    1
  56
  57 #define BMC150_ACCEL_REG_PMU_RANGE              0x0F
  58
  59 #define BMC150_ACCEL_DEF_RANGE_2G               0x03
  60 #define BMC150_ACCEL_DEF_RANGE_4G               0x05
  61 #define BMC150_ACCEL_DEF_RANGE_8G               0x08
  62 #define BMC150_ACCEL_DEF_RANGE_16G              0x0C
  63
  64 /* Default BW: 125Hz */
  65 #define BMC150_ACCEL_REG_PMU_BW         0x10
  66 #define BMC150_ACCEL_DEF_BW                     125
  67
  68 #define BMC150_ACCEL_REG_INT_MAP_0              0x19
  69 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE        BIT(2)
  70
  71 #define BMC150_ACCEL_REG_INT_MAP_1              0x1A
  72 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA         BIT(0)
  73 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM          BIT(1)
  74 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL        BIT(2)
  75
  76 #define BMC150_ACCEL_REG_INT_RST_LATCH          0x21
  77 #define BMC150_ACCEL_INT_MODE_LATCH_RESET       0x80
  78 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
  79 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT     0x00
  80
  81 #define BMC150_ACCEL_REG_INT_EN_0               0x16
  82 #define BMC150_ACCEL_INT_EN_BIT_SLP_X           BIT(0)
  83 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y           BIT(1)
  84 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z           BIT(2)
  85
  86 #define BMC150_ACCEL_REG_INT_EN_1               0x17
  87 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN         BIT(4)
  88 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN        BIT(5)
  89 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN          BIT(6)
  90
  91 #define BMC150_ACCEL_REG_INT_OUT_CTRL           0x20
  92 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL      BIT(0)
  93
  94 #define BMC150_ACCEL_REG_INT_5                  0x27
  95 #define BMC150_ACCEL_SLOPE_DUR_MASK             0x03
  96
  97 #define BMC150_ACCEL_REG_INT_6                  0x28
  98 #define BMC150_ACCEL_SLOPE_THRES_MASK           0xFF
  99
 100 /* Slope duration in terms of number of samples */
 101 #define BMC150_ACCEL_DEF_SLOPE_DURATION         1
 102 /* in terms of multiples of g's/LSB, based on range */
 103 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD        1
 104
 105 #define BMC150_ACCEL_REG_XOUT_L         0x02
 106
 107 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS        100
 108
 109 /* Sleep Duration values */
 110 #define BMC150_ACCEL_SLEEP_500_MICRO            0x05
 111 #define BMC150_ACCEL_SLEEP_1_MS         0x06
 112 #define BMC150_ACCEL_SLEEP_2_MS         0x07
 113 #define BMC150_ACCEL_SLEEP_4_MS         0x08
 114 #define BMC150_ACCEL_SLEEP_6_MS         0x09
 115 #define BMC150_ACCEL_SLEEP_10_MS                0x0A
 116 #define BMC150_ACCEL_SLEEP_25_MS                0x0B
 117 #define BMC150_ACCEL_SLEEP_50_MS                0x0C
 118 #define BMC150_ACCEL_SLEEP_100_MS               0x0D
 119 #define BMC150_ACCEL_SLEEP_500_MS               0x0E
 120 #define BMC150_ACCEL_SLEEP_1_SEC                0x0F
 121
 122 #define BMC150_ACCEL_REG_TEMP                   0x08
 123 #define BMC150_ACCEL_TEMP_CENTER_VAL            24
 124
 125 #define BMC150_ACCEL_AXIS_TO_REG(axis)  (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
 126 #define BMC150_AUTO_SUSPEND_DELAY_MS            2000
 127
 128 #define BMC150_ACCEL_REG_FIFO_STATUS            0x0E
 129 #define BMC150_ACCEL_REG_FIFO_CONFIG0           0x30
 130 #define BMC150_ACCEL_REG_FIFO_CONFIG1           0x3E
 131 #define BMC150_ACCEL_REG_FIFO_DATA              0x3F
 132 #define BMC150_ACCEL_FIFO_LENGTH                32
 133
 134 enum bmc150_accel_axis {
 135         AXIS_X,
 136         AXIS_Y,
 137         AXIS_Z,
 138 };
 139
 140 enum bmc150_power_modes {
 141         BMC150_ACCEL_SLEEP_MODE_NORMAL,
 142         BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
 143         BMC150_ACCEL_SLEEP_MODE_LPM,
 144         BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
 145 };
 146
 147 struct bmc150_scale_info {
 148         int scale;
 149         u8 reg_range;
 150 };
 151
 152 struct bmc150_accel_chip_info {
 153         const char *name;
 154         u8 chip_id;
 155         const struct iio_chan_spec *channels;
 156         int num_channels;
 157         const struct bmc150_scale_info scale_table[4];
 158 };
 159
 160 struct bmc150_accel_interrupt {
 161         const struct bmc150_accel_interrupt_info *info;
 162         atomic_t users;
 163 };
 164
 165 struct bmc150_accel_trigger {
 166         struct bmc150_accel_data *data;
 167         struct iio_trigger *indio_trig;
 168         int (*setup)(struct bmc150_accel_trigger *t, bool state);
 169         int intr;
 170         bool enabled;
 171 };
 172
 173 enum bmc150_accel_interrupt_id {
 174         BMC150_ACCEL_INT_DATA_READY,
 175         BMC150_ACCEL_INT_ANY_MOTION,
 176         BMC150_ACCEL_INT_WATERMARK,
 177         BMC150_ACCEL_INTERRUPTS,
 178 };
 179
 180 enum bmc150_accel_trigger_id {
 181         BMC150_ACCEL_TRIGGER_DATA_READY,
 182         BMC150_ACCEL_TRIGGER_ANY_MOTION,
 183         BMC150_ACCEL_TRIGGERS,
 184 };
 185
 186 struct bmc150_accel_data {
 187         struct i2c_client *client;
 188         struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
 189         atomic_t active_intr;
 190         struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
 191         struct mutex mutex;
 192         u8 fifo_mode, watermark;
 193         s16 buffer[8];
 194         u8 bw_bits;
 195         u32 slope_dur;
 196         u32 slope_thres;
 197         u32 range;
 198         int ev_enable_state;
 199         int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
 200         const struct bmc150_accel_chip_info *chip_info;
 201 };
 202
 203 static const struct {
 204         int val;
 205         int val2;
 206         u8 bw_bits;
 207 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
 208                                      {31, 260000, 0x09},
 209                                      {62, 500000, 0x0A},
 210                                      {125, 0, 0x0B},
 211                                      {250, 0, 0x0C},
 212                                      {500, 0, 0x0D},
 213                                      {1000, 0, 0x0E},
 214                                      {2000, 0, 0x0F} };
 215
 216 static const struct {
 217         int bw_bits;
 218         int msec;
 219 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
 220                                      {0x09, 32},
 221                                      {0x0A, 16},
 222                                      {0x0B, 8},
 223                                      {0x0C, 4},
 224                                      {0x0D, 2},
 225                                      {0x0E, 1},
 226                                      {0x0F, 1} };
 227
 228 static const struct {
 229         int sleep_dur;
 230         u8 reg_value;
 231 } bmc150_accel_sleep_value_table[] = { {0, 0},
 232                                        {500, BMC150_ACCEL_SLEEP_500_MICRO},
 233                                        {1000, BMC150_ACCEL_SLEEP_1_MS},
 234                                        {2000, BMC150_ACCEL_SLEEP_2_MS},
 235                                        {4000, BMC150_ACCEL_SLEEP_4_MS},
 236                                        {6000, BMC150_ACCEL_SLEEP_6_MS},
 237                                        {10000, BMC150_ACCEL_SLEEP_10_MS},
 238                                        {25000, BMC150_ACCEL_SLEEP_25_MS},
 239                                        {50000, BMC150_ACCEL_SLEEP_50_MS},
 240                                        {100000, BMC150_ACCEL_SLEEP_100_MS},
 241                                        {500000, BMC150_ACCEL_SLEEP_500_MS},
 242                                        {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
 243
 244 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
 245                                  enum bmc150_power_modes mode,
 246                                  int dur_us)
 247 {
 248         int i;
 249         int ret;
 250         u8 lpw_bits;
 251         int dur_val = -1;
 252
 253         if (dur_us > 0) {
 254                 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
 255                                                                          ++i) {
 256                         if (bmc150_accel_sleep_value_table[i].sleep_dur ==
 257                                                                         dur_us)
 258                                 dur_val =
 259                                 bmc150_accel_sleep_value_table[i].reg_value;
 260                 }
 261         } else {
 262                 dur_val = 0;
 263         }
 264
 265         if (dur_val < 0)
 266                 return -EINVAL;
 267
 268         lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
 269         lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
 270
 271         dev_dbg(&data->client->dev, "Set Mode bits %x\n", lpw_bits);
 272
 273         ret = i2c_smbus_write_byte_data(data->client,
 274                                         BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
 275         if (ret < 0) {
 276                 dev_err(&data->client->dev, "Error writing reg_pmu_lpw\n");
 277                 return ret;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
 284                                int val2)
 285 {
 286         int i;
 287         int ret;
 288
 289         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 290                 if (bmc150_accel_samp_freq_table[i].val == val &&
 291                     bmc150_accel_samp_freq_table[i].val2 == val2) {
 292                         ret = i2c_smbus_write_byte_data(
 293                                 data->client,
 294                                 BMC150_ACCEL_REG_PMU_BW,
 295                                 bmc150_accel_samp_freq_table[i].bw_bits);
 296                         if (ret < 0)
 297                                 return ret;
 298
 299                         data->bw_bits =
 300                                 bmc150_accel_samp_freq_table[i].bw_bits;
 301                         return 0;
 302                 }
 303         }
 304
 305         return -EINVAL;
 306 }
 307
 308 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
 309 {
 310         int ret, val;
 311
 312         ret = i2c_smbus_write_byte_data(data->client, BMC150_ACCEL_REG_INT_6,
 313                                         data->slope_thres);
 314         if (ret < 0) {
 315                 dev_err(&data->client->dev, "Error writing reg_int_6\n");
 316                 return ret;
 317         }
 318
 319         ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_INT_5);
 320         if (ret < 0) {
 321                 dev_err(&data->client->dev, "Error reading reg_int_5\n");
 322                 return ret;
 323         }
 324
 325         val = (ret & ~BMC150_ACCEL_SLOPE_DUR_MASK) | data->slope_dur;
 326         ret = i2c_smbus_write_byte_data(data->client, BMC150_ACCEL_REG_INT_5,
 327                                         val);
 328         if (ret < 0) {
 329                 dev_err(&data->client->dev, "Error write reg_int_5\n");
 330                 return ret;
 331         }
 332
 333         dev_dbg(&data->client->dev, "%s: %x %x\n", __func__, data->slope_thres,
 334                 data->slope_dur);
 335
 336         return ret;
 337 }
 338
 339 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
 340                                          bool state)
 341 {
 342         if (state)
 343                 return bmc150_accel_update_slope(t->data);
 344
 345         return 0;
 346 }
 347
 348 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
 349                                int *val2)
 350 {
 351         int i;
 352
 353         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 354                 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
 355                         *val = bmc150_accel_samp_freq_table[i].val;
 356                         *val2 = bmc150_accel_samp_freq_table[i].val2;
 357                         return IIO_VAL_INT_PLUS_MICRO;
 358                 }
 359         }
 360
 361         return -EINVAL;
 362 }
 363
 364 #ifdef CONFIG_PM
 365 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
 366 {
 367         int i;
 368
 369         for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
 370                 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
 371                         return bmc150_accel_sample_upd_time[i].msec;
 372         }
 373
 374         return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
 375 }
 376
 377 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 378 {
 379         int ret;
 380
 381         if (on) {
 382                 ret = pm_runtime_get_sync(&data->client->dev);
 383         } else {
 384                 pm_runtime_mark_last_busy(&data->client->dev);
 385                 ret = pm_runtime_put_autosuspend(&data->client->dev);
 386         }
 387
 388         if (ret < 0) {
 389                 dev_err(&data->client->dev,
 390                         "Failed: bmc150_accel_set_power_state for %d\n", on);
 391                 if (on)
 392                         pm_runtime_put_noidle(&data->client->dev);
 393
 394                 return ret;
 395         }
 396
 397         return 0;
 398 }
 399 #else
 400 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 401 {
 402         return 0;
 403 }
 404 #endif
 405
 406 static const struct bmc150_accel_interrupt_info {
 407         u8 map_reg;
 408         u8 map_bitmask;
 409         u8 en_reg;
 410         u8 en_bitmask;
 411 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
 412         { /* data ready interrupt */
 413                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 414                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
 415                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 416                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
 417         },
 418         {  /* motion interrupt */
 419                 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
 420                 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
 421                 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
 422                 .en_bitmask =  BMC150_ACCEL_INT_EN_BIT_SLP_X |
 423                         BMC150_ACCEL_INT_EN_BIT_SLP_Y |
 424                         BMC150_ACCEL_INT_EN_BIT_SLP_Z
 425         },
 426         { /* fifo watermark interrupt */
 427                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 428                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
 429                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 430                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
 431         },
 432 };
 433
 434 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
 435                                           struct bmc150_accel_data *data)
 436 {
 437         int i;
 438
 439         for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
 440                 data->interrupts[i].info = &bmc150_accel_interrupts[i];
 441 }
 442
 443 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
 444                                       bool state)
 445 {
 446         struct bmc150_accel_interrupt *intr = &data->interrupts[i];
 447         const struct bmc150_accel_interrupt_info *info = intr->info;
 448         int ret;
 449
 450         if (state) {
 451                 if (atomic_inc_return(&intr->users) > 1)
 452                         return 0;
 453         } else {
 454                 if (atomic_dec_return(&intr->users) > 0)
 455                         return 0;
 456         }
 457
 458         /*
 459          * We will expect the enable and disable to do operation in reverse
 460          * order. This will happen here anyway, as our resume operation uses
 461          * sync mode runtime pm calls. The suspend operation will be delayed
 462          * by autosuspend delay.
 463          * So the disable operation will still happen in reverse order of
 464          * enable operation. When runtime pm is disabled the mode is always on,
 465          * so sequence doesn't matter.
 466          */
 467         ret = bmc150_accel_set_power_state(data, state);
 468         if (ret < 0)
 469                 return ret;
 470
 471         /* map the interrupt to the appropriate pins */
 472         ret = i2c_smbus_read_byte_data(data->client, info->map_reg);
 473         if (ret < 0) {
 474                 dev_err(&data->client->dev, "Error reading reg_int_map\n");
 475                 goto out_fix_power_state;
 476         }
 477         if (state)
 478                 ret |= info->map_bitmask;
 479         else
 480                 ret &= ~info->map_bitmask;
 481
 482         ret = i2c_smbus_write_byte_data(data->client, info->map_reg,
 483                                         ret);
 484         if (ret < 0) {
 485                 dev_err(&data->client->dev, "Error writing reg_int_map\n");
 486                 goto out_fix_power_state;
 487         }
 488
 489         /* enable/disable the interrupt */
 490         ret = i2c_smbus_read_byte_data(data->client, info->en_reg);
 491         if (ret < 0) {
 492                 dev_err(&data->client->dev, "Error reading reg_int_en\n");
 493                 goto out_fix_power_state;
 494         }
 495
 496         if (state)
 497                 ret |= info->en_bitmask;
 498         else
 499                 ret &= ~info->en_bitmask;
 500
 501         ret = i2c_smbus_write_byte_data(data->client, info->en_reg, ret);
 502         if (ret < 0) {
 503                 dev_err(&data->client->dev, "Error writing reg_int_en\n");
 504                 goto out_fix_power_state;
 505         }
 506
 507         if (state)
 508                 atomic_inc(&data->active_intr);
 509         else
 510                 atomic_dec(&data->active_intr);
 511
 512         return 0;
 513
 514 out_fix_power_state:
 515         bmc150_accel_set_power_state(data, false);
 516         return ret;
 517 }
 518
 519 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
 520 {
 521         int ret, i;
 522
 523         for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
 524                 if (data->chip_info->scale_table[i].scale == val) {
 525                         ret = i2c_smbus_write_byte_data(
 526                                      data->client,
 527                                      BMC150_ACCEL_REG_PMU_RANGE,
 528                                      data->chip_info->scale_table[i].reg_range);
 529                         if (ret < 0) {
 530                                 dev_err(&data->client->dev,
 531                                         "Error writing pmu_range\n");
 532                                 return ret;
 533                         }
 534
 535                         data->range = data->chip_info->scale_table[i].reg_range;
 536                         return 0;
 537                 }
 538         }
 539
 540         return -EINVAL;
 541 }
 542
 543 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
 544 {
 545         int ret;
 546
 547         mutex_lock(&data->mutex);
 548
 549         ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_TEMP);
 550         if (ret < 0) {
 551                 dev_err(&data->client->dev, "Error reading reg_temp\n");
 552                 mutex_unlock(&data->mutex);
 553                 return ret;
 554         }
 555         *val = sign_extend32(ret, 7);
 556
 557         mutex_unlock(&data->mutex);
 558
 559         return IIO_VAL_INT;
 560 }
 561
 562 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
 563                                  struct iio_chan_spec const *chan,
 564                                  int *val)
 565 {
 566         int ret;
 567         int axis = chan->scan_index;
 568
 569         mutex_lock(&data->mutex);
 570         ret = bmc150_accel_set_power_state(data, true);
 571         if (ret < 0) {
 572                 mutex_unlock(&data->mutex);
 573                 return ret;
 574         }
 575
 576         ret = i2c_smbus_read_word_data(data->client,
 577                                        BMC150_ACCEL_AXIS_TO_REG(axis));
 578         if (ret < 0) {
 579                 dev_err(&data->client->dev, "Error reading axis %d\n", axis);
 580                 bmc150_accel_set_power_state(data, false);
 581                 mutex_unlock(&data->mutex);
 582                 return ret;
 583         }
 584         *val = sign_extend32(ret >> chan->scan_type.shift,
 585                              chan->scan_type.realbits - 1);
 586         ret = bmc150_accel_set_power_state(data, false);
 587         mutex_unlock(&data->mutex);
 588         if (ret < 0)
 589                 return ret;
 590
 591         return IIO_VAL_INT;
 592 }
 593
 594 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
 595                                  struct iio_chan_spec const *chan,
 596                                  int *val, int *val2, long mask)
 597 {
 598         struct bmc150_accel_data *data = iio_priv(indio_dev);
 599         int ret;
 600
 601         switch (mask) {
 602         case IIO_CHAN_INFO_RAW:
 603                 switch (chan->type) {
 604                 case IIO_TEMP:
 605                         return bmc150_accel_get_temp(data, val);
 606                 case IIO_ACCEL:
 607                         if (iio_buffer_enabled(indio_dev))
 608                                 return -EBUSY;
 609                         else
 610                                 return bmc150_accel_get_axis(data, chan, val);
 611                 default:
 612                         return -EINVAL;
 613                 }
 614         case IIO_CHAN_INFO_OFFSET:
 615                 if (chan->type == IIO_TEMP) {
 616                         *val = BMC150_ACCEL_TEMP_CENTER_VAL;
 617                         return IIO_VAL_INT;
 618                 } else {
 619                         return -EINVAL;
 620                 }
 621         case IIO_CHAN_INFO_SCALE:
 622                 *val = 0;
 623                 switch (chan->type) {
 624                 case IIO_TEMP:
 625                         *val2 = 500000;
 626                         return IIO_VAL_INT_PLUS_MICRO;
 627                 case IIO_ACCEL:
 628                 {
 629                         int i;
 630                         const struct bmc150_scale_info *si;
 631                         int st_size = ARRAY_SIZE(data->chip_info->scale_table);
 632
 633                         for (i = 0; i < st_size; ++i) {
 634                                 si = &data->chip_info->scale_table[i];
 635                                 if (si->reg_range == data->range) {
 636                                         *val2 = si->scale;
 637                                         return IIO_VAL_INT_PLUS_MICRO;
 638                                 }
 639                         }
 640                         return -EINVAL;
 641                 }
 642                 default:
 643                         return -EINVAL;
 644                 }
 645         case IIO_CHAN_INFO_SAMP_FREQ:
 646                 mutex_lock(&data->mutex);
 647                 ret = bmc150_accel_get_bw(data, val, val2);
 648                 mutex_unlock(&data->mutex);
 649                 return ret;
 650         default:
 651                 return -EINVAL;
 652         }
 653 }
 654
 655 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
 656                                   struct iio_chan_spec const *chan,
 657                                   int val, int val2, long mask)
 658 {
 659         struct bmc150_accel_data *data = iio_priv(indio_dev);
 660         int ret;
 661
 662         switch (mask) {
 663         case IIO_CHAN_INFO_SAMP_FREQ:
 664                 mutex_lock(&data->mutex);
 665                 ret = bmc150_accel_set_bw(data, val, val2);
 666                 mutex_unlock(&data->mutex);
 667                 break;
 668         case IIO_CHAN_INFO_SCALE:
 669                 if (val)
 670                         return -EINVAL;
 671
 672                 mutex_lock(&data->mutex);
 673                 ret = bmc150_accel_set_scale(data, val2);
 674                 mutex_unlock(&data->mutex);
 675                 return ret;
 676         default:
 677                 ret = -EINVAL;
 678         }
 679
 680         return ret;
 681 }
 682
 683 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
 684                                    const struct iio_chan_spec *chan,
 685                                    enum iio_event_type type,
 686                                    enum iio_event_direction dir,
 687                                    enum iio_event_info info,
 688                                    int *val, int *val2)
 689 {
 690         struct bmc150_accel_data *data = iio_priv(indio_dev);
 691
 692         *val2 = 0;
 693         switch (info) {
 694         case IIO_EV_INFO_VALUE:
 695                 *val = data->slope_thres;
 696                 break;
 697         case IIO_EV_INFO_PERIOD:
 698                 *val = data->slope_dur;
 699                 break;
 700         default:
 701                 return -EINVAL;
 702         }
 703
 704         return IIO_VAL_INT;
 705 }
 706
 707 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
 708                                     const struct iio_chan_spec *chan,
 709                                     enum iio_event_type type,
 710                                     enum iio_event_direction dir,
 711                                     enum iio_event_info info,
 712                                     int val, int val2)
 713 {
 714         struct bmc150_accel_data *data = iio_priv(indio_dev);
 715
 716         if (data->ev_enable_state)
 717                 return -EBUSY;
 718
 719         switch (info) {
 720         case IIO_EV_INFO_VALUE:
 721                 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
 722                 break;
 723         case IIO_EV_INFO_PERIOD:
 724                 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
 725                 break;
 726         default:
 727                 return -EINVAL;
 728         }
 729
 730         return 0;
 731 }
 732
 733 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
 734                                           const struct iio_chan_spec *chan,
 735                                           enum iio_event_type type,
 736                                           enum iio_event_direction dir)
 737 {
 738         struct bmc150_accel_data *data = iio_priv(indio_dev);
 739
 740         return data->ev_enable_state;
 741 }
 742
 743 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
 744                                            const struct iio_chan_spec *chan,
 745                                            enum iio_event_type type,
 746                                            enum iio_event_direction dir,
 747                                            int state)
 748 {
 749         struct bmc150_accel_data *data = iio_priv(indio_dev);
 750         int ret;
 751
 752         if (state == data->ev_enable_state)
 753                 return 0;
 754
 755         mutex_lock(&data->mutex);
 756
 757         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
 758                                          state);
 759         if (ret < 0) {
 760                 mutex_unlock(&data->mutex);
 761                 return ret;
 762         }
 763
 764         data->ev_enable_state = state;
 765         mutex_unlock(&data->mutex);
 766
 767         return 0;
 768 }
 769
 770 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
 771                                          struct iio_trigger *trig)
 772 {
 773         struct bmc150_accel_data *data = iio_priv(indio_dev);
 774         int i;
 775
 776         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
 777                 if (data->triggers[i].indio_trig == trig)
 778                         return 0;
 779         }
 780
 781         return -EINVAL;
 782 }
 783
 784 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
 785                                                struct device_attribute *attr,
 786                                                char *buf)
 787 {
 788         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 789         struct bmc150_accel_data *data = iio_priv(indio_dev);
 790         int wm;
 791
 792         mutex_lock(&data->mutex);
 793         wm = data->watermark;
 794         mutex_unlock(&data->mutex);
 795
 796         return sprintf(buf, "%d\n", wm);
 797 }
 798
 799 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
 800                                            struct device_attribute *attr,
 801                                            char *buf)
 802 {
 803         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 804         struct bmc150_accel_data *data = iio_priv(indio_dev);
 805         bool state;
 806
 807         mutex_lock(&data->mutex);
 808         state = data->fifo_mode;
 809         mutex_unlock(&data->mutex);
 810
 811         return sprintf(buf, "%d\n", state);
 812 }
 813
 814 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
 815 static IIO_CONST_ATTR(hwfifo_watermark_max,
 816                       __stringify(BMC150_ACCEL_FIFO_LENGTH));
 817 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
 818                        bmc150_accel_get_fifo_state, NULL, 0);
 819 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
 820                        bmc150_accel_get_fifo_watermark, NULL, 0);
 821
 822 static const struct attribute *bmc150_accel_fifo_attributes[] = {
 823         &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
 824         &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
 825         &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
 826         &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
 827         NULL,
 828 };
 829
 830 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
 831 {
 832         struct bmc150_accel_data *data = iio_priv(indio_dev);
 833
 834         if (val > BMC150_ACCEL_FIFO_LENGTH)
 835                 val = BMC150_ACCEL_FIFO_LENGTH;
 836
 837         mutex_lock(&data->mutex);
 838         data->watermark = val;
 839         mutex_unlock(&data->mutex);
 840
 841         return 0;
 842 }
 843
 844 /*
 845  * We must read at least one full frame in one burst, otherwise the rest of the
 846  * frame data is discarded.
 847  */
 848 static int bmc150_accel_fifo_transfer(const struct i2c_client *client,
 849                                       char *buffer, int samples)
 850 {
 851         int sample_length = 3 * 2;
 852         u8 reg_fifo_data = BMC150_ACCEL_REG_FIFO_DATA;
 853         int ret = -EIO;
 854
 855         if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
 856                 struct i2c_msg msg[2] = {
 857                         {
 858                                 .addr = client->addr,
 859                                 .flags = 0,
 860                                 .buf = &reg_fifo_data,
 861                                 .len = sizeof(reg_fifo_data),
 862                         },
 863                         {
 864                                 .addr = client->addr,
 865                                 .flags = I2C_M_RD,
 866                                 .buf = (u8 *)buffer,
 867                                 .len = samples * sample_length,
 868                         }
 869                 };
 870
 871                 ret = i2c_transfer(client->adapter, msg, 2);
 872                 if (ret != 2)
 873                         ret = -EIO;
 874                 else
 875                         ret = 0;
 876         } else {
 877                 int i, step = I2C_SMBUS_BLOCK_MAX / sample_length;
 878
 879                 for (i = 0; i < samples * sample_length; i += step) {
 880                         ret = i2c_smbus_read_i2c_block_data(client,
 881                                                             reg_fifo_data, step,
 882                                                             &buffer[i]);
 883                         if (ret != step) {
 884                                 ret = -EIO;
 885                                 break;
 886                         }
 887
 888                         ret = 0;
 889                 }
 890         }
 891
 892         if (ret)
 893                 dev_err(&client->dev, "Error transferring data from fifo\n");
 894
 895         return ret;
 896 }
 897
 898 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
 899                                      unsigned samples, bool irq)
 900 {
 901         struct bmc150_accel_data *data = iio_priv(indio_dev);
 902         int ret, i;
 903         u8 count;
 904         u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
 905         int64_t tstamp;
 906         uint64_t sample_period;
 907
 908         ret = i2c_smbus_read_byte_data(data->client,
 909                                        BMC150_ACCEL_REG_FIFO_STATUS);
 910         if (ret < 0) {
 911                 dev_err(&data->client->dev, "Error reading reg_fifo_status\n");
 912                 return ret;
 913         }
 914
 915         count = ret & 0x7F;
 916
 917         if (!count)
 918                 return 0;
 919
 920         /*
 921          * If we getting called from IRQ handler we know the stored timestamp is
 922          * fairly accurate for the last stored sample. Otherwise, if we are
 923          * called as a result of a read operation from userspace and hence
 924          * before the watermark interrupt was triggered, take a timestamp
 925          * now. We can fall anywhere in between two samples so the error in this
 926          * case is at most one sample period.
 927          */
 928         if (!irq) {
 929                 data->old_timestamp = data->timestamp;
 930                 data->timestamp = iio_get_time_ns();
 931         }
 932
 933         /*
 934          * Approximate timestamps for each of the sample based on the sampling
 935          * frequency, timestamp for last sample and number of samples.
 936          *
 937          * Note that we can't use the current bandwidth settings to compute the
 938          * sample period because the sample rate varies with the device
 939          * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
 940          * small variation adds when we store a large number of samples and
 941          * creates significant jitter between the last and first samples in
 942          * different batches (e.g. 32ms vs 21ms).
 943          *
 944          * To avoid this issue we compute the actual sample period ourselves
 945          * based on the timestamp delta between the last two flush operations.
 946          */
 947         sample_period = (data->timestamp - data->old_timestamp);
 948         do_div(sample_period, count);
 949         tstamp = data->timestamp - (count - 1) * sample_period;
 950
 951         if (samples && count > samples)
 952                 count = samples;
 953
 954         ret = bmc150_accel_fifo_transfer(data->client, (u8 *)buffer, count);
 955         if (ret)
 956                 return ret;
 957
 958         /*
 959          * Ideally we want the IIO core to handle the demux when running in fifo
 960          * mode but not when running in triggered buffer mode. Unfortunately
 961          * this does not seem to be possible, so stick with driver demux for
 962          * now.
 963          */
 964         for (i = 0; i < count; i++) {
 965                 u16 sample[8];
 966                 int j, bit;
 967
 968                 j = 0;
 969                 for_each_set_bit(bit, indio_dev->active_scan_mask,
 970                                  indio_dev->masklength)
 971                         memcpy(&sample[j++], &buffer[i * 3 + bit], 2);
 972
 973                 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp);
 974
 975                 tstamp += sample_period;
 976         }
 977
 978         return count;
 979 }
 980
 981 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
 982 {
 983         struct bmc150_accel_data *data = iio_priv(indio_dev);
 984         int ret;
 985
 986         mutex_lock(&data->mutex);
 987         ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
 988         mutex_unlock(&data->mutex);
 989
 990         return ret;
 991 }
 992
 993 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
 994                 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
 995
 996 static struct attribute *bmc150_accel_attributes[] = {
 997         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 998         NULL,
 999 };
1000
1001 static const struct attribute_group bmc150_accel_attrs_group = {
1002         .attrs = bmc150_accel_attributes,
1003 };
1004
1005 static const struct iio_event_spec bmc150_accel_event = {
1006                 .type = IIO_EV_TYPE_ROC,
1007                 .dir = IIO_EV_DIR_EITHER,
1008                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
1009                                  BIT(IIO_EV_INFO_ENABLE) |
1010                                  BIT(IIO_EV_INFO_PERIOD)
1011 };
1012
1013 #define BMC150_ACCEL_CHANNEL(_axis, bits) {                             \
1014         .type = IIO_ACCEL,                                              \
1015         .modified = 1,                                                  \
1016         .channel2 = IIO_MOD_##_axis,                                    \
1017         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),                   \
1018         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
1019                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),           \
1020         .scan_index = AXIS_##_axis,                                     \
1021         .scan_type = {                                                  \
1022                 .sign = 's',                                            \
1023                 .realbits = (bits),                                     \
1024                 .storagebits = 16,                                      \
1025                 .shift = 16 - (bits),                                   \
1026         },                                                              \
1027         .event_spec = &bmc150_accel_event,                              \
1028         .num_event_specs = 1                                            \
1029 }
1030
1031 #define BMC150_ACCEL_CHANNELS(bits) {                                   \
1032         {                                                               \
1033                 .type = IIO_TEMP,                                       \
1034                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1035                                       BIT(IIO_CHAN_INFO_SCALE) |        \
1036                                       BIT(IIO_CHAN_INFO_OFFSET),        \
1037                 .scan_index = -1,                                       \
1038         },                                                              \
1039         BMC150_ACCEL_CHANNEL(X, bits),                                  \
1040         BMC150_ACCEL_CHANNEL(Y, bits),                                  \
1041         BMC150_ACCEL_CHANNEL(Z, bits),                                  \
1042         IIO_CHAN_SOFT_TIMESTAMP(3),                                     \
1043 }
1044
1045 static const struct iio_chan_spec bma222e_accel_channels[] =
1046         BMC150_ACCEL_CHANNELS(8);
1047 static const struct iio_chan_spec bma250e_accel_channels[] =
1048         BMC150_ACCEL_CHANNELS(10);
1049 static const struct iio_chan_spec bmc150_accel_channels[] =
1050         BMC150_ACCEL_CHANNELS(12);
1051 static const struct iio_chan_spec bma280_accel_channels[] =
1052         BMC150_ACCEL_CHANNELS(14);
1053
1054 enum {
1055         bmc150,
1056         bmi055,
1057         bma255,
1058         bma250e,
1059         bma222e,
1060         bma280,
1061 };
1062
1063 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1064         [bmc150] = {
1065                 .name = "BMC150A",
1066                 .chip_id = 0xFA,
1067                 .channels = bmc150_accel_channels,
1068                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1069                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1070                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1071                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1072                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1073         },
1074         [bmi055] = {
1075                 .name = "BMI055A",
1076                 .chip_id = 0xFA,
1077                 .channels = bmc150_accel_channels,
1078                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1079                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1080                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1081                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1082                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1083         },
1084         [bma255] = {
1085                 .name = "BMA0255",
1086                 .chip_id = 0xFA,
1087                 .channels = bmc150_accel_channels,
1088                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1089                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1090                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1091                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1092                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1093         },
1094         [bma250e] = {
1095                 .name = "BMA250E",
1096                 .chip_id = 0xF9,
1097                 .channels = bma250e_accel_channels,
1098                 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1099                 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1100                                  {76590, BMC150_ACCEL_DEF_RANGE_4G},
1101                                  {153277, BMC150_ACCEL_DEF_RANGE_8G},
1102                                  {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1103         },
1104         [bma222e] = {
1105                 .name = "BMA222E",
1106                 .chip_id = 0xF8,
1107                 .channels = bma222e_accel_channels,
1108                 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1109                 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1110                                  {306457, BMC150_ACCEL_DEF_RANGE_4G},
1111                                  {612915, BMC150_ACCEL_DEF_RANGE_8G},
1112                                  {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1113         },
1114         [bma280] = {
1115                 .name = "BMA0280",
1116                 .chip_id = 0xFB,
1117                 .channels = bma280_accel_channels,
1118                 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1119                 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1120                                  {4785, BMC150_ACCEL_DEF_RANGE_4G},
1121                                  {9581, BMC150_ACCEL_DEF_RANGE_8G},
1122                                  {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1123         },
1124 };
1125
1126 static const struct iio_info bmc150_accel_info = {
1127         .attrs                  = &bmc150_accel_attrs_group,
1128         .read_raw               = bmc150_accel_read_raw,
1129         .write_raw              = bmc150_accel_write_raw,
1130         .read_event_value       = bmc150_accel_read_event,
1131         .write_event_value      = bmc150_accel_write_event,
1132         .write_event_config     = bmc150_accel_write_event_config,
1133         .read_event_config      = bmc150_accel_read_event_config,
1134         .driver_module          = THIS_MODULE,
1135 };
1136
1137 static const struct iio_info bmc150_accel_info_fifo = {
1138         .attrs                  = &bmc150_accel_attrs_group,
1139         .read_raw               = bmc150_accel_read_raw,
1140         .write_raw              = bmc150_accel_write_raw,
1141         .read_event_value       = bmc150_accel_read_event,
1142         .write_event_value      = bmc150_accel_write_event,
1143         .write_event_config     = bmc150_accel_write_event_config,
1144         .read_event_config      = bmc150_accel_read_event_config,
1145         .validate_trigger       = bmc150_accel_validate_trigger,
1146         .hwfifo_set_watermark   = bmc150_accel_set_watermark,
1147         .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1148         .driver_module          = THIS_MODULE,
1149 };
1150
1151 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1152 {
1153         struct iio_poll_func *pf = p;
1154         struct iio_dev *indio_dev = pf->indio_dev;
1155         struct bmc150_accel_data *data = iio_priv(indio_dev);
1156         int bit, ret, i = 0;
1157
1158         mutex_lock(&data->mutex);
1159         for_each_set_bit(bit, indio_dev->active_scan_mask,
1160                          indio_dev->masklength) {
1161                 ret = i2c_smbus_read_word_data(data->client,
1162                                                BMC150_ACCEL_AXIS_TO_REG(bit));
1163                 if (ret < 0) {
1164                         mutex_unlock(&data->mutex);
1165                         goto err_read;
1166                 }
1167                 data->buffer[i++] = ret;
1168         }
1169         mutex_unlock(&data->mutex);
1170
1171         iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1172                                            pf->timestamp);
1173 err_read:
1174         iio_trigger_notify_done(indio_dev->trig);
1175
1176         return IRQ_HANDLED;
1177 }
1178
1179 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1180 {
1181         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1182         struct bmc150_accel_data *data = t->data;
1183         int ret;
1184
1185         /* new data interrupts don't need ack */
1186         if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1187                 return 0;
1188
1189         mutex_lock(&data->mutex);
1190         /* clear any latched interrupt */
1191         ret = i2c_smbus_write_byte_data(data->client,
1192                                         BMC150_ACCEL_REG_INT_RST_LATCH,
1193                                         BMC150_ACCEL_INT_MODE_LATCH_INT |
1194                                         BMC150_ACCEL_INT_MODE_LATCH_RESET);
1195         mutex_unlock(&data->mutex);
1196         if (ret < 0) {
1197                 dev_err(&data->client->dev,
1198                         "Error writing reg_int_rst_latch\n");
1199                 return ret;
1200         }
1201
1202         return 0;
1203 }
1204
1205 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1206                                           bool state)
1207 {
1208         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1209         struct bmc150_accel_data *data = t->data;
1210         int ret;
1211
1212         mutex_lock(&data->mutex);
1213
1214         if (t->enabled == state) {
1215                 mutex_unlock(&data->mutex);
1216                 return 0;
1217         }
1218
1219         if (t->setup) {
1220                 ret = t->setup(t, state);
1221                 if (ret < 0) {
1222                         mutex_unlock(&data->mutex);
1223                         return ret;
1224                 }
1225         }
1226
1227         ret = bmc150_accel_set_interrupt(data, t->intr, state);
1228         if (ret < 0) {
1229                 mutex_unlock(&data->mutex);
1230                 return ret;
1231         }
1232
1233         t->enabled = state;
1234
1235         mutex_unlock(&data->mutex);
1236
1237         return ret;
1238 }
1239
1240 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1241         .set_trigger_state = bmc150_accel_trigger_set_state,
1242         .try_reenable = bmc150_accel_trig_try_reen,
1243         .owner = THIS_MODULE,
1244 };
1245
1246 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1247 {
1248         struct bmc150_accel_data *data = iio_priv(indio_dev);
1249         int dir;
1250         int ret;
1251
1252         ret = i2c_smbus_read_byte_data(data->client,
1253                                        BMC150_ACCEL_REG_INT_STATUS_2);
1254         if (ret < 0) {
1255                 dev_err(&data->client->dev, "Error reading reg_int_status_2\n");
1256                 return ret;
1257         }
1258
1259         if (ret & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1260                 dir = IIO_EV_DIR_FALLING;
1261         else
1262                 dir = IIO_EV_DIR_RISING;
1263
1264         if (ret & BMC150_ACCEL_ANY_MOTION_BIT_X)
1265                 iio_push_event(indio_dev,
1266                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1267                                                   0,
1268                                                   IIO_MOD_X,
1269                                                   IIO_EV_TYPE_ROC,
1270                                                   dir),
1271                                data->timestamp);
1272
1273         if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1274                 iio_push_event(indio_dev,
1275                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1276                                                   0,
1277                                                   IIO_MOD_Y,
1278                                                   IIO_EV_TYPE_ROC,
1279                                                   dir),
1280                                data->timestamp);
1281
1282         if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1283                 iio_push_event(indio_dev,
1284                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1285                                                   0,
1286                                                   IIO_MOD_Z,
1287                                                   IIO_EV_TYPE_ROC,
1288                                                   dir),
1289                                data->timestamp);
1290
1291         return ret;
1292 }
1293
1294 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1295 {
1296         struct iio_dev *indio_dev = private;
1297         struct bmc150_accel_data *data = iio_priv(indio_dev);
1298         bool ack = false;
1299         int ret;
1300
1301         mutex_lock(&data->mutex);
1302
1303         if (data->fifo_mode) {
1304                 ret = __bmc150_accel_fifo_flush(indio_dev,
1305                                                 BMC150_ACCEL_FIFO_LENGTH, true);
1306                 if (ret > 0)
1307                         ack = true;
1308         }
1309
1310         if (data->ev_enable_state) {
1311                 ret = bmc150_accel_handle_roc_event(indio_dev);
1312                 if (ret > 0)
1313                         ack = true;
1314         }
1315
1316         if (ack) {
1317                 ret = i2c_smbus_write_byte_data(data->client,
1318                                         BMC150_ACCEL_REG_INT_RST_LATCH,
1319                                         BMC150_ACCEL_INT_MODE_LATCH_INT |
1320                                         BMC150_ACCEL_INT_MODE_LATCH_RESET);
1321                 if (ret)
1322                         dev_err(&data->client->dev,
1323                                 "Error writing reg_int_rst_latch\n");
1324
1325                 ret = IRQ_HANDLED;
1326         } else {
1327                 ret = IRQ_NONE;
1328         }
1329
1330         mutex_unlock(&data->mutex);
1331
1332         return ret;
1333 }
1334
1335 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1336 {
1337         struct iio_dev *indio_dev = private;
1338         struct bmc150_accel_data *data = iio_priv(indio_dev);
1339         bool ack = false;
1340         int i;
1341
1342         data->old_timestamp = data->timestamp;
1343         data->timestamp = iio_get_time_ns();
1344
1345         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1346                 if (data->triggers[i].enabled) {
1347                         iio_trigger_poll(data->triggers[i].indio_trig);
1348                         ack = true;
1349                         break;
1350                 }
1351         }
1352
1353         if (data->ev_enable_state || data->fifo_mode)
1354                 return IRQ_WAKE_THREAD;
1355
1356         if (ack)
1357                 return IRQ_HANDLED;
1358
1359         return IRQ_NONE;
1360 }
1361
1362 static const struct {
1363         int intr;
1364         const char *name;
1365         int (*setup)(struct bmc150_accel_trigger *t, bool state);
1366 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1367         {
1368                 .intr = 0,
1369                 .name = "%s-dev%d",
1370         },
1371         {
1372                 .intr = 1,
1373                 .name = "%s-any-motion-dev%d",
1374                 .setup = bmc150_accel_any_motion_setup,
1375         },
1376 };
1377
1378 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1379                                              int from)
1380 {
1381         int i;
1382
1383         for (i = from; i >= 0; i--) {
1384                 if (data->triggers[i].indio_trig) {
1385                         iio_trigger_unregister(data->triggers[i].indio_trig);
1386                         data->triggers[i].indio_trig = NULL;
1387                 }
1388         }
1389 }
1390
1391 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1392                                        struct bmc150_accel_data *data)
1393 {
1394         int i, ret;
1395
1396         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1397                 struct bmc150_accel_trigger *t = &data->triggers[i];
1398
1399                 t->indio_trig = devm_iio_trigger_alloc(&data->client->dev,
1400                                                bmc150_accel_triggers[i].name,
1401                                                        indio_dev->name,
1402                                                        indio_dev->id);
1403                 if (!t->indio_trig) {
1404                         ret = -ENOMEM;
1405                         break;
1406                 }
1407
1408                 t->indio_trig->dev.parent = &data->client->dev;
1409                 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1410                 t->intr = bmc150_accel_triggers[i].intr;
1411                 t->data = data;
1412                 t->setup = bmc150_accel_triggers[i].setup;
1413                 iio_trigger_set_drvdata(t->indio_trig, t);
1414
1415                 ret = iio_trigger_register(t->indio_trig);
1416                 if (ret)
1417                         break;
1418         }
1419
1420         if (ret)
1421                 bmc150_accel_unregister_triggers(data, i - 1);
1422
1423         return ret;
1424 }
1425
1426 #define BMC150_ACCEL_FIFO_MODE_STREAM          0x80
1427 #define BMC150_ACCEL_FIFO_MODE_FIFO            0x40
1428 #define BMC150_ACCEL_FIFO_MODE_BYPASS          0x00
1429
1430 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1431 {
1432         u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1433         int ret;
1434
1435         ret = i2c_smbus_write_byte_data(data->client, reg, data->fifo_mode);
1436         if (ret < 0) {
1437                 dev_err(&data->client->dev, "Error writing reg_fifo_config1\n");
1438                 return ret;
1439         }
1440
1441         if (!data->fifo_mode)
1442                 return 0;
1443
1444         ret = i2c_smbus_write_byte_data(data->client,
1445                                         BMC150_ACCEL_REG_FIFO_CONFIG0,
1446                                         data->watermark);
1447         if (ret < 0)
1448                 dev_err(&data->client->dev, "Error writing reg_fifo_config0\n");
1449
1450         return ret;
1451 }
1452
1453 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1454 {
1455         struct bmc150_accel_data *data = iio_priv(indio_dev);
1456
1457         return bmc150_accel_set_power_state(data, true);
1458 }
1459
1460 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1461 {
1462         struct bmc150_accel_data *data = iio_priv(indio_dev);
1463         int ret = 0;
1464
1465         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1466                 return iio_triggered_buffer_postenable(indio_dev);
1467
1468         mutex_lock(&data->mutex);
1469
1470         if (!data->watermark)
1471                 goto out;
1472
1473         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1474                                          true);
1475         if (ret)
1476                 goto out;
1477
1478         data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1479
1480         ret = bmc150_accel_fifo_set_mode(data);
1481         if (ret) {
1482                 data->fifo_mode = 0;
1483                 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1484                                            false);
1485         }
1486
1487 out:
1488         mutex_unlock(&data->mutex);
1489
1490         return ret;
1491 }
1492
1493 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1494 {
1495         struct bmc150_accel_data *data = iio_priv(indio_dev);
1496
1497         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1498                 return iio_triggered_buffer_predisable(indio_dev);
1499
1500         mutex_lock(&data->mutex);
1501
1502         if (!data->fifo_mode)
1503                 goto out;
1504
1505         bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1506         __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1507         data->fifo_mode = 0;
1508         bmc150_accel_fifo_set_mode(data);
1509
1510 out:
1511         mutex_unlock(&data->mutex);
1512
1513         return 0;
1514 }
1515
1516 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1517 {
1518         struct bmc150_accel_data *data = iio_priv(indio_dev);
1519
1520         return bmc150_accel_set_power_state(data, false);
1521 }
1522
1523 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1524         .preenable = bmc150_accel_buffer_preenable,
1525         .postenable = bmc150_accel_buffer_postenable,
1526         .predisable = bmc150_accel_buffer_predisable,
1527         .postdisable = bmc150_accel_buffer_postdisable,
1528 };
1529
1530 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1531 {
1532         int ret, i;
1533
1534         ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_CHIP_ID);
1535         if (ret < 0) {
1536                 dev_err(&data->client->dev, "Error: Reading chip id\n");
1537                 return ret;
1538         }
1539
1540         dev_dbg(&data->client->dev, "Chip Id %x\n", ret);
1541         for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1542                 if (bmc150_accel_chip_info_tbl[i].chip_id == ret) {
1543                         data->chip_info = &bmc150_accel_chip_info_tbl[i];
1544                         break;
1545                 }
1546         }
1547
1548         if (!data->chip_info) {
1549                 dev_err(&data->client->dev, "Unsupported chip %x\n", ret);
1550                 return -ENODEV;
1551         }
1552
1553         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1554         if (ret < 0)
1555                 return ret;
1556
1557         /* Set Bandwidth */
1558         ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1559         if (ret < 0)
1560                 return ret;
1561
1562         /* Set Default Range */
1563         ret = i2c_smbus_write_byte_data(data->client,
1564                                         BMC150_ACCEL_REG_PMU_RANGE,
1565                                         BMC150_ACCEL_DEF_RANGE_4G);
1566         if (ret < 0) {
1567                 dev_err(&data->client->dev, "Error writing reg_pmu_range\n");
1568                 return ret;
1569         }
1570
1571         data->range = BMC150_ACCEL_DEF_RANGE_4G;
1572
1573         /* Set default slope duration and thresholds */
1574         data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1575         data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1576         ret = bmc150_accel_update_slope(data);
1577         if (ret < 0)
1578                 return ret;
1579
1580         /* Set default as latched interrupts */
1581         ret = i2c_smbus_write_byte_data(data->client,
1582                                         BMC150_ACCEL_REG_INT_RST_LATCH,
1583                                         BMC150_ACCEL_INT_MODE_LATCH_INT |
1584                                         BMC150_ACCEL_INT_MODE_LATCH_RESET);
1585         if (ret < 0) {
1586                 dev_err(&data->client->dev,
1587                         "Error writing reg_int_rst_latch\n");
1588                 return ret;
1589         }
1590
1591         return 0;
1592 }
1593
1594 static int bmc150_accel_probe(struct i2c_client *client,
1595                               const struct i2c_device_id *id)
1596 {
1597         struct bmc150_accel_data *data;
1598         struct iio_dev *indio_dev;
1599         int ret;
1600         const char *name = NULL;
1601
1602         indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1603         if (!indio_dev)
1604                 return -ENOMEM;
1605
1606         data = iio_priv(indio_dev);
1607         i2c_set_clientdata(client, indio_dev);
1608         data->client = client;
1609
1610         if (id)
1611                 name = id->name;
1612
1613         ret = bmc150_accel_chip_init(data);
1614         if (ret < 0)
1615                 return ret;
1616
1617         mutex_init(&data->mutex);
1618
1619         indio_dev->dev.parent = &client->dev;
1620         indio_dev->channels = data->chip_info->channels;
1621         indio_dev->num_channels = data->chip_info->num_channels;
1622         indio_dev->name = name ? name : data->chip_info->name;
1623         indio_dev->modes = INDIO_DIRECT_MODE;
1624         indio_dev->info = &bmc150_accel_info;
1625
1626         ret = iio_triggered_buffer_setup(indio_dev,
1627                                          &iio_pollfunc_store_time,
1628                                          bmc150_accel_trigger_handler,
1629                                          &bmc150_accel_buffer_ops);
1630         if (ret < 0) {
1631                 dev_err(&client->dev, "Failed: iio triggered buffer setup\n");
1632                 return ret;
1633         }
1634
1635         if (client->irq > 0) {
1636                 ret = devm_request_threaded_irq(
1637                                                 &client->dev, client->irq,
1638                                                 bmc150_accel_irq_handler,
1639                                                 bmc150_accel_irq_thread_handler,
1640                                                 IRQF_TRIGGER_RISING,
1641                                                 BMC150_ACCEL_IRQ_NAME,
1642                                                 indio_dev);
1643                 if (ret)
1644                         goto err_buffer_cleanup;
1645
1646                 /*
1647                  * Set latched mode interrupt. While certain interrupts are
1648                  * non-latched regardless of this settings (e.g. new data) we
1649                  * want to use latch mode when we can to prevent interrupt
1650                  * flooding.
1651                  */
1652                 ret = i2c_smbus_write_byte_data(data->client,
1653                                                 BMC150_ACCEL_REG_INT_RST_LATCH,
1654                                              BMC150_ACCEL_INT_MODE_LATCH_RESET);
1655                 if (ret < 0) {
1656                         dev_err(&data->client->dev, "Error writing reg_int_rst_latch\n");
1657                         goto err_buffer_cleanup;
1658                 }
1659
1660                 bmc150_accel_interrupts_setup(indio_dev, data);
1661
1662                 ret = bmc150_accel_triggers_setup(indio_dev, data);
1663                 if (ret)
1664                         goto err_buffer_cleanup;
1665
1666                 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) ||
1667                     i2c_check_functionality(client->adapter,
1668                                             I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
1669                         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1670                         indio_dev->info = &bmc150_accel_info_fifo;
1671                         indio_dev->buffer->attrs = bmc150_accel_fifo_attributes;
1672                 }
1673         }
1674
1675         ret = iio_device_register(indio_dev);
1676         if (ret < 0) {
1677                 dev_err(&client->dev, "Unable to register iio device\n");
1678                 goto err_trigger_unregister;
1679         }
1680
1681         ret = pm_runtime_set_active(&client->dev);
1682         if (ret)
1683                 goto err_iio_unregister;
1684
1685         pm_runtime_enable(&client->dev);
1686         pm_runtime_set_autosuspend_delay(&client->dev,
1687                                          BMC150_AUTO_SUSPEND_DELAY_MS);
1688         pm_runtime_use_autosuspend(&client->dev);
1689
1690         return 0;
1691
1692 err_iio_unregister:
1693         iio_device_unregister(indio_dev);
1694 err_trigger_unregister:
1695         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1696 err_buffer_cleanup:
1697         iio_triggered_buffer_cleanup(indio_dev);
1698
1699         return ret;
1700 }
1701
1702 static int bmc150_accel_remove(struct i2c_client *client)
1703 {
1704         struct iio_dev *indio_dev = i2c_get_clientdata(client);
1705         struct bmc150_accel_data *data = iio_priv(indio_dev);
1706
1707         pm_runtime_disable(&client->dev);
1708         pm_runtime_set_suspended(&client->dev);
1709         pm_runtime_put_noidle(&client->dev);
1710
1711         iio_device_unregister(indio_dev);
1712
1713         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1714
1715         iio_triggered_buffer_cleanup(indio_dev);
1716
1717         mutex_lock(&data->mutex);
1718         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1719         mutex_unlock(&data->mutex);
1720
1721         return 0;
1722 }
1723
1724 #ifdef CONFIG_PM_SLEEP
1725 static int bmc150_accel_suspend(struct device *dev)
1726 {
1727         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1728         struct bmc150_accel_data *data = iio_priv(indio_dev);
1729
1730         mutex_lock(&data->mutex);
1731         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1732         mutex_unlock(&data->mutex);
1733
1734         return 0;
1735 }
1736
1737 static int bmc150_accel_resume(struct device *dev)
1738 {
1739         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1740         struct bmc150_accel_data *data = iio_priv(indio_dev);
1741
1742         mutex_lock(&data->mutex);
1743         if (atomic_read(&data->active_intr))
1744                 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1745         bmc150_accel_fifo_set_mode(data);
1746         mutex_unlock(&data->mutex);
1747
1748         return 0;
1749 }
1750 #endif
1751
1752 #ifdef CONFIG_PM
1753 static int bmc150_accel_runtime_suspend(struct device *dev)
1754 {
1755         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1756         struct bmc150_accel_data *data = iio_priv(indio_dev);
1757         int ret;
1758
1759         dev_dbg(&data->client->dev,  __func__);
1760         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1761         if (ret < 0)
1762                 return -EAGAIN;
1763
1764         return 0;
1765 }
1766
1767 static int bmc150_accel_runtime_resume(struct device *dev)
1768 {
1769         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1770         struct bmc150_accel_data *data = iio_priv(indio_dev);
1771         int ret;
1772         int sleep_val;
1773
1774         dev_dbg(&data->client->dev,  __func__);
1775
1776         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1777         if (ret < 0)
1778                 return ret;
1779         ret = bmc150_accel_fifo_set_mode(data);
1780         if (ret < 0)
1781                 return ret;
1782
1783         sleep_val = bmc150_accel_get_startup_times(data);
1784         if (sleep_val < 20)
1785                 usleep_range(sleep_val * 1000, 20000);
1786         else
1787                 msleep_interruptible(sleep_val);
1788
1789         return 0;
1790 }
1791 #endif
1792
1793 static const struct dev_pm_ops bmc150_accel_pm_ops = {
1794         SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1795         SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1796                            bmc150_accel_runtime_resume, NULL)
1797 };
1798
1799 static const struct acpi_device_id bmc150_accel_acpi_match[] = {
1800         {"BSBA0150",    bmc150},
1801         {"BMC150A",     bmc150},
1802         {"BMI055A",     bmi055},
1803         {"BMA0255",     bma255},
1804         {"BMA250E",     bma250e},
1805         {"BMA222E",     bma222e},
1806         {"BMA0280",     bma280},
1807         { },
1808 };
1809 MODULE_DEVICE_TABLE(acpi, bmc150_accel_acpi_match);
1810
1811 static const struct i2c_device_id bmc150_accel_id[] = {
1812         {"bmc150_accel",        bmc150},
1813         {"bmi055_accel",        bmi055},
1814         {"bma255",              bma255},
1815         {"bma250e",             bma250e},
1816         {"bma222e",             bma222e},
1817         {"bma280",              bma280},
1818         {}
1819 };
1820
1821 MODULE_DEVICE_TABLE(i2c, bmc150_accel_id);
1822
1823 static struct i2c_driver bmc150_accel_driver = {
1824         .driver = {
1825                 .name   = BMC150_ACCEL_DRV_NAME,
1826                 .acpi_match_table = ACPI_PTR(bmc150_accel_acpi_match),
1827                 .pm     = &bmc150_accel_pm_ops,
1828         },
1829         .probe          = bmc150_accel_probe,
1830         .remove         = bmc150_accel_remove,
1831         .id_table       = bmc150_accel_id,
1832 };
1833 module_i2c_driver(bmc150_accel_driver);
1834
1835 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1836 MODULE_LICENSE("GPL v2");
1837 MODULE_DESCRIPTION("BMC150 accelerometer driver");