2 * mma8452.c - Support for Freescale MMA8452Q 3-axis 12-bit accelerometer
4 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
6 * This file is subject to the terms and conditions of version 2 of
7 * the GNU General Public License. See the file COPYING in the main
8 * directory of this archive for more details.
10 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
12 * TODO: orientation / freefall events, autosleep
15 #include <linux/module.h>
16 #include <linux/i2c.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/sysfs.h>
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/trigger.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/triggered_buffer.h>
23 #include <linux/iio/events.h>
24 #include <linux/delay.h>
25 #include <linux/of_device.h>
27 #define MMA8452_STATUS 0x00
28 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
29 #define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */
30 #define MMA8452_OUT_Y 0x03
31 #define MMA8452_OUT_Z 0x05
32 #define MMA8452_INT_SRC 0x0c
33 #define MMA8452_WHO_AM_I 0x0d
34 #define MMA8452_DATA_CFG 0x0e
35 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
36 #define MMA8452_DATA_CFG_FS_2G 0
37 #define MMA8452_DATA_CFG_FS_4G 1
38 #define MMA8452_DATA_CFG_FS_8G 2
39 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
40 #define MMA8452_HP_FILTER_CUTOFF 0x0f
41 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
42 #define MMA8452_TRANSIENT_CFG 0x1d
43 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
44 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
45 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
46 #define MMA8452_TRANSIENT_SRC 0x1e
47 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
48 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
49 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
50 #define MMA8452_TRANSIENT_THS 0x1f
51 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
52 #define MMA8452_TRANSIENT_COUNT 0x20
53 #define MMA8452_CTRL_REG1 0x2a
54 #define MMA8452_CTRL_ACTIVE BIT(0)
55 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
56 #define MMA8452_CTRL_DR_SHIFT 3
57 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
58 #define MMA8452_CTRL_REG2 0x2b
59 #define MMA8452_CTRL_REG2_RST BIT(6)
60 #define MMA8452_CTRL_REG4 0x2d
61 #define MMA8452_CTRL_REG5 0x2e
62 #define MMA8452_OFF_X 0x2f
63 #define MMA8452_OFF_Y 0x30
64 #define MMA8452_OFF_Z 0x31
66 #define MMA8452_MAX_REG 0x31
68 #define MMA8452_INT_DRDY BIT(0)
69 #define MMA8452_INT_TRANS BIT(5)
71 #define MMA8452_DEVICE_ID 0x2a
74 struct i2c_client *client;
78 const struct mma_chip_info *chip_info;
82 * struct mma_chip_info - chip specific data for Freescale's accelerometers
83 * @chip_id: WHO_AM_I register's value
84 * @channels: struct iio_chan_spec matching the device's
86 * @num_channels: number of channels
87 * @mma_scales: scale factors for converting register values
88 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
89 * per mode: m/s^2 and micro m/s^2
90 * @ev_cfg: event config register address
91 * @ev_cfg_ele: latch bit in event config register
92 * @ev_cfg_chan_shift: number of the bit to enable events in X
93 * direction; in event config register
94 * @ev_src: event source register address
95 * @ev_src_xe: bit in event source register that indicates
96 * an event in X direction
97 * @ev_src_ye: bit in event source register that indicates
98 * an event in Y direction
99 * @ev_src_ze: bit in event source register that indicates
100 * an event in Z direction
101 * @ev_ths: event threshold register address
102 * @ev_ths_mask: mask for the threshold value
103 * @ev_count: event count (period) register address
105 * Since not all chips supported by the driver support comparing high pass
106 * filtered data for events (interrupts), different interrupt sources are
107 * used for different chips and the relevant registers are included here.
109 struct mma_chip_info {
111 const struct iio_chan_spec *channels;
113 const int mma_scales[3][2];
116 u8 ev_cfg_chan_shift;
126 static int mma8452_drdy(struct mma8452_data *data)
130 while (tries-- > 0) {
131 int ret = i2c_smbus_read_byte_data(data->client,
135 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
141 dev_err(&data->client->dev, "data not ready\n");
146 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
148 int ret = mma8452_drdy(data);
153 return i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
154 3 * sizeof(__be16), (u8 *)buf);
157 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
163 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
164 vals[n][0], vals[n][1]);
166 /* replace trailing space by newline */
172 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
176 if (val == vals[n][0] && val2 == vals[n][1])
182 static int mma8452_get_odr_index(struct mma8452_data *data)
184 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
185 MMA8452_CTRL_DR_SHIFT;
188 static const int mma8452_samp_freq[8][2] = {
189 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
190 {6, 250000}, {1, 560000}
193 /* Datasheet table 35 (step time vs sample frequency) */
194 static const int mma8452_transient_time_step_us[8] = {
205 /* Datasheet table 18 (normal mode) */
206 static const int mma8452_hp_filter_cutoff[8][4][2] = {
207 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
208 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
209 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
210 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
211 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
212 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
213 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
214 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
217 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
218 struct device_attribute *attr,
221 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
222 ARRAY_SIZE(mma8452_samp_freq));
225 static ssize_t mma8452_show_scale_avail(struct device *dev,
226 struct device_attribute *attr,
229 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
230 to_i2c_client(dev)));
232 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
233 ARRAY_SIZE(data->chip_info->mma_scales));
236 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
237 struct device_attribute *attr,
240 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
241 struct mma8452_data *data = iio_priv(indio_dev);
242 int i = mma8452_get_odr_index(data);
244 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
245 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
248 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
249 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
250 mma8452_show_scale_avail, NULL, 0);
251 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
252 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
254 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
257 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
258 ARRAY_SIZE(mma8452_samp_freq),
262 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
264 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
265 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
268 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
271 int i = mma8452_get_odr_index(data);
273 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
274 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
277 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
281 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
285 i = mma8452_get_odr_index(data);
286 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
287 *hz = mma8452_hp_filter_cutoff[i][ret][0];
288 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
293 static int mma8452_read_raw(struct iio_dev *indio_dev,
294 struct iio_chan_spec const *chan,
295 int *val, int *val2, long mask)
297 struct mma8452_data *data = iio_priv(indio_dev);
302 case IIO_CHAN_INFO_RAW:
303 if (iio_buffer_enabled(indio_dev))
306 mutex_lock(&data->lock);
307 ret = mma8452_read(data, buffer);
308 mutex_unlock(&data->lock);
312 *val = sign_extend32(be16_to_cpu(
313 buffer[chan->scan_index]) >> chan->scan_type.shift,
314 chan->scan_type.realbits - 1);
317 case IIO_CHAN_INFO_SCALE:
318 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
319 *val = data->chip_info->mma_scales[i][0];
320 *val2 = data->chip_info->mma_scales[i][1];
322 return IIO_VAL_INT_PLUS_MICRO;
323 case IIO_CHAN_INFO_SAMP_FREQ:
324 i = mma8452_get_odr_index(data);
325 *val = mma8452_samp_freq[i][0];
326 *val2 = mma8452_samp_freq[i][1];
328 return IIO_VAL_INT_PLUS_MICRO;
329 case IIO_CHAN_INFO_CALIBBIAS:
330 ret = i2c_smbus_read_byte_data(data->client,
331 MMA8452_OFF_X + chan->scan_index);
335 *val = sign_extend32(ret, 7);
338 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
339 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
340 ret = mma8452_read_hp_filter(data, val, val2);
348 return IIO_VAL_INT_PLUS_MICRO;
354 static int mma8452_standby(struct mma8452_data *data)
356 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
357 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
360 static int mma8452_active(struct mma8452_data *data)
362 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
366 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
370 mutex_lock(&data->lock);
372 /* config can only be changed when in standby */
373 ret = mma8452_standby(data);
377 ret = i2c_smbus_write_byte_data(data->client, reg, val);
381 ret = mma8452_active(data);
387 mutex_unlock(&data->lock);
392 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
397 i = mma8452_get_hp_filter_index(data, val, val2);
401 reg = i2c_smbus_read_byte_data(data->client,
402 MMA8452_HP_FILTER_CUTOFF);
406 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
409 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
412 static int mma8452_write_raw(struct iio_dev *indio_dev,
413 struct iio_chan_spec const *chan,
414 int val, int val2, long mask)
416 struct mma8452_data *data = iio_priv(indio_dev);
419 if (iio_buffer_enabled(indio_dev))
423 case IIO_CHAN_INFO_SAMP_FREQ:
424 i = mma8452_get_samp_freq_index(data, val, val2);
428 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
429 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
431 return mma8452_change_config(data, MMA8452_CTRL_REG1,
433 case IIO_CHAN_INFO_SCALE:
434 i = mma8452_get_scale_index(data, val, val2);
438 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
441 return mma8452_change_config(data, MMA8452_DATA_CFG,
443 case IIO_CHAN_INFO_CALIBBIAS:
444 if (val < -128 || val > 127)
447 return mma8452_change_config(data,
448 MMA8452_OFF_X + chan->scan_index,
451 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
452 if (val == 0 && val2 == 0) {
453 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
455 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
456 ret = mma8452_set_hp_filter_frequency(data, val, val2);
461 return mma8452_change_config(data, MMA8452_DATA_CFG,
469 static int mma8452_read_thresh(struct iio_dev *indio_dev,
470 const struct iio_chan_spec *chan,
471 enum iio_event_type type,
472 enum iio_event_direction dir,
473 enum iio_event_info info,
476 struct mma8452_data *data = iio_priv(indio_dev);
480 case IIO_EV_INFO_VALUE:
481 ret = i2c_smbus_read_byte_data(data->client,
482 data->chip_info->ev_ths);
486 *val = ret & data->chip_info->ev_ths_mask;
490 case IIO_EV_INFO_PERIOD:
491 ret = i2c_smbus_read_byte_data(data->client,
492 data->chip_info->ev_count);
496 us = ret * mma8452_transient_time_step_us[
497 mma8452_get_odr_index(data)];
498 *val = us / USEC_PER_SEC;
499 *val2 = us % USEC_PER_SEC;
501 return IIO_VAL_INT_PLUS_MICRO;
503 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
504 ret = i2c_smbus_read_byte_data(data->client,
505 MMA8452_TRANSIENT_CFG);
509 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
513 ret = mma8452_read_hp_filter(data, val, val2);
518 return IIO_VAL_INT_PLUS_MICRO;
525 static int mma8452_write_thresh(struct iio_dev *indio_dev,
526 const struct iio_chan_spec *chan,
527 enum iio_event_type type,
528 enum iio_event_direction dir,
529 enum iio_event_info info,
532 struct mma8452_data *data = iio_priv(indio_dev);
536 case IIO_EV_INFO_VALUE:
537 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
540 return mma8452_change_config(data, data->chip_info->ev_ths,
543 case IIO_EV_INFO_PERIOD:
544 steps = (val * USEC_PER_SEC + val2) /
545 mma8452_transient_time_step_us[
546 mma8452_get_odr_index(data)];
548 if (steps < 0 || steps > 0xff)
551 return mma8452_change_config(data, data->chip_info->ev_count,
554 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
555 reg = i2c_smbus_read_byte_data(data->client,
556 MMA8452_TRANSIENT_CFG);
560 if (val == 0 && val2 == 0) {
561 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
563 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
564 ret = mma8452_set_hp_filter_frequency(data, val, val2);
569 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
576 static int mma8452_read_event_config(struct iio_dev *indio_dev,
577 const struct iio_chan_spec *chan,
578 enum iio_event_type type,
579 enum iio_event_direction dir)
581 struct mma8452_data *data = iio_priv(indio_dev);
582 const struct mma_chip_info *chip = data->chip_info;
585 ret = i2c_smbus_read_byte_data(data->client,
586 data->chip_info->ev_cfg);
590 return !!(ret & BIT(chan->scan_index + chip->ev_cfg_chan_shift));
593 static int mma8452_write_event_config(struct iio_dev *indio_dev,
594 const struct iio_chan_spec *chan,
595 enum iio_event_type type,
596 enum iio_event_direction dir,
599 struct mma8452_data *data = iio_priv(indio_dev);
600 const struct mma_chip_info *chip = data->chip_info;
603 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
608 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
610 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
612 val |= MMA8452_TRANSIENT_CFG_ELE;
614 return mma8452_change_config(data, chip->ev_cfg, val);
617 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
619 struct mma8452_data *data = iio_priv(indio_dev);
620 s64 ts = iio_get_time_ns();
623 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
627 if (src & data->chip_info->ev_src_xe)
628 iio_push_event(indio_dev,
629 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
634 if (src & data->chip_info->ev_src_ye)
635 iio_push_event(indio_dev,
636 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
641 if (src & data->chip_info->ev_src_ze)
642 iio_push_event(indio_dev,
643 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
649 static irqreturn_t mma8452_interrupt(int irq, void *p)
651 struct iio_dev *indio_dev = p;
652 struct mma8452_data *data = iio_priv(indio_dev);
656 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
660 if (src & MMA8452_INT_DRDY) {
661 iio_trigger_poll_chained(indio_dev->trig);
665 if (src & MMA8452_INT_TRANS) {
666 mma8452_transient_interrupt(indio_dev);
673 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
675 struct iio_poll_func *pf = p;
676 struct iio_dev *indio_dev = pf->indio_dev;
677 struct mma8452_data *data = iio_priv(indio_dev);
678 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
681 ret = mma8452_read(data, (__be16 *)buffer);
685 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
689 iio_trigger_notify_done(indio_dev->trig);
694 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
695 unsigned reg, unsigned writeval,
699 struct mma8452_data *data = iio_priv(indio_dev);
701 if (reg > MMA8452_MAX_REG)
705 return mma8452_change_config(data, reg, writeval);
707 ret = i2c_smbus_read_byte_data(data->client, reg);
716 static const struct iio_event_spec mma8452_transient_event[] = {
718 .type = IIO_EV_TYPE_MAG,
719 .dir = IIO_EV_DIR_RISING,
720 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
721 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
722 BIT(IIO_EV_INFO_PERIOD) |
723 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
728 * Threshold is configured in fixed 8G/127 steps regardless of
729 * currently selected scale for measurement.
731 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
733 static struct attribute *mma8452_event_attributes[] = {
734 &iio_const_attr_accel_transient_scale.dev_attr.attr,
738 static struct attribute_group mma8452_event_attribute_group = {
739 .attrs = mma8452_event_attributes,
743 #define MMA8452_CHANNEL(axis, idx, bits) { \
746 .channel2 = IIO_MOD_##axis, \
747 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
748 BIT(IIO_CHAN_INFO_CALIBBIAS), \
749 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
750 BIT(IIO_CHAN_INFO_SCALE) | \
751 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
755 .realbits = (bits), \
757 .shift = 16 - (bits), \
758 .endianness = IIO_BE, \
760 .event_spec = mma8452_transient_event, \
761 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
764 static const struct iio_chan_spec mma8452_channels[] = {
765 MMA8452_CHANNEL(X, 0, 12),
766 MMA8452_CHANNEL(Y, 1, 12),
767 MMA8452_CHANNEL(Z, 2, 12),
768 IIO_CHAN_SOFT_TIMESTAMP(3),
775 static const struct mma_chip_info mma_chip_info_table[] = {
777 .chip_id = MMA8452_DEVICE_ID,
778 .channels = mma8452_channels,
779 .num_channels = ARRAY_SIZE(mma8452_channels),
781 * Hardware has fullscale of -2G, -4G, -8G corresponding to
782 * raw value -2048 for 12 bit or -512 for 10 bit.
783 * The userspace interface uses m/s^2 and we declare micro units
784 * So scale factor for 12 bit here is given by:
785 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
787 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
788 .ev_cfg = MMA8452_TRANSIENT_CFG,
789 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
790 .ev_cfg_chan_shift = 1,
791 .ev_src = MMA8452_TRANSIENT_SRC,
792 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
793 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
794 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
795 .ev_ths = MMA8452_TRANSIENT_THS,
796 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
797 .ev_count = MMA8452_TRANSIENT_COUNT,
801 static struct attribute *mma8452_attributes[] = {
802 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
803 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
804 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
808 static const struct attribute_group mma8452_group = {
809 .attrs = mma8452_attributes,
812 static const struct iio_info mma8452_info = {
813 .attrs = &mma8452_group,
814 .read_raw = &mma8452_read_raw,
815 .write_raw = &mma8452_write_raw,
816 .event_attrs = &mma8452_event_attribute_group,
817 .read_event_value = &mma8452_read_thresh,
818 .write_event_value = &mma8452_write_thresh,
819 .read_event_config = &mma8452_read_event_config,
820 .write_event_config = &mma8452_write_event_config,
821 .debugfs_reg_access = &mma8452_reg_access_dbg,
822 .driver_module = THIS_MODULE,
825 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
827 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
830 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
831 struct mma8452_data *data = iio_priv(indio_dev);
834 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
839 reg |= MMA8452_INT_DRDY;
841 reg &= ~MMA8452_INT_DRDY;
843 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
846 static int mma8452_validate_device(struct iio_trigger *trig,
847 struct iio_dev *indio_dev)
849 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
851 if (indio != indio_dev)
857 static const struct iio_trigger_ops mma8452_trigger_ops = {
858 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
859 .validate_device = mma8452_validate_device,
860 .owner = THIS_MODULE,
863 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
865 struct mma8452_data *data = iio_priv(indio_dev);
866 struct iio_trigger *trig;
869 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
875 trig->dev.parent = &data->client->dev;
876 trig->ops = &mma8452_trigger_ops;
877 iio_trigger_set_drvdata(trig, indio_dev);
879 ret = iio_trigger_register(trig);
883 indio_dev->trig = trig;
888 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
891 iio_trigger_unregister(indio_dev->trig);
894 static int mma8452_reset(struct i2c_client *client)
899 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
900 MMA8452_CTRL_REG2_RST);
904 for (i = 0; i < 10; i++) {
905 usleep_range(100, 200);
906 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
908 continue; /* I2C comm reset */
911 if (!(ret & MMA8452_CTRL_REG2_RST))
918 static const struct of_device_id mma8452_dt_ids[] = {
919 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
922 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
924 static int mma8452_probe(struct i2c_client *client,
925 const struct i2c_device_id *id)
927 struct mma8452_data *data;
928 struct iio_dev *indio_dev;
930 const struct of_device_id *match;
932 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
935 if (ret != MMA8452_DEVICE_ID)
938 match = of_match_device(mma8452_dt_ids, &client->dev);
940 dev_err(&client->dev, "unknown device model\n");
944 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
948 data = iio_priv(indio_dev);
949 data->client = client;
950 mutex_init(&data->lock);
951 data->chip_info = match->data;
953 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
954 match->compatible, data->chip_info->chip_id);
956 i2c_set_clientdata(client, indio_dev);
957 indio_dev->info = &mma8452_info;
958 indio_dev->name = id->name;
959 indio_dev->dev.parent = &client->dev;
960 indio_dev->modes = INDIO_DIRECT_MODE;
961 indio_dev->channels = data->chip_info->channels;
962 indio_dev->num_channels = data->chip_info->num_channels;
963 indio_dev->available_scan_masks = mma8452_scan_masks;
965 ret = mma8452_reset(client);
969 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
970 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
976 * By default set transient threshold to max to avoid events if
977 * enabling without configuring threshold.
979 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
980 MMA8452_TRANSIENT_THS_MASK);
986 * Although we enable the transient interrupt source once and
987 * for all here the transient event detection itself is not
988 * enabled until userspace asks for it by
989 * mma8452_write_event_config()
991 int supported_interrupts = MMA8452_INT_DRDY | MMA8452_INT_TRANS;
992 int enabled_interrupts = MMA8452_INT_TRANS;
994 /* Assume wired to INT1 pin */
995 ret = i2c_smbus_write_byte_data(client,
997 supported_interrupts);
1001 ret = i2c_smbus_write_byte_data(client,
1003 enabled_interrupts);
1007 ret = mma8452_trigger_setup(indio_dev);
1012 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1013 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1014 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1017 goto trigger_cleanup;
1019 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1020 mma8452_trigger_handler, NULL);
1022 goto trigger_cleanup;
1025 ret = devm_request_threaded_irq(&client->dev,
1027 NULL, mma8452_interrupt,
1028 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1029 client->name, indio_dev);
1031 goto buffer_cleanup;
1034 ret = iio_device_register(indio_dev);
1036 goto buffer_cleanup;
1041 iio_triggered_buffer_cleanup(indio_dev);
1044 mma8452_trigger_cleanup(indio_dev);
1049 static int mma8452_remove(struct i2c_client *client)
1051 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1053 iio_device_unregister(indio_dev);
1054 iio_triggered_buffer_cleanup(indio_dev);
1055 mma8452_trigger_cleanup(indio_dev);
1056 mma8452_standby(iio_priv(indio_dev));
1061 #ifdef CONFIG_PM_SLEEP
1062 static int mma8452_suspend(struct device *dev)
1064 return mma8452_standby(iio_priv(i2c_get_clientdata(
1065 to_i2c_client(dev))));
1068 static int mma8452_resume(struct device *dev)
1070 return mma8452_active(iio_priv(i2c_get_clientdata(
1071 to_i2c_client(dev))));
1074 static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
1075 #define MMA8452_PM_OPS (&mma8452_pm_ops)
1077 #define MMA8452_PM_OPS NULL
1080 static const struct i2c_device_id mma8452_id[] = {
1081 { "mma8452", mma8452 },
1084 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1086 static struct i2c_driver mma8452_driver = {
1089 .of_match_table = of_match_ptr(mma8452_dt_ids),
1090 .pm = MMA8452_PM_OPS,
1092 .probe = mma8452_probe,
1093 .remove = mma8452_remove,
1094 .id_table = mma8452_id,
1096 module_i2c_driver(mma8452_driver);
1098 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1099 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
1100 MODULE_LICENSE("GPL");