2 * 3-axis accelerometer driver for MXC4005XC Memsic sensor
4 * Copyright (c) 2014, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/module.h>
17 #include <linux/i2c.h>
18 #include <linux/iio/iio.h>
19 #include <linux/acpi.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/regmap.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/triggered_buffer.h>
26 #include <linux/iio/trigger_consumer.h>
28 #define MXC4005_DRV_NAME "mxc4005"
29 #define MXC4005_IRQ_NAME "mxc4005_event"
30 #define MXC4005_REGMAP_NAME "mxc4005_regmap"
32 #define MXC4005_REG_XOUT_UPPER 0x03
33 #define MXC4005_REG_XOUT_LOWER 0x04
34 #define MXC4005_REG_YOUT_UPPER 0x05
35 #define MXC4005_REG_YOUT_LOWER 0x06
36 #define MXC4005_REG_ZOUT_UPPER 0x07
37 #define MXC4005_REG_ZOUT_LOWER 0x08
39 #define MXC4005_REG_INT_MASK1 0x0B
40 #define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01
42 #define MXC4005_REG_INT_CLR1 0x01
43 #define MXC4005_REG_INT_CLR1_BIT_DRDYC 0x01
45 #define MXC4005_REG_CONTROL 0x0D
46 #define MXC4005_REG_CONTROL_MASK_FSR GENMASK(6, 5)
47 #define MXC4005_CONTROL_FSR_SHIFT 5
49 #define MXC4005_REG_DEVICE_ID 0x0E
66 struct regmap *regmap;
67 struct iio_trigger *dready_trig;
73 * MXC4005 can operate in the following ranges:
74 * +/- 2G, 4G, 8G (the default +/-2G)
76 * (2 + 2) * 9.81 / (2^12 - 1) = 0.009582
77 * (4 + 4) * 9.81 / (2^12 - 1) = 0.019164
78 * (8 + 8) * 9.81 / (2^12 - 1) = 0.038329
83 } mxc4005_scale_table[] = {
84 {MXC4005_RANGE_2G, 9582},
85 {MXC4005_RANGE_4G, 19164},
86 {MXC4005_RANGE_8G, 38329},
90 static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329");
92 static struct attribute *mxc4005_attributes[] = {
93 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
97 static const struct attribute_group mxc4005_attrs_group = {
98 .attrs = mxc4005_attributes,
101 static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg)
104 case MXC4005_REG_XOUT_UPPER:
105 case MXC4005_REG_XOUT_LOWER:
106 case MXC4005_REG_YOUT_UPPER:
107 case MXC4005_REG_YOUT_LOWER:
108 case MXC4005_REG_ZOUT_UPPER:
109 case MXC4005_REG_ZOUT_LOWER:
110 case MXC4005_REG_DEVICE_ID:
111 case MXC4005_REG_CONTROL:
118 static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
121 case MXC4005_REG_INT_CLR1:
122 case MXC4005_REG_INT_MASK1:
123 case MXC4005_REG_CONTROL:
130 static const struct regmap_config mxc4005_regmap_config = {
131 .name = MXC4005_REGMAP_NAME,
136 .max_register = MXC4005_REG_DEVICE_ID,
138 .readable_reg = mxc4005_is_readable_reg,
139 .writeable_reg = mxc4005_is_writeable_reg,
142 static int mxc4005_read_xyz(struct mxc4005_data *data)
146 ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER,
147 (u8 *) data->buffer, sizeof(data->buffer));
149 dev_err(data->dev, "failed to read axes\n");
156 static int mxc4005_read_axis(struct mxc4005_data *data,
162 ret = regmap_bulk_read(data->regmap, addr, (u8 *) ®, sizeof(reg));
164 dev_err(data->dev, "failed to read reg %02x\n", addr);
168 return be16_to_cpu(reg);
171 static int mxc4005_read_scale(struct mxc4005_data *data)
177 ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, ®);
179 dev_err(data->dev, "failed to read reg_control\n");
183 i = reg >> MXC4005_CONTROL_FSR_SHIFT;
185 if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table))
188 return mxc4005_scale_table[i].scale;
191 static int mxc4005_set_scale(struct mxc4005_data *data, int val)
197 for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) {
198 if (mxc4005_scale_table[i].scale == val) {
199 reg = i << MXC4005_CONTROL_FSR_SHIFT;
200 ret = regmap_update_bits(data->regmap,
202 MXC4005_REG_CONTROL_MASK_FSR,
206 "failed to write reg_control\n");
214 static int mxc4005_read_raw(struct iio_dev *indio_dev,
215 struct iio_chan_spec const *chan,
216 int *val, int *val2, long mask)
218 struct mxc4005_data *data = iio_priv(indio_dev);
222 case IIO_CHAN_INFO_RAW:
223 switch (chan->type) {
225 if (iio_buffer_enabled(indio_dev))
228 ret = mxc4005_read_axis(data, chan->address);
231 *val = sign_extend32(ret >> chan->scan_type.shift,
232 chan->scan_type.realbits - 1);
237 case IIO_CHAN_INFO_SCALE:
238 ret = mxc4005_read_scale(data);
244 return IIO_VAL_INT_PLUS_MICRO;
250 static int mxc4005_write_raw(struct iio_dev *indio_dev,
251 struct iio_chan_spec const *chan,
252 int val, int val2, long mask)
254 struct mxc4005_data *data = iio_priv(indio_dev);
257 case IIO_CHAN_INFO_SCALE:
261 return mxc4005_set_scale(data, val2);
267 static const struct iio_info mxc4005_info = {
268 .driver_module = THIS_MODULE,
269 .read_raw = mxc4005_read_raw,
270 .write_raw = mxc4005_write_raw,
271 .attrs = &mxc4005_attrs_group,
274 static const unsigned long mxc4005_scan_masks[] = {
275 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
279 #define MXC4005_CHANNEL(_axis, _addr) { \
282 .channel2 = IIO_MOD_##_axis, \
284 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
285 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
286 .scan_index = AXIS_##_axis, \
292 .endianness = IIO_BE, \
296 static const struct iio_chan_spec mxc4005_channels[] = {
297 MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER),
298 MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER),
299 MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER),
300 IIO_CHAN_SOFT_TIMESTAMP(3),
303 static irqreturn_t mxc4005_trigger_handler(int irq, void *private)
305 struct iio_poll_func *pf = private;
306 struct iio_dev *indio_dev = pf->indio_dev;
307 struct mxc4005_data *data = iio_priv(indio_dev);
310 ret = mxc4005_read_xyz(data);
314 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
318 iio_trigger_notify_done(indio_dev->trig);
323 static int mxc4005_clr_intr(struct mxc4005_data *data)
327 /* clear interrupt */
328 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
329 MXC4005_REG_INT_CLR1_BIT_DRDYC);
331 dev_err(data->dev, "failed to write to reg_int_clr1\n");
338 static int mxc4005_set_trigger_state(struct iio_trigger *trig,
341 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
342 struct mxc4005_data *data = iio_priv(indio_dev);
345 mutex_lock(&data->mutex);
347 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
348 MXC4005_REG_INT_MASK1_BIT_DRDYE);
350 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
351 ~MXC4005_REG_INT_MASK1_BIT_DRDYE);
355 mutex_unlock(&data->mutex);
356 dev_err(data->dev, "failed to update reg_int_mask1");
360 data->trigger_enabled = state;
361 mutex_unlock(&data->mutex);
366 static int mxc4005_trigger_try_reen(struct iio_trigger *trig)
368 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
369 struct mxc4005_data *data = iio_priv(indio_dev);
371 if (!data->dready_trig)
374 return mxc4005_clr_intr(data);
377 static const struct iio_trigger_ops mxc4005_trigger_ops = {
378 .set_trigger_state = mxc4005_set_trigger_state,
379 .try_reenable = mxc4005_trigger_try_reen,
380 .owner = THIS_MODULE,
383 static int mxc4005_gpio_probe(struct i2c_client *client,
384 struct mxc4005_data *data)
387 struct gpio_desc *gpio;
395 gpio = devm_gpiod_get_index(dev, "mxc4005_int", 0, GPIOD_IN);
397 dev_err(dev, "failed to get acpi gpio index\n");
398 return PTR_ERR(gpio);
401 ret = gpiod_to_irq(gpio);
403 dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret);
408 static int mxc4005_chip_init(struct mxc4005_data *data)
413 ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, ®);
415 dev_err(data->dev, "failed to read chip id\n");
419 dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg);
424 static int mxc4005_probe(struct i2c_client *client,
425 const struct i2c_device_id *id)
427 struct mxc4005_data *data;
428 struct iio_dev *indio_dev;
429 struct regmap *regmap;
432 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
436 regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config);
437 if (IS_ERR(regmap)) {
438 dev_err(&client->dev, "failed to initialize regmap\n");
439 return PTR_ERR(regmap);
442 data = iio_priv(indio_dev);
443 i2c_set_clientdata(client, indio_dev);
444 data->dev = &client->dev;
445 data->regmap = regmap;
447 ret = mxc4005_chip_init(data);
449 dev_err(&client->dev, "failed to initialize chip\n");
453 mutex_init(&data->mutex);
455 indio_dev->dev.parent = &client->dev;
456 indio_dev->channels = mxc4005_channels;
457 indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels);
458 indio_dev->available_scan_masks = mxc4005_scan_masks;
459 indio_dev->name = MXC4005_DRV_NAME;
460 indio_dev->modes = INDIO_DIRECT_MODE;
461 indio_dev->info = &mxc4005_info;
463 ret = iio_triggered_buffer_setup(indio_dev,
464 iio_pollfunc_store_time,
465 mxc4005_trigger_handler,
468 dev_err(&client->dev,
469 "failed to setup iio triggered buffer\n");
474 client->irq = mxc4005_gpio_probe(client, data);
476 if (client->irq > 0) {
477 data->dready_trig = devm_iio_trigger_alloc(&client->dev,
481 if (!data->dready_trig)
484 ret = devm_request_threaded_irq(&client->dev, client->irq,
485 iio_trigger_generic_data_rdy_poll,
487 IRQF_TRIGGER_FALLING |
492 dev_err(&client->dev,
493 "failed to init threaded irq\n");
494 goto err_buffer_cleanup;
497 data->dready_trig->dev.parent = &client->dev;
498 data->dready_trig->ops = &mxc4005_trigger_ops;
499 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
500 indio_dev->trig = data->dready_trig;
501 iio_trigger_get(indio_dev->trig);
502 ret = iio_trigger_register(data->dready_trig);
504 dev_err(&client->dev,
505 "failed to register trigger\n");
506 goto err_trigger_unregister;
510 ret = iio_device_register(indio_dev);
512 dev_err(&client->dev,
513 "unable to register iio device %d\n", ret);
514 goto err_buffer_cleanup;
519 err_trigger_unregister:
520 iio_trigger_unregister(data->dready_trig);
522 iio_triggered_buffer_cleanup(indio_dev);
527 static int mxc4005_remove(struct i2c_client *client)
529 struct iio_dev *indio_dev = i2c_get_clientdata(client);
530 struct mxc4005_data *data = iio_priv(indio_dev);
532 iio_device_unregister(indio_dev);
534 iio_triggered_buffer_cleanup(indio_dev);
535 if (data->dready_trig)
536 iio_trigger_unregister(data->dready_trig);
541 static const struct acpi_device_id mxc4005_acpi_match[] = {
545 MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match);
547 static const struct i2c_device_id mxc4005_id[] = {
551 MODULE_DEVICE_TABLE(i2c, mxc4005_id);
553 static struct i2c_driver mxc4005_driver = {
555 .name = MXC4005_DRV_NAME,
556 .acpi_match_table = ACPI_PTR(mxc4005_acpi_match),
558 .probe = mxc4005_probe,
559 .remove = mxc4005_remove,
560 .id_table = mxc4005_id,
563 module_i2c_driver(mxc4005_driver);
565 MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>");
566 MODULE_LICENSE("GPL v2");
567 MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver");