2 * Driver for the ADC present in the Atmel AT91 evaluation boards.
4 * Copyright 2011 Free Electrons
6 * Licensed under the GPLv2 or later.
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
14 #include <linux/input.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
26 #include <linux/platform_data/at91_adc.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
35 #define AT91_ADC_CR 0x00 /* Control Register */
36 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
37 #define AT91_ADC_START (1 << 1) /* Start Conversion */
39 #define AT91_ADC_MR 0x04 /* Mode Register */
40 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
41 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
42 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
43 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
44 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
45 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
46 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
47 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
48 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
49 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
50 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
51 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
52 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
53 #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
54 #define AT91_ADC_PRESCAL_(x) ((x) << 8)
55 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
56 #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
57 #define AT91_ADC_STARTUP_9X5 (0xf << 16)
58 #define AT91_ADC_STARTUP_(x) ((x) << 16)
59 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
60 #define AT91_ADC_SHTIM_(x) ((x) << 24)
61 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
62 #define AT91_ADC_PENDBC_(x) ((x) << 28)
64 #define AT91_ADC_TSR 0x0C
65 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
66 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
68 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
69 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
70 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
71 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
73 #define AT91_ADC_SR 0x1C /* Status Register */
74 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
75 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
76 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
77 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
78 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
79 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
81 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
82 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
84 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
85 #define AT91_ADC_LDATA (0x3ff)
87 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
88 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
89 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
90 #define AT91RL_ADC_IER_PEN (1 << 20)
91 #define AT91RL_ADC_IER_NOPEN (1 << 21)
92 #define AT91_ADC_IER_PEN (1 << 29)
93 #define AT91_ADC_IER_NOPEN (1 << 30)
94 #define AT91_ADC_IER_XRDY (1 << 20)
95 #define AT91_ADC_IER_YRDY (1 << 21)
96 #define AT91_ADC_IER_PRDY (1 << 22)
97 #define AT91_ADC_ISR_PENS (1 << 31)
99 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
100 #define AT91_ADC_DATA (0x3ff)
102 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
104 #define AT91_ADC_ACR 0x94 /* Analog Control Register */
105 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
107 #define AT91_ADC_TSMR 0xB0
108 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
109 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
110 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
111 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
112 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
113 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
114 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
115 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
116 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
117 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
118 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
119 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
120 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
122 #define AT91_ADC_TSXPOSR 0xB4
123 #define AT91_ADC_TSYPOSR 0xB8
124 #define AT91_ADC_TSPRESSR 0xBC
126 #define AT91_ADC_TRGR_9260 AT91_ADC_MR
127 #define AT91_ADC_TRGR_9G45 0x08
128 #define AT91_ADC_TRGR_9X5 0xC0
130 /* Trigger Register bit field */
131 #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
132 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
133 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
134 #define AT91_ADC_TRGR_NONE (0 << 0)
135 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
137 #define AT91_ADC_CHAN(st, ch) \
138 (st->registers->channel_base + (ch * 4))
139 #define at91_adc_readl(st, reg) \
140 (readl_relaxed(st->reg_base + reg))
141 #define at91_adc_writel(st, reg, val) \
142 (writel_relaxed(val, st->reg_base + reg))
144 #define DRIVER_NAME "at91_adc"
145 #define MAX_POS_BITS 12
147 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
148 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
150 #define MAX_RLPOS_BITS 10
151 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
152 #define TOUCH_SHTIM 0xa
155 * struct at91_adc_reg_desc - Various informations relative to registers
156 * @channel_base: Base offset for the channel data registers
157 * @drdy_mask: Mask of the DRDY field in the relevant registers
158 (Interruptions registers mostly)
159 * @status_register: Offset of the Interrupt Status Register
160 * @trigger_register: Offset of the Trigger setup register
161 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
162 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
164 struct at91_adc_reg_desc {
173 struct at91_adc_caps {
174 bool has_ts; /* Support touch screen */
175 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
177 * Numbers of sampling data will be averaged. Can be 0~3.
178 * Hardware can average (2 ^ ts_filter_average) sample data.
180 u8 ts_filter_average;
181 /* Pen Detection input pull-up resistor, can be 0~3 */
182 u8 ts_pen_detect_sensitivity;
184 /* startup time calculate function */
185 u32 (*calc_startup_ticks)(u8 startup_time, u32 adc_clk_khz);
188 struct at91_adc_reg_desc registers;
191 struct at91_adc_state {
194 unsigned long channels_mask;
202 void __iomem *reg_base;
203 struct at91_adc_reg_desc *registers;
207 struct iio_trigger **trig;
208 struct at91_adc_trigger *trigger_list;
212 u32 res; /* resolution used for convertions */
213 bool low_res; /* the resolution corresponds to the lowest one */
214 wait_queue_head_t wq_data_avail;
215 struct at91_adc_caps *caps;
218 * Following ADC channels are shared by touchscreen:
220 * CH0 -- Touch screen XP/UL
221 * CH1 -- Touch screen XM/UR
222 * CH2 -- Touch screen YP/LL
223 * CH3 -- Touch screen YM/Sense
224 * CH4 -- Touch screen LR(5-wire only)
226 * The bitfields below represents the reserved channel in the
229 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
230 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
231 enum atmel_adc_ts_type touchscreen_type;
232 struct input_dev *ts_input;
234 u16 ts_sample_period_val;
235 u32 ts_pressure_threshold;
238 bool ts_bufferedmeasure;
243 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
245 struct iio_poll_func *pf = p;
246 struct iio_dev *idev = pf->indio_dev;
247 struct at91_adc_state *st = iio_priv(idev);
250 for (i = 0; i < idev->masklength; i++) {
251 if (!test_bit(i, idev->active_scan_mask))
253 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i));
257 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
259 iio_trigger_notify_done(idev->trig);
261 /* Needed to ACK the DRDY interruption */
262 at91_adc_readl(st, AT91_ADC_LCDR);
269 /* Handler for classic adc channel eoc trigger */
270 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
272 struct at91_adc_state *st = iio_priv(idev);
274 if (iio_buffer_enabled(idev)) {
275 disable_irq_nosync(irq);
276 iio_trigger_poll(idev->trig);
278 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
280 wake_up_interruptible(&st->wq_data_avail);
284 static int at91_ts_sample(struct at91_adc_state *st)
286 unsigned int xscale, yscale, reg, z1, z2;
287 unsigned int x, y, pres, xpos, ypos;
288 unsigned int rxp = 1;
289 unsigned int factor = 1000;
290 struct iio_dev *idev = iio_priv_to_dev(st);
292 unsigned int xyz_mask_bits = st->res;
293 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
295 /* calculate position */
296 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
297 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
298 xpos = reg & xyz_mask;
299 x = (xpos << MAX_POS_BITS) - xpos;
300 xscale = (reg >> 16) & xyz_mask;
302 dev_err(&idev->dev, "Error: xscale == 0!\n");
307 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
308 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
309 ypos = reg & xyz_mask;
310 y = (ypos << MAX_POS_BITS) - ypos;
311 yscale = (reg >> 16) & xyz_mask;
313 dev_err(&idev->dev, "Error: yscale == 0!\n");
318 /* calculate the pressure */
319 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
321 z2 = (reg >> 16) & xyz_mask;
324 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
327 pres = st->ts_pressure_threshold; /* no pen contacted */
329 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
330 xpos, xscale, ypos, yscale, z1, z2, pres);
332 if (pres < st->ts_pressure_threshold) {
333 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
334 x, y, pres / factor);
335 input_report_abs(st->ts_input, ABS_X, x);
336 input_report_abs(st->ts_input, ABS_Y, y);
337 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
338 input_report_key(st->ts_input, BTN_TOUCH, 1);
339 input_sync(st->ts_input);
341 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
347 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
349 struct iio_dev *idev = private;
350 struct at91_adc_state *st = iio_priv(idev);
351 u32 status = at91_adc_readl(st, st->registers->status_register);
354 status &= at91_adc_readl(st, AT91_ADC_IMR);
355 if (status & GENMASK(st->num_channels - 1, 0))
356 handle_adc_eoc_trigger(irq, idev);
358 if (status & AT91RL_ADC_IER_PEN) {
359 /* Disabling pen debounce is required to get a NOPEN irq */
360 reg = at91_adc_readl(st, AT91_ADC_MR);
361 reg &= ~AT91_ADC_PENDBC;
362 at91_adc_writel(st, AT91_ADC_MR, reg);
364 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
365 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
367 /* Set up period trigger for sampling */
368 at91_adc_writel(st, st->registers->trigger_register,
369 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
370 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
371 } else if (status & AT91RL_ADC_IER_NOPEN) {
372 reg = at91_adc_readl(st, AT91_ADC_MR);
373 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
374 at91_adc_writel(st, AT91_ADC_MR, reg);
375 at91_adc_writel(st, st->registers->trigger_register,
378 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
380 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
381 st->ts_bufferedmeasure = false;
382 input_report_key(st->ts_input, BTN_TOUCH, 0);
383 input_sync(st->ts_input);
384 } else if (status & AT91_ADC_EOC(3)) {
385 /* Conversion finished */
386 if (st->ts_bufferedmeasure) {
388 * Last measurement is always discarded, since it can
390 * Always report previous measurement
392 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
393 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
394 input_report_key(st->ts_input, BTN_TOUCH, 1);
395 input_sync(st->ts_input);
397 st->ts_bufferedmeasure = true;
399 /* Now make new measurement */
400 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
402 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
404 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
406 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
412 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
414 struct iio_dev *idev = private;
415 struct at91_adc_state *st = iio_priv(idev);
416 u32 status = at91_adc_readl(st, st->registers->status_register);
417 const uint32_t ts_data_irq_mask =
422 if (status & GENMASK(st->num_channels - 1, 0))
423 handle_adc_eoc_trigger(irq, idev);
425 if (status & AT91_ADC_IER_PEN) {
426 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
427 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
429 /* Set up period trigger for sampling */
430 at91_adc_writel(st, st->registers->trigger_register,
431 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
432 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
433 } else if (status & AT91_ADC_IER_NOPEN) {
434 at91_adc_writel(st, st->registers->trigger_register, 0);
435 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
437 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
439 input_report_key(st->ts_input, BTN_TOUCH, 0);
440 input_sync(st->ts_input);
441 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
442 /* Now all touchscreen data is ready */
444 if (status & AT91_ADC_ISR_PENS) {
445 /* validate data by pen contact */
448 /* triggered by event that is no pen contact, just read
449 * them to clean the interrupt and discard all.
451 at91_adc_readl(st, AT91_ADC_TSXPOSR);
452 at91_adc_readl(st, AT91_ADC_TSYPOSR);
453 at91_adc_readl(st, AT91_ADC_TSPRESSR);
460 static int at91_adc_channel_init(struct iio_dev *idev)
462 struct at91_adc_state *st = iio_priv(idev);
463 struct iio_chan_spec *chan_array, *timestamp;
465 unsigned long rsvd_mask = 0;
467 /* If touchscreen is enable, then reserve the adc channels */
468 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
469 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
470 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
471 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
473 /* set up the channel mask to reserve touchscreen channels */
474 st->channels_mask &= ~rsvd_mask;
476 idev->num_channels = bitmap_weight(&st->channels_mask,
477 st->num_channels) + 1;
479 chan_array = devm_kzalloc(&idev->dev,
480 ((idev->num_channels + 1) *
481 sizeof(struct iio_chan_spec)),
487 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
488 struct iio_chan_spec *chan = chan_array + idx;
490 chan->type = IIO_VOLTAGE;
493 chan->scan_index = idx;
494 chan->scan_type.sign = 'u';
495 chan->scan_type.realbits = st->res;
496 chan->scan_type.storagebits = 16;
497 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
498 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
501 timestamp = chan_array + idx;
503 timestamp->type = IIO_TIMESTAMP;
504 timestamp->channel = -1;
505 timestamp->scan_index = idx;
506 timestamp->scan_type.sign = 's';
507 timestamp->scan_type.realbits = 64;
508 timestamp->scan_type.storagebits = 64;
510 idev->channels = chan_array;
511 return idev->num_channels;
514 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
515 struct at91_adc_trigger *triggers,
516 const char *trigger_name)
518 struct at91_adc_state *st = iio_priv(idev);
521 for (i = 0; i < st->trigger_number; i++) {
522 char *name = kasprintf(GFP_KERNEL,
530 if (strcmp(trigger_name, name) == 0) {
532 if (triggers[i].value == 0)
534 return triggers[i].value;
543 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
545 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
546 struct at91_adc_state *st = iio_priv(idev);
547 struct iio_buffer *buffer = idev->buffer;
548 struct at91_adc_reg_desc *reg = st->registers;
549 u32 status = at91_adc_readl(st, reg->trigger_register);
553 value = at91_adc_get_trigger_value_by_name(idev,
560 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
561 if (st->buffer == NULL)
564 at91_adc_writel(st, reg->trigger_register,
567 for_each_set_bit(bit, buffer->scan_mask,
569 struct iio_chan_spec const *chan = idev->channels + bit;
570 at91_adc_writel(st, AT91_ADC_CHER,
571 AT91_ADC_CH(chan->channel));
574 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
577 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
579 at91_adc_writel(st, reg->trigger_register,
582 for_each_set_bit(bit, buffer->scan_mask,
584 struct iio_chan_spec const *chan = idev->channels + bit;
585 at91_adc_writel(st, AT91_ADC_CHDR,
586 AT91_ADC_CH(chan->channel));
594 static const struct iio_trigger_ops at91_adc_trigger_ops = {
595 .owner = THIS_MODULE,
596 .set_trigger_state = &at91_adc_configure_trigger,
599 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
600 struct at91_adc_trigger *trigger)
602 struct iio_trigger *trig;
605 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
606 idev->id, trigger->name);
610 trig->dev.parent = idev->dev.parent;
611 iio_trigger_set_drvdata(trig, idev);
612 trig->ops = &at91_adc_trigger_ops;
614 ret = iio_trigger_register(trig);
621 static int at91_adc_trigger_init(struct iio_dev *idev)
623 struct at91_adc_state *st = iio_priv(idev);
626 st->trig = devm_kzalloc(&idev->dev,
627 st->trigger_number * sizeof(*st->trig),
630 if (st->trig == NULL) {
635 for (i = 0; i < st->trigger_number; i++) {
636 if (st->trigger_list[i].is_external && !(st->use_external))
639 st->trig[i] = at91_adc_allocate_trigger(idev,
640 st->trigger_list + i);
641 if (st->trig[i] == NULL) {
643 "Could not allocate trigger %d\n", i);
652 for (i--; i >= 0; i--) {
653 iio_trigger_unregister(st->trig[i]);
654 iio_trigger_free(st->trig[i]);
660 static void at91_adc_trigger_remove(struct iio_dev *idev)
662 struct at91_adc_state *st = iio_priv(idev);
665 for (i = 0; i < st->trigger_number; i++) {
666 iio_trigger_unregister(st->trig[i]);
667 iio_trigger_free(st->trig[i]);
671 static int at91_adc_buffer_init(struct iio_dev *idev)
673 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
674 &at91_adc_trigger_handler, NULL);
677 static void at91_adc_buffer_remove(struct iio_dev *idev)
679 iio_triggered_buffer_cleanup(idev);
682 static int at91_adc_read_raw(struct iio_dev *idev,
683 struct iio_chan_spec const *chan,
684 int *val, int *val2, long mask)
686 struct at91_adc_state *st = iio_priv(idev);
690 case IIO_CHAN_INFO_RAW:
691 mutex_lock(&st->lock);
693 st->chnb = chan->channel;
694 at91_adc_writel(st, AT91_ADC_CHER,
695 AT91_ADC_CH(chan->channel));
696 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
697 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
699 ret = wait_event_interruptible_timeout(st->wq_data_avail,
701 msecs_to_jiffies(1000));
705 mutex_unlock(&st->lock);
709 *val = st->last_value;
711 at91_adc_writel(st, AT91_ADC_CHDR,
712 AT91_ADC_CH(chan->channel));
713 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
717 mutex_unlock(&st->lock);
720 case IIO_CHAN_INFO_SCALE:
722 *val2 = chan->scan_type.realbits;
723 return IIO_VAL_FRACTIONAL_LOG2;
730 static int at91_adc_of_get_resolution(struct at91_adc_state *st,
731 struct platform_device *pdev)
733 struct iio_dev *idev = iio_priv_to_dev(st);
734 struct device_node *np = pdev->dev.of_node;
735 int count, i, ret = 0;
739 count = of_property_count_strings(np, "atmel,adc-res-names");
741 dev_err(&idev->dev, "You must specified at least two resolution names for "
742 "adc-res-names property in the DT\n");
746 resolutions = kmalloc(count * sizeof(*resolutions), GFP_KERNEL);
750 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
751 dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
756 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
757 res_name = "highres";
759 for (i = 0; i < count; i++) {
760 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
763 if (strcmp(res_name, s))
766 st->res = resolutions[i];
767 if (!strcmp(res_name, "lowres"))
772 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
776 dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
783 static u32 calc_startup_ticks_9260(u8 startup_time, u32 adc_clk_khz)
786 * Number of ticks needed to cover the startup time of the ADC
787 * as defined in the electrical characteristics of the board,
788 * divided by 8. The formula thus is :
789 * Startup Time = (ticks + 1) * 8 / ADC Clock
791 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
794 static u32 calc_startup_ticks_9x5(u8 startup_time, u32 adc_clk_khz)
797 * For sama5d3x and at91sam9x5, the formula changes to:
798 * Startup Time = <lookup_table_value> / ADC Clock
800 const int startup_lookup[] = {
806 int i, size = ARRAY_SIZE(startup_lookup);
809 ticks = startup_time * adc_clk_khz / 1000;
810 for (i = 0; i < size; i++)
811 if (ticks < startup_lookup[i])
816 /* Reach the end of lookup table */
822 static const struct of_device_id at91_adc_dt_ids[];
824 static int at91_adc_probe_dt_ts(struct device_node *node,
825 struct at91_adc_state *st, struct device *dev)
830 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
832 dev_info(dev, "ADC Touch screen is disabled.\n");
839 st->touchscreen_type = prop;
842 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
846 if (!st->caps->has_tsmr)
849 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
850 st->ts_pressure_threshold = prop;
851 if (st->ts_pressure_threshold) {
854 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
859 static int at91_adc_probe_dt(struct at91_adc_state *st,
860 struct platform_device *pdev)
862 struct iio_dev *idev = iio_priv_to_dev(st);
863 struct device_node *node = pdev->dev.of_node;
864 struct device_node *trig_node;
871 st->caps = (struct at91_adc_caps *)
872 of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
874 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
876 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
877 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
881 st->channels_mask = prop;
883 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
885 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
886 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
890 st->startup_time = prop;
893 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
894 st->sample_hold_time = prop;
896 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
897 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
903 ret = at91_adc_of_get_resolution(st, pdev);
907 st->registers = &st->caps->registers;
908 st->num_channels = st->caps->num_channels;
909 st->trigger_number = of_get_child_count(node);
910 st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
911 sizeof(struct at91_adc_trigger),
913 if (!st->trigger_list) {
914 dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
919 for_each_child_of_node(node, trig_node) {
920 struct at91_adc_trigger *trig = st->trigger_list + i;
923 if (of_property_read_string(trig_node, "trigger-name", &name)) {
924 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
930 if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
931 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
936 trig->is_external = of_property_read_bool(trig_node, "trigger-external");
940 /* Check if touchscreen is supported. */
941 if (st->caps->has_ts)
942 return at91_adc_probe_dt_ts(node, st, &idev->dev);
944 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
952 static int at91_adc_probe_pdata(struct at91_adc_state *st,
953 struct platform_device *pdev)
955 struct at91_adc_data *pdata = pdev->dev.platform_data;
960 st->caps = (struct at91_adc_caps *)
961 platform_get_device_id(pdev)->driver_data;
963 st->use_external = pdata->use_external_triggers;
964 st->vref_mv = pdata->vref;
965 st->channels_mask = pdata->channels_used;
966 st->num_channels = st->caps->num_channels;
967 st->startup_time = pdata->startup_time;
968 st->trigger_number = pdata->trigger_number;
969 st->trigger_list = pdata->trigger_list;
970 st->registers = &st->caps->registers;
971 st->touchscreen_type = pdata->touchscreen_type;
976 static const struct iio_info at91_adc_info = {
977 .driver_module = THIS_MODULE,
978 .read_raw = &at91_adc_read_raw,
981 /* Touchscreen related functions */
982 static int atmel_ts_open(struct input_dev *dev)
984 struct at91_adc_state *st = input_get_drvdata(dev);
986 if (st->caps->has_tsmr)
987 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
989 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
993 static void atmel_ts_close(struct input_dev *dev)
995 struct at91_adc_state *st = input_get_drvdata(dev);
997 if (st->caps->has_tsmr)
998 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
1000 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
1003 static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
1008 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
1010 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
1012 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1015 while (st->ts_pendbc >> ++i)
1016 ; /* Empty! Find the shift offset */
1017 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1020 st->ts_pendbc = i - 1;
1022 if (!st->caps->has_tsmr) {
1023 reg = at91_adc_readl(st, AT91_ADC_MR);
1024 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1026 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1027 at91_adc_writel(st, AT91_ADC_MR, reg);
1029 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1030 at91_adc_writel(st, AT91_ADC_TSR, reg);
1032 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1033 adc_clk_khz / 1000) - 1, 1);
1038 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1039 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1041 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1043 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1044 & AT91_ADC_TSMR_TSAV;
1045 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1046 reg |= AT91_ADC_TSMR_NOTSDMA;
1047 reg |= AT91_ADC_TSMR_PENDET_ENA;
1048 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
1050 at91_adc_writel(st, AT91_ADC_TSMR, reg);
1052 /* Change adc internal resistor value for better pen detection,
1053 * default value is 100 kOhm.
1054 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
1055 * option only available on ES2 and higher
1057 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1058 & AT91_ADC_ACR_PENDETSENS);
1060 /* Sample Period Time = (TRGPER + 1) / ADCClock */
1061 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1062 adc_clk_khz / 1000) - 1, 1);
1067 static int at91_ts_register(struct at91_adc_state *st,
1068 struct platform_device *pdev)
1070 struct input_dev *input;
1071 struct iio_dev *idev = iio_priv_to_dev(st);
1074 input = input_allocate_device();
1076 dev_err(&idev->dev, "Failed to allocate TS device!\n");
1080 input->name = DRIVER_NAME;
1081 input->id.bustype = BUS_HOST;
1082 input->dev.parent = &pdev->dev;
1083 input->open = atmel_ts_open;
1084 input->close = atmel_ts_close;
1086 __set_bit(EV_ABS, input->evbit);
1087 __set_bit(EV_KEY, input->evbit);
1088 __set_bit(BTN_TOUCH, input->keybit);
1089 if (st->caps->has_tsmr) {
1090 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1092 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1094 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1096 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1098 "This touchscreen controller only support 4 wires\n");
1103 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1105 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1109 st->ts_input = input;
1110 input_set_drvdata(input, st);
1112 ret = input_register_device(input);
1119 input_free_device(st->ts_input);
1123 static void at91_ts_unregister(struct at91_adc_state *st)
1125 input_unregister_device(st->ts_input);
1128 static int at91_adc_probe(struct platform_device *pdev)
1130 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1132 struct iio_dev *idev;
1133 struct at91_adc_state *st;
1134 struct resource *res;
1137 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1141 st = iio_priv(idev);
1143 if (pdev->dev.of_node)
1144 ret = at91_adc_probe_dt(st, pdev);
1146 ret = at91_adc_probe_pdata(st, pdev);
1149 dev_err(&pdev->dev, "No platform data available.\n");
1153 platform_set_drvdata(pdev, idev);
1155 idev->dev.parent = &pdev->dev;
1156 idev->name = dev_name(&pdev->dev);
1157 idev->modes = INDIO_DIRECT_MODE;
1158 idev->info = &at91_adc_info;
1160 st->irq = platform_get_irq(pdev, 0);
1162 dev_err(&pdev->dev, "No IRQ ID is designated\n");
1166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1168 st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1169 if (IS_ERR(st->reg_base)) {
1170 return PTR_ERR(st->reg_base);
1174 * Disable all IRQs before setting up the handler
1176 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1177 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1179 if (st->caps->has_tsmr)
1180 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1181 pdev->dev.driver->name, idev);
1183 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1184 pdev->dev.driver->name, idev);
1186 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1190 st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1191 if (IS_ERR(st->clk)) {
1192 dev_err(&pdev->dev, "Failed to get the clock.\n");
1193 ret = PTR_ERR(st->clk);
1194 goto error_free_irq;
1197 ret = clk_prepare_enable(st->clk);
1200 "Could not prepare or enable the clock.\n");
1201 goto error_free_irq;
1204 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1205 if (IS_ERR(st->adc_clk)) {
1206 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1207 ret = PTR_ERR(st->adc_clk);
1208 goto error_disable_clk;
1211 ret = clk_prepare_enable(st->adc_clk);
1214 "Could not prepare or enable the ADC clock.\n");
1215 goto error_disable_clk;
1219 * Prescaler rate computation using the formula from the Atmel's
1220 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1221 * specified by the electrical characteristics of the board.
1223 mstrclk = clk_get_rate(st->clk);
1224 adc_clk = clk_get_rate(st->adc_clk);
1225 adc_clk_khz = adc_clk / 1000;
1227 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1230 prsc = (mstrclk / (2 * adc_clk)) - 1;
1232 if (!st->startup_time) {
1233 dev_err(&pdev->dev, "No startup time available.\n");
1235 goto error_disable_adc_clk;
1237 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1240 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1241 * the best converted final value between two channels selection
1242 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1244 if (st->sample_hold_time > 0)
1245 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1250 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1251 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1253 reg |= AT91_ADC_LOWRES;
1255 reg |= AT91_ADC_SLEEP;
1256 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1257 at91_adc_writel(st, AT91_ADC_MR, reg);
1259 /* Setup the ADC channels available on the board */
1260 ret = at91_adc_channel_init(idev);
1262 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1263 goto error_disable_adc_clk;
1266 init_waitqueue_head(&st->wq_data_avail);
1267 mutex_init(&st->lock);
1270 * Since touch screen will set trigger register as period trigger. So
1271 * when touch screen is enabled, then we have to disable hardware
1272 * trigger for classic adc.
1274 if (!st->touchscreen_type) {
1275 ret = at91_adc_buffer_init(idev);
1277 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1278 goto error_disable_adc_clk;
1281 ret = at91_adc_trigger_init(idev);
1283 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1284 at91_adc_buffer_remove(idev);
1285 goto error_disable_adc_clk;
1288 ret = at91_ts_register(st, pdev);
1290 goto error_disable_adc_clk;
1292 at91_ts_hw_init(st, adc_clk_khz);
1295 ret = iio_device_register(idev);
1297 dev_err(&pdev->dev, "Couldn't register the device.\n");
1298 goto error_iio_device_register;
1303 error_iio_device_register:
1304 if (!st->touchscreen_type) {
1305 at91_adc_trigger_remove(idev);
1306 at91_adc_buffer_remove(idev);
1308 at91_ts_unregister(st);
1310 error_disable_adc_clk:
1311 clk_disable_unprepare(st->adc_clk);
1313 clk_disable_unprepare(st->clk);
1315 free_irq(st->irq, idev);
1319 static int at91_adc_remove(struct platform_device *pdev)
1321 struct iio_dev *idev = platform_get_drvdata(pdev);
1322 struct at91_adc_state *st = iio_priv(idev);
1324 iio_device_unregister(idev);
1325 if (!st->touchscreen_type) {
1326 at91_adc_trigger_remove(idev);
1327 at91_adc_buffer_remove(idev);
1329 at91_ts_unregister(st);
1331 clk_disable_unprepare(st->adc_clk);
1332 clk_disable_unprepare(st->clk);
1333 free_irq(st->irq, idev);
1338 static struct at91_adc_caps at91sam9260_caps = {
1339 .calc_startup_ticks = calc_startup_ticks_9260,
1342 .channel_base = AT91_ADC_CHR(0),
1343 .drdy_mask = AT91_ADC_DRDY,
1344 .status_register = AT91_ADC_SR,
1345 .trigger_register = AT91_ADC_TRGR_9260,
1346 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1347 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1351 static struct at91_adc_caps at91sam9rl_caps = {
1353 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1356 .channel_base = AT91_ADC_CHR(0),
1357 .drdy_mask = AT91_ADC_DRDY,
1358 .status_register = AT91_ADC_SR,
1359 .trigger_register = AT91_ADC_TRGR_9G45,
1360 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1361 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1365 static struct at91_adc_caps at91sam9g45_caps = {
1367 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1370 .channel_base = AT91_ADC_CHR(0),
1371 .drdy_mask = AT91_ADC_DRDY,
1372 .status_register = AT91_ADC_SR,
1373 .trigger_register = AT91_ADC_TRGR_9G45,
1374 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1375 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1379 static struct at91_adc_caps at91sam9x5_caps = {
1382 .ts_filter_average = 3,
1383 .ts_pen_detect_sensitivity = 2,
1384 .calc_startup_ticks = calc_startup_ticks_9x5,
1387 .channel_base = AT91_ADC_CDR0_9X5,
1388 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1389 .status_register = AT91_ADC_SR_9X5,
1390 .trigger_register = AT91_ADC_TRGR_9X5,
1391 /* prescal mask is same as 9G45 */
1392 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1393 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1397 static const struct of_device_id at91_adc_dt_ids[] = {
1398 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1399 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1400 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1401 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1404 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1406 static const struct platform_device_id at91_adc_ids[] = {
1408 .name = "at91sam9260-adc",
1409 .driver_data = (unsigned long)&at91sam9260_caps,
1411 .name = "at91sam9rl-adc",
1412 .driver_data = (unsigned long)&at91sam9rl_caps,
1414 .name = "at91sam9g45-adc",
1415 .driver_data = (unsigned long)&at91sam9g45_caps,
1417 .name = "at91sam9x5-adc",
1418 .driver_data = (unsigned long)&at91sam9x5_caps,
1423 MODULE_DEVICE_TABLE(platform, at91_adc_ids);
1425 static struct platform_driver at91_adc_driver = {
1426 .probe = at91_adc_probe,
1427 .remove = at91_adc_remove,
1428 .id_table = at91_adc_ids,
1430 .name = DRIVER_NAME,
1431 .of_match_table = of_match_ptr(at91_adc_dt_ids),
1435 module_platform_driver(at91_adc_driver);
1437 MODULE_LICENSE("GPL");
1438 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1439 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");