drivers/iio/adc/exynos_adc.c

   1 /*
   2  *  exynos_adc.c - Support for ADC in EXYNOS SoCs
   3  *
   4  *  8 ~ 10 channel, 10/12-bit ADC
   5  *
   6  *  Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/kernel.h>
  29 #include <linux/slab.h>
  30 #include <linux/io.h>
  31 #include <linux/clk.h>
  32 #include <linux/completion.h>
  33 #include <linux/of.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/err.h>
  38
  39 #include <linux/iio/iio.h>
  40 #include <linux/iio/machine.h>
  41 #include <linux/iio/driver.h>
  42
  43 /* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
  44 #define ADC_V1_CON(x)           ((x) + 0x00)
  45 #define ADC_V1_DLY(x)           ((x) + 0x08)
  46 #define ADC_V1_DATX(x)          ((x) + 0x0C)
  47 #define ADC_V1_INTCLR(x)        ((x) + 0x18)
  48 #define ADC_V1_MUX(x)           ((x) + 0x1c)
  49
  50 /* Future ADC_V2 registers definitions */
  51 #define ADC_V2_CON1(x)          ((x) + 0x00)
  52 #define ADC_V2_CON2(x)          ((x) + 0x04)
  53 #define ADC_V2_STAT(x)          ((x) + 0x08)
  54 #define ADC_V2_INT_EN(x)        ((x) + 0x10)
  55 #define ADC_V2_INT_ST(x)        ((x) + 0x14)
  56 #define ADC_V2_VER(x)           ((x) + 0x20)
  57
  58 /* Bit definitions for ADC_V1 */
  59 #define ADC_V1_CON_RES          (1u << 16)
  60 #define ADC_V1_CON_PRSCEN       (1u << 14)
  61 #define ADC_V1_CON_PRSCLV(x)    (((x) & 0xFF) << 6)
  62 #define ADC_V1_CON_STANDBY      (1u << 2)
  63
  64 /* Bit definitions for S3C2410 ADC */
  65 #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
  66
  67 /* Bit definitions for ADC_V2 */
  68 #define ADC_V2_CON1_SOFT_RESET  (1u << 2)
  69
  70 #define ADC_V2_CON2_OSEL        (1u << 10)
  71 #define ADC_V2_CON2_ESEL        (1u << 9)
  72 #define ADC_V2_CON2_HIGHF       (1u << 8)
  73 #define ADC_V2_CON2_C_TIME(x)   (((x) & 7) << 4)
  74 #define ADC_V2_CON2_ACH_SEL(x)  (((x) & 0xF) << 0)
  75 #define ADC_V2_CON2_ACH_MASK    0xF
  76
  77 #define MAX_ADC_V2_CHANNELS             10
  78 #define MAX_ADC_V1_CHANNELS             8
  79 #define MAX_EXYNOS3250_ADC_CHANNELS     2
  80
  81 /* Bit definitions common for ADC_V1 and ADC_V2 */
  82 #define ADC_CON_EN_START        (1u << 0)
  83 #define ADC_DATX_MASK           0xFFF
  84
  85 #define EXYNOS_ADC_TIMEOUT      (msecs_to_jiffies(100))
  86
  87 struct exynos_adc {
  88         struct exynos_adc_data  *data;
  89         struct device           *dev;
  90         void __iomem            *regs;
  91         void __iomem            *enable_reg;
  92         struct clk              *clk;
  93         struct clk              *sclk;
  94         unsigned int            irq;
  95         struct regulator        *vdd;
  96
  97         struct completion       completion;
  98
  99         u32                     value;
 100         unsigned int            version;
 101 };
 102
 103 struct exynos_adc_data {
 104         int num_channels;
 105         bool needs_sclk;
 106
 107         void (*init_hw)(struct exynos_adc *info);
 108         void (*exit_hw)(struct exynos_adc *info);
 109         void (*clear_irq)(struct exynos_adc *info);
 110         void (*start_conv)(struct exynos_adc *info, unsigned long addr);
 111 };
 112
 113 static void exynos_adc_unprepare_clk(struct exynos_adc *info)
 114 {
 115         if (info->data->needs_sclk)
 116                 clk_unprepare(info->sclk);
 117         clk_unprepare(info->clk);
 118 }
 119
 120 static int exynos_adc_prepare_clk(struct exynos_adc *info)
 121 {
 122         int ret;
 123
 124         ret = clk_prepare(info->clk);
 125         if (ret) {
 126                 dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
 127                 return ret;
 128         }
 129
 130         if (info->data->needs_sclk) {
 131                 ret = clk_prepare(info->sclk);
 132                 if (ret) {
 133                         clk_unprepare(info->clk);
 134                         dev_err(info->dev,
 135                                 "failed preparing sclk_adc clock: %d\n", ret);
 136                         return ret;
 137                 }
 138         }
 139
 140         return 0;
 141 }
 142
 143 static void exynos_adc_disable_clk(struct exynos_adc *info)
 144 {
 145         if (info->data->needs_sclk)
 146                 clk_disable(info->sclk);
 147         clk_disable(info->clk);
 148 }
 149
 150 static int exynos_adc_enable_clk(struct exynos_adc *info)
 151 {
 152         int ret;
 153
 154         ret = clk_enable(info->clk);
 155         if (ret) {
 156                 dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
 157                 return ret;
 158         }
 159
 160         if (info->data->needs_sclk) {
 161                 ret = clk_enable(info->sclk);
 162                 if (ret) {
 163                         clk_disable(info->clk);
 164                         dev_err(info->dev,
 165                                 "failed enabling sclk_adc clock: %d\n", ret);
 166                         return ret;
 167                 }
 168         }
 169
 170         return 0;
 171 }
 172
 173 static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 174 {
 175         u32 con1;
 176
 177         writel(1, info->enable_reg);
 178
 179         /* set default prescaler values and Enable prescaler */
 180         con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 181
 182         /* Enable 12-bit ADC resolution */
 183         con1 |= ADC_V1_CON_RES;
 184         writel(con1, ADC_V1_CON(info->regs));
 185 }
 186
 187 static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
 188 {
 189         u32 con;
 190
 191         writel(0, info->enable_reg);
 192
 193         con = readl(ADC_V1_CON(info->regs));
 194         con |= ADC_V1_CON_STANDBY;
 195         writel(con, ADC_V1_CON(info->regs));
 196 }
 197
 198 static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
 199 {
 200         writel(1, ADC_V1_INTCLR(info->regs));
 201 }
 202
 203 static void exynos_adc_v1_start_conv(struct exynos_adc *info,
 204                                      unsigned long addr)
 205 {
 206         u32 con1;
 207
 208         writel(addr, ADC_V1_MUX(info->regs));
 209
 210         con1 = readl(ADC_V1_CON(info->regs));
 211         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 212 }
 213
 214 static const struct exynos_adc_data exynos_adc_v1_data = {
 215         .num_channels   = MAX_ADC_V1_CHANNELS,
 216
 217         .init_hw        = exynos_adc_v1_init_hw,
 218         .exit_hw        = exynos_adc_v1_exit_hw,
 219         .clear_irq      = exynos_adc_v1_clear_irq,
 220         .start_conv     = exynos_adc_v1_start_conv,
 221 };
 222
 223 static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
 224                                           unsigned long addr)
 225 {
 226         u32 con1;
 227
 228         con1 = readl(ADC_V1_CON(info->regs));
 229         con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
 230         con1 |= ADC_S3C2410_CON_SELMUX(addr);
 231         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 232 }
 233
 234 static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
 235         .num_channels   = MAX_ADC_V1_CHANNELS,
 236
 237         .init_hw        = exynos_adc_v1_init_hw,
 238         .exit_hw        = exynos_adc_v1_exit_hw,
 239         .clear_irq      = exynos_adc_v1_clear_irq,
 240         .start_conv     = exynos_adc_s3c64xx_start_conv,
 241 };
 242
 243 static void exynos_adc_v2_init_hw(struct exynos_adc *info)
 244 {
 245         u32 con1, con2;
 246
 247         writel(1, info->enable_reg);
 248
 249         con1 = ADC_V2_CON1_SOFT_RESET;
 250         writel(con1, ADC_V2_CON1(info->regs));
 251
 252         con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 253                 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 254         writel(con2, ADC_V2_CON2(info->regs));
 255
 256         /* Enable interrupts */
 257         writel(1, ADC_V2_INT_EN(info->regs));
 258 }
 259
 260 static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
 261 {
 262         u32 con;
 263
 264         writel(0, info->enable_reg);
 265
 266         con = readl(ADC_V2_CON1(info->regs));
 267         con &= ~ADC_CON_EN_START;
 268         writel(con, ADC_V2_CON1(info->regs));
 269 }
 270
 271 static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
 272 {
 273         writel(1, ADC_V2_INT_ST(info->regs));
 274 }
 275
 276 static void exynos_adc_v2_start_conv(struct exynos_adc *info,
 277                                      unsigned long addr)
 278 {
 279         u32 con1, con2;
 280
 281         con2 = readl(ADC_V2_CON2(info->regs));
 282         con2 &= ~ADC_V2_CON2_ACH_MASK;
 283         con2 |= ADC_V2_CON2_ACH_SEL(addr);
 284         writel(con2, ADC_V2_CON2(info->regs));
 285
 286         con1 = readl(ADC_V2_CON1(info->regs));
 287         writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
 288 }
 289
 290 static const struct exynos_adc_data exynos_adc_v2_data = {
 291         .num_channels   = MAX_ADC_V2_CHANNELS,
 292
 293         .init_hw        = exynos_adc_v2_init_hw,
 294         .exit_hw        = exynos_adc_v2_exit_hw,
 295         .clear_irq      = exynos_adc_v2_clear_irq,
 296         .start_conv     = exynos_adc_v2_start_conv,
 297 };
 298
 299 static const struct exynos_adc_data exynos3250_adc_data = {
 300         .num_channels   = MAX_EXYNOS3250_ADC_CHANNELS,
 301         .needs_sclk     = true,
 302
 303         .init_hw        = exynos_adc_v2_init_hw,
 304         .exit_hw        = exynos_adc_v2_exit_hw,
 305         .clear_irq      = exynos_adc_v2_clear_irq,
 306         .start_conv     = exynos_adc_v2_start_conv,
 307 };
 308
 309 static const struct of_device_id exynos_adc_match[] = {
 310         {
 311                 .compatible = "samsung,s3c6410-adc",
 312                 .data = &exynos_adc_s3c64xx_data,
 313         }, {
 314                 .compatible = "samsung,exynos-adc-v1",
 315                 .data = &exynos_adc_v1_data,
 316         }, {
 317                 .compatible = "samsung,exynos-adc-v2",
 318                 .data = &exynos_adc_v2_data,
 319         }, {
 320                 .compatible = "samsung,exynos3250-adc",
 321                 .data = &exynos3250_adc_data,
 322         },
 323         {},
 324 };
 325 MODULE_DEVICE_TABLE(of, exynos_adc_match);
 326
 327 static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
 328 {
 329         const struct of_device_id *match;
 330
 331         match = of_match_node(exynos_adc_match, pdev->dev.of_node);
 332         return (struct exynos_adc_data *)match->data;
 333 }
 334
 335 static int exynos_read_raw(struct iio_dev *indio_dev,
 336                                 struct iio_chan_spec const *chan,
 337                                 int *val,
 338                                 int *val2,
 339                                 long mask)
 340 {
 341         struct exynos_adc *info = iio_priv(indio_dev);
 342         unsigned long timeout;
 343         int ret;
 344
 345         if (mask != IIO_CHAN_INFO_RAW)
 346                 return -EINVAL;
 347
 348         mutex_lock(&indio_dev->mlock);
 349         reinit_completion(&info->completion);
 350
 351         /* Select the channel to be used and Trigger conversion */
 352         if (info->data->start_conv)
 353                 info->data->start_conv(info, chan->address);
 354
 355         timeout = wait_for_completion_timeout
 356                         (&info->completion, EXYNOS_ADC_TIMEOUT);
 357         if (timeout == 0) {
 358                 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
 359                 if (info->data->init_hw)
 360                         info->data->init_hw(info);
 361                 ret = -ETIMEDOUT;
 362         } else {
 363                 *val = info->value;
 364                 *val2 = 0;
 365                 ret = IIO_VAL_INT;
 366         }
 367
 368         mutex_unlock(&indio_dev->mlock);
 369
 370         return ret;
 371 }
 372
 373 static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
 374 {
 375         struct exynos_adc *info = (struct exynos_adc *)dev_id;
 376
 377         /* Read value */
 378         info->value = readl(ADC_V1_DATX(info->regs)) & ADC_DATX_MASK;
 379
 380         /* clear irq */
 381         if (info->data->clear_irq)
 382                 info->data->clear_irq(info);
 383
 384         complete(&info->completion);
 385
 386         return IRQ_HANDLED;
 387 }
 388
 389 static int exynos_adc_reg_access(struct iio_dev *indio_dev,
 390                               unsigned reg, unsigned writeval,
 391                               unsigned *readval)
 392 {
 393         struct exynos_adc *info = iio_priv(indio_dev);
 394
 395         if (readval == NULL)
 396                 return -EINVAL;
 397
 398         *readval = readl(info->regs + reg);
 399
 400         return 0;
 401 }
 402
 403 static const struct iio_info exynos_adc_iio_info = {
 404         .read_raw = &exynos_read_raw,
 405         .debugfs_reg_access = &exynos_adc_reg_access,
 406         .driver_module = THIS_MODULE,
 407 };
 408
 409 #define ADC_CHANNEL(_index, _id) {                      \
 410         .type = IIO_VOLTAGE,                            \
 411         .indexed = 1,                                   \
 412         .channel = _index,                              \
 413         .address = _index,                              \
 414         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
 415         .datasheet_name = _id,                          \
 416 }
 417
 418 static const struct iio_chan_spec exynos_adc_iio_channels[] = {
 419         ADC_CHANNEL(0, "adc0"),
 420         ADC_CHANNEL(1, "adc1"),
 421         ADC_CHANNEL(2, "adc2"),
 422         ADC_CHANNEL(3, "adc3"),
 423         ADC_CHANNEL(4, "adc4"),
 424         ADC_CHANNEL(5, "adc5"),
 425         ADC_CHANNEL(6, "adc6"),
 426         ADC_CHANNEL(7, "adc7"),
 427         ADC_CHANNEL(8, "adc8"),
 428         ADC_CHANNEL(9, "adc9"),
 429 };
 430
 431 static int exynos_adc_remove_devices(struct device *dev, void *c)
 432 {
 433         struct platform_device *pdev = to_platform_device(dev);
 434
 435         platform_device_unregister(pdev);
 436
 437         return 0;
 438 }
 439
 440 static int exynos_adc_probe(struct platform_device *pdev)
 441 {
 442         struct exynos_adc *info = NULL;
 443         struct device_node *np = pdev->dev.of_node;
 444         struct iio_dev *indio_dev = NULL;
 445         struct resource *mem;
 446         int ret = -ENODEV;
 447         int irq;
 448
 449         if (!np)
 450                 return ret;
 451
 452         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
 453         if (!indio_dev) {
 454                 dev_err(&pdev->dev, "failed allocating iio device\n");
 455                 return -ENOMEM;
 456         }
 457
 458         info = iio_priv(indio_dev);
 459
 460         info->data = exynos_adc_get_data(pdev);
 461         if (!info->data) {
 462                 dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
 463                 return -EINVAL;
 464         }
 465
 466         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 467         info->regs = devm_ioremap_resource(&pdev->dev, mem);
 468         if (IS_ERR(info->regs))
 469                 return PTR_ERR(info->regs);
 470
 471         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 472         info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
 473         if (IS_ERR(info->enable_reg))
 474                 return PTR_ERR(info->enable_reg);
 475
 476         irq = platform_get_irq(pdev, 0);
 477         if (irq < 0) {
 478                 dev_err(&pdev->dev, "no irq resource?\n");
 479                 return irq;
 480         }
 481
 482         info->irq = irq;
 483         info->dev = &pdev->dev;
 484
 485         init_completion(&info->completion);
 486
 487         info->clk = devm_clk_get(&pdev->dev, "adc");
 488         if (IS_ERR(info->clk)) {
 489                 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
 490                                                         PTR_ERR(info->clk));
 491                 return PTR_ERR(info->clk);
 492         }
 493
 494         if (info->data->needs_sclk) {
 495                 info->sclk = devm_clk_get(&pdev->dev, "sclk");
 496                 if (IS_ERR(info->sclk)) {
 497                         dev_err(&pdev->dev,
 498                                 "failed getting sclk clock, err = %ld\n",
 499                                 PTR_ERR(info->sclk));
 500                         return PTR_ERR(info->sclk);
 501                 }
 502         }
 503
 504         info->vdd = devm_regulator_get(&pdev->dev, "vdd");
 505         if (IS_ERR(info->vdd)) {
 506                 dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
 507                                                         PTR_ERR(info->vdd));
 508                 return PTR_ERR(info->vdd);
 509         }
 510
 511         ret = regulator_enable(info->vdd);
 512         if (ret)
 513                 return ret;
 514
 515         ret = exynos_adc_prepare_clk(info);
 516         if (ret)
 517                 goto err_disable_reg;
 518
 519         ret = exynos_adc_enable_clk(info);
 520         if (ret)
 521                 goto err_unprepare_clk;
 522
 523         platform_set_drvdata(pdev, indio_dev);
 524
 525         indio_dev->name = dev_name(&pdev->dev);
 526         indio_dev->dev.parent = &pdev->dev;
 527         indio_dev->dev.of_node = pdev->dev.of_node;
 528         indio_dev->info = &exynos_adc_iio_info;
 529         indio_dev->modes = INDIO_DIRECT_MODE;
 530         indio_dev->channels = exynos_adc_iio_channels;
 531         indio_dev->num_channels = info->data->num_channels;
 532
 533         ret = request_irq(info->irq, exynos_adc_isr,
 534                                         0, dev_name(&pdev->dev), info);
 535         if (ret < 0) {
 536                 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
 537                                                         info->irq);
 538                 goto err_disable_clk;
 539         }
 540
 541         ret = iio_device_register(indio_dev);
 542         if (ret)
 543                 goto err_irq;
 544
 545         if (info->data->init_hw)
 546                 info->data->init_hw(info);
 547
 548         ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
 549         if (ret < 0) {
 550                 dev_err(&pdev->dev, "failed adding child nodes\n");
 551                 goto err_of_populate;
 552         }
 553
 554         return 0;
 555
 556 err_of_populate:
 557         device_for_each_child(&indio_dev->dev, NULL,
 558                                 exynos_adc_remove_devices);
 559         iio_device_unregister(indio_dev);
 560 err_irq:
 561         free_irq(info->irq, info);
 562 err_disable_clk:
 563         if (info->data->exit_hw)
 564                 info->data->exit_hw(info);
 565         exynos_adc_disable_clk(info);
 566 err_unprepare_clk:
 567         exynos_adc_unprepare_clk(info);
 568 err_disable_reg:
 569         regulator_disable(info->vdd);
 570         return ret;
 571 }
 572
 573 static int exynos_adc_remove(struct platform_device *pdev)
 574 {
 575         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 576         struct exynos_adc *info = iio_priv(indio_dev);
 577
 578         device_for_each_child(&indio_dev->dev, NULL,
 579                                 exynos_adc_remove_devices);
 580         iio_device_unregister(indio_dev);
 581         free_irq(info->irq, info);
 582         if (info->data->exit_hw)
 583                 info->data->exit_hw(info);
 584         exynos_adc_disable_clk(info);
 585         exynos_adc_unprepare_clk(info);
 586         regulator_disable(info->vdd);
 587
 588         return 0;
 589 }
 590
 591 #ifdef CONFIG_PM_SLEEP
 592 static int exynos_adc_suspend(struct device *dev)
 593 {
 594         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 595         struct exynos_adc *info = iio_priv(indio_dev);
 596
 597         if (info->data->exit_hw)
 598                 info->data->exit_hw(info);
 599         exynos_adc_disable_clk(info);
 600         regulator_disable(info->vdd);
 601
 602         return 0;
 603 }
 604
 605 static int exynos_adc_resume(struct device *dev)
 606 {
 607         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 608         struct exynos_adc *info = iio_priv(indio_dev);
 609         int ret;
 610
 611         ret = regulator_enable(info->vdd);
 612         if (ret)
 613                 return ret;
 614
 615         ret = exynos_adc_enable_clk(info);
 616         if (ret)
 617                 return ret;
 618
 619         if (info->data->init_hw)
 620                 info->data->init_hw(info);
 621
 622         return 0;
 623 }
 624 #endif
 625
 626 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
 627                         exynos_adc_suspend,
 628                         exynos_adc_resume);
 629
 630 static struct platform_driver exynos_adc_driver = {
 631         .probe          = exynos_adc_probe,
 632         .remove         = exynos_adc_remove,
 633         .driver         = {
 634                 .name   = "exynos-adc",
 635                 .owner  = THIS_MODULE,
 636                 .of_match_table = exynos_adc_match,
 637                 .pm     = &exynos_adc_pm_ops,
 638         },
 639 };
 640
 641 module_platform_driver(exynos_adc_driver);
 642
 643 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
 644 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
 645 MODULE_LICENSE("GPL v2");