2 * exynos_adc.c - Support for ADC in EXYNOS SoCs
4 * 8 ~ 10 channel, 10/12-bit ADC
6 * Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/slab.h>
31 #include <linux/clk.h>
32 #include <linux/completion.h>
34 #include <linux/of_irq.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/of_platform.h>
37 #include <linux/err.h>
39 #include <linux/iio/iio.h>
40 #include <linux/iio/machine.h>
41 #include <linux/iio/driver.h>
43 /* EXYNOS4412/5250 ADC_V1 registers definitions */
44 #define ADC_V1_CON(x) ((x) + 0x00)
45 #define ADC_V1_DLY(x) ((x) + 0x08)
46 #define ADC_V1_DATX(x) ((x) + 0x0C)
47 #define ADC_V1_INTCLR(x) ((x) + 0x18)
48 #define ADC_V1_MUX(x) ((x) + 0x1c)
50 /* Future ADC_V2 registers definitions */
51 #define ADC_V2_CON1(x) ((x) + 0x00)
52 #define ADC_V2_CON2(x) ((x) + 0x04)
53 #define ADC_V2_STAT(x) ((x) + 0x08)
54 #define ADC_V2_INT_EN(x) ((x) + 0x10)
55 #define ADC_V2_INT_ST(x) ((x) + 0x14)
56 #define ADC_V2_VER(x) ((x) + 0x20)
58 /* Bit definitions for ADC_V1 */
59 #define ADC_V1_CON_RES (1u << 16)
60 #define ADC_V1_CON_PRSCEN (1u << 14)
61 #define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
62 #define ADC_V1_CON_STANDBY (1u << 2)
64 /* Bit definitions for ADC_V2 */
65 #define ADC_V2_CON1_SOFT_RESET (1u << 2)
67 #define ADC_V2_CON2_OSEL (1u << 10)
68 #define ADC_V2_CON2_ESEL (1u << 9)
69 #define ADC_V2_CON2_HIGHF (1u << 8)
70 #define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4)
71 #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0)
72 #define ADC_V2_CON2_ACH_MASK 0xF
74 #define MAX_ADC_V2_CHANNELS 10
75 #define MAX_ADC_V1_CHANNELS 8
76 #define MAX_EXYNOS3250_ADC_CHANNELS 2
78 /* Bit definitions common for ADC_V1 and ADC_V2 */
79 #define ADC_CON_EN_START (1u << 0)
80 #define ADC_DATX_MASK 0xFFF
82 #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
85 struct exynos_adc_data *data;
88 void __iomem *enable_reg;
92 struct regulator *vdd;
94 struct completion completion;
100 struct exynos_adc_data {
104 void (*init_hw)(struct exynos_adc *info);
105 void (*exit_hw)(struct exynos_adc *info);
106 void (*clear_irq)(struct exynos_adc *info);
107 void (*start_conv)(struct exynos_adc *info, unsigned long addr);
110 static void exynos_adc_unprepare_clk(struct exynos_adc *info)
112 if (info->data->needs_sclk)
113 clk_unprepare(info->sclk);
114 clk_unprepare(info->clk);
117 static int exynos_adc_prepare_clk(struct exynos_adc *info)
121 ret = clk_prepare(info->clk);
123 dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
127 if (info->data->needs_sclk) {
128 ret = clk_prepare(info->sclk);
130 clk_unprepare(info->clk);
132 "failed preparing sclk_adc clock: %d\n", ret);
140 static void exynos_adc_disable_clk(struct exynos_adc *info)
142 if (info->data->needs_sclk)
143 clk_disable(info->sclk);
144 clk_disable(info->clk);
147 static int exynos_adc_enable_clk(struct exynos_adc *info)
151 ret = clk_enable(info->clk);
153 dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
157 if (info->data->needs_sclk) {
158 ret = clk_enable(info->sclk);
160 clk_disable(info->clk);
162 "failed enabling sclk_adc clock: %d\n", ret);
170 static void exynos_adc_v1_init_hw(struct exynos_adc *info)
174 writel(1, info->enable_reg);
176 /* set default prescaler values and Enable prescaler */
177 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
179 /* Enable 12-bit ADC resolution */
180 con1 |= ADC_V1_CON_RES;
181 writel(con1, ADC_V1_CON(info->regs));
184 static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
188 writel(0, info->enable_reg);
190 con = readl(ADC_V1_CON(info->regs));
191 con |= ADC_V1_CON_STANDBY;
192 writel(con, ADC_V1_CON(info->regs));
195 static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
197 writel(1, ADC_V1_INTCLR(info->regs));
200 static void exynos_adc_v1_start_conv(struct exynos_adc *info,
205 writel(addr, ADC_V1_MUX(info->regs));
207 con1 = readl(ADC_V1_CON(info->regs));
208 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
211 static const struct exynos_adc_data exynos_adc_v1_data = {
212 .num_channels = MAX_ADC_V1_CHANNELS,
214 .init_hw = exynos_adc_v1_init_hw,
215 .exit_hw = exynos_adc_v1_exit_hw,
216 .clear_irq = exynos_adc_v1_clear_irq,
217 .start_conv = exynos_adc_v1_start_conv,
220 static void exynos_adc_v2_init_hw(struct exynos_adc *info)
224 writel(1, info->enable_reg);
226 con1 = ADC_V2_CON1_SOFT_RESET;
227 writel(con1, ADC_V2_CON1(info->regs));
229 con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
230 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
231 writel(con2, ADC_V2_CON2(info->regs));
233 /* Enable interrupts */
234 writel(1, ADC_V2_INT_EN(info->regs));
237 static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
241 writel(0, info->enable_reg);
243 con = readl(ADC_V2_CON1(info->regs));
244 con &= ~ADC_CON_EN_START;
245 writel(con, ADC_V2_CON1(info->regs));
248 static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
250 writel(1, ADC_V2_INT_ST(info->regs));
253 static void exynos_adc_v2_start_conv(struct exynos_adc *info,
258 con2 = readl(ADC_V2_CON2(info->regs));
259 con2 &= ~ADC_V2_CON2_ACH_MASK;
260 con2 |= ADC_V2_CON2_ACH_SEL(addr);
261 writel(con2, ADC_V2_CON2(info->regs));
263 con1 = readl(ADC_V2_CON1(info->regs));
264 writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
267 static const struct exynos_adc_data exynos_adc_v2_data = {
268 .num_channels = MAX_ADC_V2_CHANNELS,
270 .init_hw = exynos_adc_v2_init_hw,
271 .exit_hw = exynos_adc_v2_exit_hw,
272 .clear_irq = exynos_adc_v2_clear_irq,
273 .start_conv = exynos_adc_v2_start_conv,
276 static const struct exynos_adc_data exynos3250_adc_data = {
277 .num_channels = MAX_EXYNOS3250_ADC_CHANNELS,
280 .init_hw = exynos_adc_v2_init_hw,
281 .exit_hw = exynos_adc_v2_exit_hw,
282 .clear_irq = exynos_adc_v2_clear_irq,
283 .start_conv = exynos_adc_v2_start_conv,
286 static const struct of_device_id exynos_adc_match[] = {
288 .compatible = "samsung,exynos-adc-v1",
289 .data = &exynos_adc_v1_data,
291 .compatible = "samsung,exynos-adc-v2",
292 .data = &exynos_adc_v2_data,
294 .compatible = "samsung,exynos3250-adc",
295 .data = &exynos3250_adc_data,
299 MODULE_DEVICE_TABLE(of, exynos_adc_match);
301 static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
303 const struct of_device_id *match;
305 match = of_match_node(exynos_adc_match, pdev->dev.of_node);
306 return (struct exynos_adc_data *)match->data;
309 static int exynos_read_raw(struct iio_dev *indio_dev,
310 struct iio_chan_spec const *chan,
315 struct exynos_adc *info = iio_priv(indio_dev);
316 unsigned long timeout;
319 if (mask != IIO_CHAN_INFO_RAW)
322 mutex_lock(&indio_dev->mlock);
323 reinit_completion(&info->completion);
325 /* Select the channel to be used and Trigger conversion */
326 if (info->data->start_conv)
327 info->data->start_conv(info, chan->address);
329 timeout = wait_for_completion_timeout
330 (&info->completion, EXYNOS_ADC_TIMEOUT);
332 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
333 if (info->data->init_hw)
334 info->data->init_hw(info);
342 mutex_unlock(&indio_dev->mlock);
347 static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
349 struct exynos_adc *info = (struct exynos_adc *)dev_id;
352 info->value = readl(ADC_V1_DATX(info->regs)) & ADC_DATX_MASK;
355 if (info->data->clear_irq)
356 info->data->clear_irq(info);
358 complete(&info->completion);
363 static int exynos_adc_reg_access(struct iio_dev *indio_dev,
364 unsigned reg, unsigned writeval,
367 struct exynos_adc *info = iio_priv(indio_dev);
372 *readval = readl(info->regs + reg);
377 static const struct iio_info exynos_adc_iio_info = {
378 .read_raw = &exynos_read_raw,
379 .debugfs_reg_access = &exynos_adc_reg_access,
380 .driver_module = THIS_MODULE,
383 #define ADC_CHANNEL(_index, _id) { \
384 .type = IIO_VOLTAGE, \
388 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
389 .datasheet_name = _id, \
392 static const struct iio_chan_spec exynos_adc_iio_channels[] = {
393 ADC_CHANNEL(0, "adc0"),
394 ADC_CHANNEL(1, "adc1"),
395 ADC_CHANNEL(2, "adc2"),
396 ADC_CHANNEL(3, "adc3"),
397 ADC_CHANNEL(4, "adc4"),
398 ADC_CHANNEL(5, "adc5"),
399 ADC_CHANNEL(6, "adc6"),
400 ADC_CHANNEL(7, "adc7"),
401 ADC_CHANNEL(8, "adc8"),
402 ADC_CHANNEL(9, "adc9"),
405 static int exynos_adc_remove_devices(struct device *dev, void *c)
407 struct platform_device *pdev = to_platform_device(dev);
409 platform_device_unregister(pdev);
414 static int exynos_adc_probe(struct platform_device *pdev)
416 struct exynos_adc *info = NULL;
417 struct device_node *np = pdev->dev.of_node;
418 struct iio_dev *indio_dev = NULL;
419 struct resource *mem;
426 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
428 dev_err(&pdev->dev, "failed allocating iio device\n");
432 info = iio_priv(indio_dev);
434 info->data = exynos_adc_get_data(pdev);
436 dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
440 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
441 info->regs = devm_ioremap_resource(&pdev->dev, mem);
442 if (IS_ERR(info->regs))
443 return PTR_ERR(info->regs);
445 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
446 info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
447 if (IS_ERR(info->enable_reg))
448 return PTR_ERR(info->enable_reg);
450 irq = platform_get_irq(pdev, 0);
452 dev_err(&pdev->dev, "no irq resource?\n");
457 info->dev = &pdev->dev;
459 init_completion(&info->completion);
461 info->clk = devm_clk_get(&pdev->dev, "adc");
462 if (IS_ERR(info->clk)) {
463 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
465 return PTR_ERR(info->clk);
468 if (info->data->needs_sclk) {
469 info->sclk = devm_clk_get(&pdev->dev, "sclk");
470 if (IS_ERR(info->sclk)) {
472 "failed getting sclk clock, err = %ld\n",
473 PTR_ERR(info->sclk));
474 return PTR_ERR(info->sclk);
478 info->vdd = devm_regulator_get(&pdev->dev, "vdd");
479 if (IS_ERR(info->vdd)) {
480 dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
482 return PTR_ERR(info->vdd);
485 ret = regulator_enable(info->vdd);
489 ret = exynos_adc_prepare_clk(info);
491 goto err_disable_reg;
493 ret = exynos_adc_enable_clk(info);
495 goto err_unprepare_clk;
497 platform_set_drvdata(pdev, indio_dev);
499 indio_dev->name = dev_name(&pdev->dev);
500 indio_dev->dev.parent = &pdev->dev;
501 indio_dev->dev.of_node = pdev->dev.of_node;
502 indio_dev->info = &exynos_adc_iio_info;
503 indio_dev->modes = INDIO_DIRECT_MODE;
504 indio_dev->channels = exynos_adc_iio_channels;
505 indio_dev->num_channels = info->data->num_channels;
507 ret = request_irq(info->irq, exynos_adc_isr,
508 0, dev_name(&pdev->dev), info);
510 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
512 goto err_disable_clk;
515 ret = iio_device_register(indio_dev);
519 if (info->data->init_hw)
520 info->data->init_hw(info);
522 ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
524 dev_err(&pdev->dev, "failed adding child nodes\n");
525 goto err_of_populate;
531 device_for_each_child(&indio_dev->dev, NULL,
532 exynos_adc_remove_devices);
533 iio_device_unregister(indio_dev);
535 free_irq(info->irq, info);
537 if (info->data->exit_hw)
538 info->data->exit_hw(info);
539 exynos_adc_disable_clk(info);
541 exynos_adc_unprepare_clk(info);
543 regulator_disable(info->vdd);
547 static int exynos_adc_remove(struct platform_device *pdev)
549 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
550 struct exynos_adc *info = iio_priv(indio_dev);
552 device_for_each_child(&indio_dev->dev, NULL,
553 exynos_adc_remove_devices);
554 iio_device_unregister(indio_dev);
555 free_irq(info->irq, info);
556 if (info->data->exit_hw)
557 info->data->exit_hw(info);
558 exynos_adc_disable_clk(info);
559 exynos_adc_unprepare_clk(info);
560 regulator_disable(info->vdd);
565 #ifdef CONFIG_PM_SLEEP
566 static int exynos_adc_suspend(struct device *dev)
568 struct iio_dev *indio_dev = dev_get_drvdata(dev);
569 struct exynos_adc *info = iio_priv(indio_dev);
571 if (info->data->exit_hw)
572 info->data->exit_hw(info);
573 exynos_adc_disable_clk(info);
574 regulator_disable(info->vdd);
579 static int exynos_adc_resume(struct device *dev)
581 struct iio_dev *indio_dev = dev_get_drvdata(dev);
582 struct exynos_adc *info = iio_priv(indio_dev);
585 ret = regulator_enable(info->vdd);
589 ret = exynos_adc_enable_clk(info);
593 if (info->data->init_hw)
594 info->data->init_hw(info);
600 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
604 static struct platform_driver exynos_adc_driver = {
605 .probe = exynos_adc_probe,
606 .remove = exynos_adc_remove,
608 .name = "exynos-adc",
609 .owner = THIS_MODULE,
610 .of_match_table = exynos_adc_match,
611 .pm = &exynos_adc_pm_ops,
615 module_platform_driver(exynos_adc_driver);
617 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
618 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
619 MODULE_LICENSE("GPL v2");