drivers/iio/adc/exynos_adc.c

   1 /*
   2  *  exynos_adc.c - Support for ADC in EXYNOS SoCs
   3  *
   4  *  8 ~ 10 channel, 10/12-bit ADC
   5  *
   6  *  Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/kernel.h>
  29 #include <linux/slab.h>
  30 #include <linux/io.h>
  31 #include <linux/clk.h>
  32 #include <linux/completion.h>
  33 #include <linux/of.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/err.h>
  38
  39 #include <linux/iio/iio.h>
  40 #include <linux/iio/machine.h>
  41 #include <linux/iio/driver.h>
  42 #include <linux/mfd/syscon.h>
  43 #include <linux/regmap.h>
  44
  45 /* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
  46 #define ADC_V1_CON(x)           ((x) + 0x00)
  47 #define ADC_V1_DLY(x)           ((x) + 0x08)
  48 #define ADC_V1_DATX(x)          ((x) + 0x0C)
  49 #define ADC_V1_INTCLR(x)        ((x) + 0x18)
  50 #define ADC_V1_MUX(x)           ((x) + 0x1c)
  51
  52 /* S3C2410 ADC registers definitions */
  53 #define ADC_S3C2410_MUX(x)      ((x) + 0x18)
  54
  55 /* Future ADC_V2 registers definitions */
  56 #define ADC_V2_CON1(x)          ((x) + 0x00)
  57 #define ADC_V2_CON2(x)          ((x) + 0x04)
  58 #define ADC_V2_STAT(x)          ((x) + 0x08)
  59 #define ADC_V2_INT_EN(x)        ((x) + 0x10)
  60 #define ADC_V2_INT_ST(x)        ((x) + 0x14)
  61 #define ADC_V2_VER(x)           ((x) + 0x20)
  62
  63 /* Bit definitions for ADC_V1 */
  64 #define ADC_V1_CON_RES          (1u << 16)
  65 #define ADC_V1_CON_PRSCEN       (1u << 14)
  66 #define ADC_V1_CON_PRSCLV(x)    (((x) & 0xFF) << 6)
  67 #define ADC_V1_CON_STANDBY      (1u << 2)
  68
  69 /* Bit definitions for S3C2410 ADC */
  70 #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
  71 #define ADC_S3C2410_DATX_MASK   0x3FF
  72 #define ADC_S3C2416_CON_RES_SEL (1u << 3)
  73
  74 /* Bit definitions for ADC_V2 */
  75 #define ADC_V2_CON1_SOFT_RESET  (1u << 2)
  76
  77 #define ADC_V2_CON2_OSEL        (1u << 10)
  78 #define ADC_V2_CON2_ESEL        (1u << 9)
  79 #define ADC_V2_CON2_HIGHF       (1u << 8)
  80 #define ADC_V2_CON2_C_TIME(x)   (((x) & 7) << 4)
  81 #define ADC_V2_CON2_ACH_SEL(x)  (((x) & 0xF) << 0)
  82 #define ADC_V2_CON2_ACH_MASK    0xF
  83
  84 #define MAX_ADC_V2_CHANNELS             10
  85 #define MAX_ADC_V1_CHANNELS             8
  86 #define MAX_EXYNOS3250_ADC_CHANNELS     2
  87
  88 /* Bit definitions common for ADC_V1 and ADC_V2 */
  89 #define ADC_CON_EN_START        (1u << 0)
  90 #define ADC_CON_EN_START_MASK   (0x3 << 0)
  91 #define ADC_DATX_MASK           0xFFF
  92
  93 #define EXYNOS_ADC_TIMEOUT      (msecs_to_jiffies(100))
  94
  95 #define EXYNOS_ADCV1_PHY_OFFSET 0x0718
  96 #define EXYNOS_ADCV2_PHY_OFFSET 0x0720
  97
  98 struct exynos_adc {
  99         struct exynos_adc_data  *data;
 100         struct device           *dev;
 101         void __iomem            *regs;
 102         struct regmap           *pmu_map;
 103         struct clk              *clk;
 104         struct clk              *sclk;
 105         unsigned int            irq;
 106         struct regulator        *vdd;
 107
 108         struct completion       completion;
 109
 110         u32                     value;
 111         unsigned int            version;
 112 };
 113
 114 struct exynos_adc_data {
 115         int num_channels;
 116         bool needs_sclk;
 117         bool needs_adc_phy;
 118         int phy_offset;
 119         u32 mask;
 120
 121         void (*init_hw)(struct exynos_adc *info);
 122         void (*exit_hw)(struct exynos_adc *info);
 123         void (*clear_irq)(struct exynos_adc *info);
 124         void (*start_conv)(struct exynos_adc *info, unsigned long addr);
 125 };
 126
 127 static void exynos_adc_unprepare_clk(struct exynos_adc *info)
 128 {
 129         if (info->data->needs_sclk)
 130                 clk_unprepare(info->sclk);
 131         clk_unprepare(info->clk);
 132 }
 133
 134 static int exynos_adc_prepare_clk(struct exynos_adc *info)
 135 {
 136         int ret;
 137
 138         ret = clk_prepare(info->clk);
 139         if (ret) {
 140                 dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
 141                 return ret;
 142         }
 143
 144         if (info->data->needs_sclk) {
 145                 ret = clk_prepare(info->sclk);
 146                 if (ret) {
 147                         clk_unprepare(info->clk);
 148                         dev_err(info->dev,
 149                                 "failed preparing sclk_adc clock: %d\n", ret);
 150                         return ret;
 151                 }
 152         }
 153
 154         return 0;
 155 }
 156
 157 static void exynos_adc_disable_clk(struct exynos_adc *info)
 158 {
 159         if (info->data->needs_sclk)
 160                 clk_disable(info->sclk);
 161         clk_disable(info->clk);
 162 }
 163
 164 static int exynos_adc_enable_clk(struct exynos_adc *info)
 165 {
 166         int ret;
 167
 168         ret = clk_enable(info->clk);
 169         if (ret) {
 170                 dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
 171                 return ret;
 172         }
 173
 174         if (info->data->needs_sclk) {
 175                 ret = clk_enable(info->sclk);
 176                 if (ret) {
 177                         clk_disable(info->clk);
 178                         dev_err(info->dev,
 179                                 "failed enabling sclk_adc clock: %d\n", ret);
 180                         return ret;
 181                 }
 182         }
 183
 184         return 0;
 185 }
 186
 187 static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 188 {
 189         u32 con1;
 190
 191         if (info->data->needs_adc_phy)
 192                 regmap_write(info->pmu_map, info->data->phy_offset, 1);
 193
 194         /* set default prescaler values and Enable prescaler */
 195         con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 196
 197         /* Enable 12-bit ADC resolution */
 198         con1 |= ADC_V1_CON_RES;
 199         writel(con1, ADC_V1_CON(info->regs));
 200 }
 201
 202 static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
 203 {
 204         u32 con;
 205
 206         if (info->data->needs_adc_phy)
 207                 regmap_write(info->pmu_map, info->data->phy_offset, 0);
 208
 209         con = readl(ADC_V1_CON(info->regs));
 210         con |= ADC_V1_CON_STANDBY;
 211         writel(con, ADC_V1_CON(info->regs));
 212 }
 213
 214 static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
 215 {
 216         writel(1, ADC_V1_INTCLR(info->regs));
 217 }
 218
 219 static void exynos_adc_v1_start_conv(struct exynos_adc *info,
 220                                      unsigned long addr)
 221 {
 222         u32 con1;
 223
 224         writel(addr, ADC_V1_MUX(info->regs));
 225
 226         con1 = readl(ADC_V1_CON(info->regs));
 227         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 228 }
 229
 230 static const struct exynos_adc_data exynos_adc_v1_data = {
 231         .num_channels   = MAX_ADC_V1_CHANNELS,
 232         .mask           = ADC_DATX_MASK,        /* 12 bit ADC resolution */
 233         .needs_adc_phy  = true,
 234         .phy_offset     = EXYNOS_ADCV1_PHY_OFFSET,
 235
 236         .init_hw        = exynos_adc_v1_init_hw,
 237         .exit_hw        = exynos_adc_v1_exit_hw,
 238         .clear_irq      = exynos_adc_v1_clear_irq,
 239         .start_conv     = exynos_adc_v1_start_conv,
 240 };
 241
 242 static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
 243                                           unsigned long addr)
 244 {
 245         u32 con1;
 246
 247         /* Enable 12 bit ADC resolution */
 248         con1 = readl(ADC_V1_CON(info->regs));
 249         con1 |= ADC_S3C2416_CON_RES_SEL;
 250         writel(con1, ADC_V1_CON(info->regs));
 251
 252         /* Select channel for S3C2416 */
 253         writel(addr, ADC_S3C2410_MUX(info->regs));
 254
 255         con1 = readl(ADC_V1_CON(info->regs));
 256         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 257 }
 258
 259 static struct exynos_adc_data const exynos_adc_s3c2416_data = {
 260         .num_channels   = MAX_ADC_V1_CHANNELS,
 261         .mask           = ADC_DATX_MASK,        /* 12 bit ADC resolution */
 262
 263         .init_hw        = exynos_adc_v1_init_hw,
 264         .exit_hw        = exynos_adc_v1_exit_hw,
 265         .start_conv     = exynos_adc_s3c2416_start_conv,
 266 };
 267
 268 static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
 269                                           unsigned long addr)
 270 {
 271         u32 con1;
 272
 273         /* Select channel for S3C2433 */
 274         writel(addr, ADC_S3C2410_MUX(info->regs));
 275
 276         con1 = readl(ADC_V1_CON(info->regs));
 277         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 278 }
 279
 280 static struct exynos_adc_data const exynos_adc_s3c2443_data = {
 281         .num_channels   = MAX_ADC_V1_CHANNELS,
 282         .mask           = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
 283
 284         .init_hw        = exynos_adc_v1_init_hw,
 285         .exit_hw        = exynos_adc_v1_exit_hw,
 286         .start_conv     = exynos_adc_s3c2443_start_conv,
 287 };
 288
 289 static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
 290                                           unsigned long addr)
 291 {
 292         u32 con1;
 293
 294         con1 = readl(ADC_V1_CON(info->regs));
 295         con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
 296         con1 |= ADC_S3C2410_CON_SELMUX(addr);
 297         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 298 }
 299
 300 static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
 301         .num_channels   = MAX_ADC_V1_CHANNELS,
 302         .mask           = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
 303
 304         .init_hw        = exynos_adc_v1_init_hw,
 305         .exit_hw        = exynos_adc_v1_exit_hw,
 306         .start_conv     = exynos_adc_s3c64xx_start_conv,
 307 };
 308
 309 static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
 310         .num_channels   = MAX_ADC_V1_CHANNELS,
 311         .mask           = ADC_DATX_MASK,        /* 12 bit ADC resolution */
 312
 313         .init_hw        = exynos_adc_v1_init_hw,
 314         .exit_hw        = exynos_adc_v1_exit_hw,
 315         .clear_irq      = exynos_adc_v1_clear_irq,
 316         .start_conv     = exynos_adc_s3c64xx_start_conv,
 317 };
 318
 319 static void exynos_adc_v2_init_hw(struct exynos_adc *info)
 320 {
 321         u32 con1, con2;
 322
 323         if (info->data->needs_adc_phy)
 324                 regmap_write(info->pmu_map, info->data->phy_offset, 1);
 325
 326         con1 = ADC_V2_CON1_SOFT_RESET;
 327         writel(con1, ADC_V2_CON1(info->regs));
 328
 329         con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 330                 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 331         writel(con2, ADC_V2_CON2(info->regs));
 332
 333         /* Enable interrupts */
 334         writel(1, ADC_V2_INT_EN(info->regs));
 335 }
 336
 337 static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
 338 {
 339         u32 con;
 340
 341         if (info->data->needs_adc_phy)
 342                 regmap_write(info->pmu_map, info->data->phy_offset, 0);
 343
 344         con = readl(ADC_V2_CON1(info->regs));
 345         con &= ~ADC_CON_EN_START;
 346         writel(con, ADC_V2_CON1(info->regs));
 347 }
 348
 349 static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
 350 {
 351         writel(1, ADC_V2_INT_ST(info->regs));
 352 }
 353
 354 static void exynos_adc_v2_start_conv(struct exynos_adc *info,
 355                                      unsigned long addr)
 356 {
 357         u32 con1, con2;
 358
 359         con2 = readl(ADC_V2_CON2(info->regs));
 360         con2 &= ~ADC_V2_CON2_ACH_MASK;
 361         con2 |= ADC_V2_CON2_ACH_SEL(addr);
 362         writel(con2, ADC_V2_CON2(info->regs));
 363
 364         con1 = readl(ADC_V2_CON1(info->regs));
 365         writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
 366 }
 367
 368 static const struct exynos_adc_data exynos_adc_v2_data = {
 369         .num_channels   = MAX_ADC_V2_CHANNELS,
 370         .mask           = ADC_DATX_MASK, /* 12 bit ADC resolution */
 371         .needs_adc_phy  = true,
 372         .phy_offset     = EXYNOS_ADCV2_PHY_OFFSET,
 373
 374         .init_hw        = exynos_adc_v2_init_hw,
 375         .exit_hw        = exynos_adc_v2_exit_hw,
 376         .clear_irq      = exynos_adc_v2_clear_irq,
 377         .start_conv     = exynos_adc_v2_start_conv,
 378 };
 379
 380 static const struct exynos_adc_data exynos3250_adc_data = {
 381         .num_channels   = MAX_EXYNOS3250_ADC_CHANNELS,
 382         .mask           = ADC_DATX_MASK, /* 12 bit ADC resolution */
 383         .needs_sclk     = true,
 384         .needs_adc_phy  = true,
 385         .phy_offset     = EXYNOS_ADCV1_PHY_OFFSET,
 386
 387         .init_hw        = exynos_adc_v2_init_hw,
 388         .exit_hw        = exynos_adc_v2_exit_hw,
 389         .clear_irq      = exynos_adc_v2_clear_irq,
 390         .start_conv     = exynos_adc_v2_start_conv,
 391 };
 392
 393 static const struct of_device_id exynos_adc_match[] = {
 394         {
 395                 .compatible = "samsung,s3c2410-adc",
 396                 .data = &exynos_adc_s3c24xx_data,
 397         }, {
 398                 .compatible = "samsung,s3c2416-adc",
 399                 .data = &exynos_adc_s3c2416_data,
 400         }, {
 401                 .compatible = "samsung,s3c2440-adc",
 402                 .data = &exynos_adc_s3c24xx_data,
 403         }, {
 404                 .compatible = "samsung,s3c2443-adc",
 405                 .data = &exynos_adc_s3c2443_data,
 406         }, {
 407                 .compatible = "samsung,s3c6410-adc",
 408                 .data = &exynos_adc_s3c64xx_data,
 409         }, {
 410                 .compatible = "samsung,exynos-adc-v1",
 411                 .data = &exynos_adc_v1_data,
 412         }, {
 413                 .compatible = "samsung,exynos-adc-v2",
 414                 .data = &exynos_adc_v2_data,
 415         }, {
 416                 .compatible = "samsung,exynos3250-adc",
 417                 .data = &exynos3250_adc_data,
 418         },
 419         {},
 420 };
 421 MODULE_DEVICE_TABLE(of, exynos_adc_match);
 422
 423 static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
 424 {
 425         const struct of_device_id *match;
 426
 427         match = of_match_node(exynos_adc_match, pdev->dev.of_node);
 428         return (struct exynos_adc_data *)match->data;
 429 }
 430
 431 static int exynos_read_raw(struct iio_dev *indio_dev,
 432                                 struct iio_chan_spec const *chan,
 433                                 int *val,
 434                                 int *val2,
 435                                 long mask)
 436 {
 437         struct exynos_adc *info = iio_priv(indio_dev);
 438         unsigned long timeout;
 439         int ret;
 440
 441         if (mask != IIO_CHAN_INFO_RAW)
 442                 return -EINVAL;
 443
 444         mutex_lock(&indio_dev->mlock);
 445         reinit_completion(&info->completion);
 446
 447         /* Select the channel to be used and Trigger conversion */
 448         if (info->data->start_conv)
 449                 info->data->start_conv(info, chan->address);
 450
 451         timeout = wait_for_completion_timeout
 452                         (&info->completion, EXYNOS_ADC_TIMEOUT);
 453         if (timeout == 0) {
 454                 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
 455                 if (info->data->init_hw)
 456                         info->data->init_hw(info);
 457                 ret = -ETIMEDOUT;
 458         } else {
 459                 *val = info->value;
 460                 *val2 = 0;
 461                 ret = IIO_VAL_INT;
 462         }
 463
 464         mutex_unlock(&indio_dev->mlock);
 465
 466         return ret;
 467 }
 468
 469 static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
 470 {
 471         struct exynos_adc *info = (struct exynos_adc *)dev_id;
 472         u32 mask = info->data->mask;
 473
 474         /* Read value */
 475         info->value = readl(ADC_V1_DATX(info->regs)) & mask;
 476
 477         /* clear irq */
 478         if (info->data->clear_irq)
 479                 info->data->clear_irq(info);
 480
 481         complete(&info->completion);
 482
 483         return IRQ_HANDLED;
 484 }
 485
 486 static int exynos_adc_reg_access(struct iio_dev *indio_dev,
 487                               unsigned reg, unsigned writeval,
 488                               unsigned *readval)
 489 {
 490         struct exynos_adc *info = iio_priv(indio_dev);
 491
 492         if (readval == NULL)
 493                 return -EINVAL;
 494
 495         *readval = readl(info->regs + reg);
 496
 497         return 0;
 498 }
 499
 500 static const struct iio_info exynos_adc_iio_info = {
 501         .read_raw = &exynos_read_raw,
 502         .debugfs_reg_access = &exynos_adc_reg_access,
 503         .driver_module = THIS_MODULE,
 504 };
 505
 506 #define ADC_CHANNEL(_index, _id) {                      \
 507         .type = IIO_VOLTAGE,                            \
 508         .indexed = 1,                                   \
 509         .channel = _index,                              \
 510         .address = _index,                              \
 511         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
 512         .datasheet_name = _id,                          \
 513 }
 514
 515 static const struct iio_chan_spec exynos_adc_iio_channels[] = {
 516         ADC_CHANNEL(0, "adc0"),
 517         ADC_CHANNEL(1, "adc1"),
 518         ADC_CHANNEL(2, "adc2"),
 519         ADC_CHANNEL(3, "adc3"),
 520         ADC_CHANNEL(4, "adc4"),
 521         ADC_CHANNEL(5, "adc5"),
 522         ADC_CHANNEL(6, "adc6"),
 523         ADC_CHANNEL(7, "adc7"),
 524         ADC_CHANNEL(8, "adc8"),
 525         ADC_CHANNEL(9, "adc9"),
 526 };
 527
 528 static int exynos_adc_remove_devices(struct device *dev, void *c)
 529 {
 530         struct platform_device *pdev = to_platform_device(dev);
 531
 532         platform_device_unregister(pdev);
 533
 534         return 0;
 535 }
 536
 537 static int exynos_adc_probe(struct platform_device *pdev)
 538 {
 539         struct exynos_adc *info = NULL;
 540         struct device_node *np = pdev->dev.of_node;
 541         struct iio_dev *indio_dev = NULL;
 542         struct resource *mem;
 543         int ret = -ENODEV;
 544         int irq;
 545
 546         if (!np)
 547                 return ret;
 548
 549         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
 550         if (!indio_dev) {
 551                 dev_err(&pdev->dev, "failed allocating iio device\n");
 552                 return -ENOMEM;
 553         }
 554
 555         info = iio_priv(indio_dev);
 556
 557         info->data = exynos_adc_get_data(pdev);
 558         if (!info->data) {
 559                 dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
 560                 return -EINVAL;
 561         }
 562
 563         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 564         info->regs = devm_ioremap_resource(&pdev->dev, mem);
 565         if (IS_ERR(info->regs))
 566                 return PTR_ERR(info->regs);
 567
 568
 569         if (info->data->needs_adc_phy) {
 570                 info->pmu_map = syscon_regmap_lookup_by_phandle(
 571                                         pdev->dev.of_node,
 572                                         "samsung,syscon-phandle");
 573                 if (IS_ERR(info->pmu_map)) {
 574                         dev_err(&pdev->dev, "syscon regmap lookup failed.\n");
 575                         return PTR_ERR(info->pmu_map);
 576                 }
 577         }
 578
 579         irq = platform_get_irq(pdev, 0);
 580         if (irq < 0) {
 581                 dev_err(&pdev->dev, "no irq resource?\n");
 582                 return irq;
 583         }
 584
 585         info->irq = irq;
 586         info->dev = &pdev->dev;
 587
 588         init_completion(&info->completion);
 589
 590         info->clk = devm_clk_get(&pdev->dev, "adc");
 591         if (IS_ERR(info->clk)) {
 592                 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
 593                                                         PTR_ERR(info->clk));
 594                 return PTR_ERR(info->clk);
 595         }
 596
 597         if (info->data->needs_sclk) {
 598                 info->sclk = devm_clk_get(&pdev->dev, "sclk");
 599                 if (IS_ERR(info->sclk)) {
 600                         dev_err(&pdev->dev,
 601                                 "failed getting sclk clock, err = %ld\n",
 602                                 PTR_ERR(info->sclk));
 603                         return PTR_ERR(info->sclk);
 604                 }
 605         }
 606
 607         info->vdd = devm_regulator_get(&pdev->dev, "vdd");
 608         if (IS_ERR(info->vdd)) {
 609                 dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
 610                                                         PTR_ERR(info->vdd));
 611                 return PTR_ERR(info->vdd);
 612         }
 613
 614         ret = regulator_enable(info->vdd);
 615         if (ret)
 616                 return ret;
 617
 618         ret = exynos_adc_prepare_clk(info);
 619         if (ret)
 620                 goto err_disable_reg;
 621
 622         ret = exynos_adc_enable_clk(info);
 623         if (ret)
 624                 goto err_unprepare_clk;
 625
 626         platform_set_drvdata(pdev, indio_dev);
 627
 628         indio_dev->name = dev_name(&pdev->dev);
 629         indio_dev->dev.parent = &pdev->dev;
 630         indio_dev->dev.of_node = pdev->dev.of_node;
 631         indio_dev->info = &exynos_adc_iio_info;
 632         indio_dev->modes = INDIO_DIRECT_MODE;
 633         indio_dev->channels = exynos_adc_iio_channels;
 634         indio_dev->num_channels = info->data->num_channels;
 635
 636         ret = request_irq(info->irq, exynos_adc_isr,
 637                                         0, dev_name(&pdev->dev), info);
 638         if (ret < 0) {
 639                 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
 640                                                         info->irq);
 641                 goto err_disable_clk;
 642         }
 643
 644         ret = iio_device_register(indio_dev);
 645         if (ret)
 646                 goto err_irq;
 647
 648         if (info->data->init_hw)
 649                 info->data->init_hw(info);
 650
 651         ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
 652         if (ret < 0) {
 653                 dev_err(&pdev->dev, "failed adding child nodes\n");
 654                 goto err_of_populate;
 655         }
 656
 657         return 0;
 658
 659 err_of_populate:
 660         device_for_each_child(&indio_dev->dev, NULL,
 661                                 exynos_adc_remove_devices);
 662         iio_device_unregister(indio_dev);
 663 err_irq:
 664         free_irq(info->irq, info);
 665 err_disable_clk:
 666         if (info->data->exit_hw)
 667                 info->data->exit_hw(info);
 668         exynos_adc_disable_clk(info);
 669 err_unprepare_clk:
 670         exynos_adc_unprepare_clk(info);
 671 err_disable_reg:
 672         regulator_disable(info->vdd);
 673         return ret;
 674 }
 675
 676 static int exynos_adc_remove(struct platform_device *pdev)
 677 {
 678         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 679         struct exynos_adc *info = iio_priv(indio_dev);
 680
 681         device_for_each_child(&indio_dev->dev, NULL,
 682                                 exynos_adc_remove_devices);
 683         iio_device_unregister(indio_dev);
 684         free_irq(info->irq, info);
 685         if (info->data->exit_hw)
 686                 info->data->exit_hw(info);
 687         exynos_adc_disable_clk(info);
 688         exynos_adc_unprepare_clk(info);
 689         regulator_disable(info->vdd);
 690
 691         return 0;
 692 }
 693
 694 #ifdef CONFIG_PM_SLEEP
 695 static int exynos_adc_suspend(struct device *dev)
 696 {
 697         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 698         struct exynos_adc *info = iio_priv(indio_dev);
 699
 700         if (info->data->exit_hw)
 701                 info->data->exit_hw(info);
 702         exynos_adc_disable_clk(info);
 703         regulator_disable(info->vdd);
 704
 705         return 0;
 706 }
 707
 708 static int exynos_adc_resume(struct device *dev)
 709 {
 710         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 711         struct exynos_adc *info = iio_priv(indio_dev);
 712         int ret;
 713
 714         ret = regulator_enable(info->vdd);
 715         if (ret)
 716                 return ret;
 717
 718         ret = exynos_adc_enable_clk(info);
 719         if (ret)
 720                 return ret;
 721
 722         if (info->data->init_hw)
 723                 info->data->init_hw(info);
 724
 725         return 0;
 726 }
 727 #endif
 728
 729 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
 730                         exynos_adc_suspend,
 731                         exynos_adc_resume);
 732
 733 static struct platform_driver exynos_adc_driver = {
 734         .probe          = exynos_adc_probe,
 735         .remove         = exynos_adc_remove,
 736         .driver         = {
 737                 .name   = "exynos-adc",
 738                 .of_match_table = exynos_adc_match,
 739                 .pm     = &exynos_adc_pm_ops,
 740         },
 741 };
 742
 743 module_platform_driver(exynos_adc_driver);
 744
 745 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
 746 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
 747 MODULE_LICENSE("GPL v2");