drivers/infiniband/hw/cxgb4/qp.c

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34
  35 #include "iw_cxgb4.h"
  36
  37 static int db_delay_usecs = 1;
  38 module_param(db_delay_usecs, int, 0644);
  39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
  40
  41 static int ocqp_support = 1;
  42 module_param(ocqp_support, int, 0644);
  43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
  44
  45 int db_fc_threshold = 1000;
  46 module_param(db_fc_threshold, int, 0644);
  47 MODULE_PARM_DESC(db_fc_threshold,
  48                  "QP count/threshold that triggers"
  49                  " automatic db flow control mode (default = 1000)");
  50
  51 int db_coalescing_threshold;
  52 module_param(db_coalescing_threshold, int, 0644);
  53 MODULE_PARM_DESC(db_coalescing_threshold,
  54                  "QP count/threshold that triggers"
  55                  " disabling db coalescing (default = 0)");
  56
  57 static int max_fr_immd = T4_MAX_FR_IMMD;
  58 module_param(max_fr_immd, int, 0644);
  59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
  60
  61 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  62 {
  63         unsigned long flag;
  64         spin_lock_irqsave(&qhp->lock, flag);
  65         qhp->attr.state = state;
  66         spin_unlock_irqrestore(&qhp->lock, flag);
  67 }
  68
  69 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  70 {
  71         c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
  72 }
  73
  74 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  75 {
  76         dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
  77                           pci_unmap_addr(sq, mapping));
  78 }
  79
  80 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  81 {
  82         if (t4_sq_onchip(sq))
  83                 dealloc_oc_sq(rdev, sq);
  84         else
  85                 dealloc_host_sq(rdev, sq);
  86 }
  87
  88 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  89 {
  90         if (!ocqp_support || !ocqp_supported(&rdev->lldi))
  91                 return -ENOSYS;
  92         sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
  93         if (!sq->dma_addr)
  94                 return -ENOMEM;
  95         sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
  96                         rdev->lldi.vr->ocq.start;
  97         sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
  98                                             rdev->lldi.vr->ocq.start);
  99         sq->flags |= T4_SQ_ONCHIP;
 100         return 0;
 101 }
 102
 103 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 104 {
 105         sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
 106                                        &(sq->dma_addr), GFP_KERNEL);
 107         if (!sq->queue)
 108                 return -ENOMEM;
 109         sq->phys_addr = virt_to_phys(sq->queue);
 110         pci_unmap_addr_set(sq, mapping, sq->dma_addr);
 111         return 0;
 112 }
 113
 114 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 115                       struct c4iw_dev_ucontext *uctx)
 116 {
 117         /*
 118          * uP clears EQ contexts when the connection exits rdma mode,
 119          * so no need to post a RESET WR for these EQs.
 120          */
 121         dma_free_coherent(&(rdev->lldi.pdev->dev),
 122                           wq->rq.memsize, wq->rq.queue,
 123                           dma_unmap_addr(&wq->rq, mapping));
 124         dealloc_sq(rdev, &wq->sq);
 125         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 126         kfree(wq->rq.sw_rq);
 127         kfree(wq->sq.sw_sq);
 128         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 129         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 130         return 0;
 131 }
 132
 133 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 134                      struct t4_cq *rcq, struct t4_cq *scq,
 135                      struct c4iw_dev_ucontext *uctx)
 136 {
 137         int user = (uctx != &rdev->uctx);
 138         struct fw_ri_res_wr *res_wr;
 139         struct fw_ri_res *res;
 140         int wr_len;
 141         struct c4iw_wr_wait wr_wait;
 142         struct sk_buff *skb;
 143         int ret = 0;
 144         int eqsize;
 145
 146         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
 147         if (!wq->sq.qid)
 148                 return -ENOMEM;
 149
 150         wq->rq.qid = c4iw_get_qpid(rdev, uctx);
 151         if (!wq->rq.qid) {
 152                 ret = -ENOMEM;
 153                 goto free_sq_qid;
 154         }
 155
 156         if (!user) {
 157                 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
 158                                  GFP_KERNEL);
 159                 if (!wq->sq.sw_sq) {
 160                         ret = -ENOMEM;
 161                         goto free_rq_qid;
 162                 }
 163
 164                 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
 165                                  GFP_KERNEL);
 166                 if (!wq->rq.sw_rq) {
 167                         ret = -ENOMEM;
 168                         goto free_sw_sq;
 169                 }
 170         }
 171
 172         /*
 173          * RQT must be a power of 2.
 174          */
 175         wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
 176         wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
 177         if (!wq->rq.rqt_hwaddr) {
 178                 ret = -ENOMEM;
 179                 goto free_sw_rq;
 180         }
 181
 182         if (user) {
 183                 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq))
 184                         goto free_hwaddr;
 185         } else {
 186                 ret = alloc_host_sq(rdev, &wq->sq);
 187                 if (ret)
 188                         goto free_hwaddr;
 189         }
 190
 191         memset(wq->sq.queue, 0, wq->sq.memsize);
 192         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
 193
 194         wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
 195                                           wq->rq.memsize, &(wq->rq.dma_addr),
 196                                           GFP_KERNEL);
 197         if (!wq->rq.queue) {
 198                 ret = -ENOMEM;
 199                 goto free_sq;
 200         }
 201         PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
 202                 __func__, wq->sq.queue,
 203                 (unsigned long long)virt_to_phys(wq->sq.queue),
 204                 wq->rq.queue,
 205                 (unsigned long long)virt_to_phys(wq->rq.queue));
 206         memset(wq->rq.queue, 0, wq->rq.memsize);
 207         dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
 208
 209         wq->db = rdev->lldi.db_reg;
 210         wq->gts = rdev->lldi.gts_reg;
 211         if (user) {
 212                 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
 213                                         (wq->sq.qid << rdev->qpshift);
 214                 wq->sq.udb &= PAGE_MASK;
 215                 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
 216                                         (wq->rq.qid << rdev->qpshift);
 217                 wq->rq.udb &= PAGE_MASK;
 218         }
 219         wq->rdev = rdev;
 220         wq->rq.msn = 1;
 221
 222         /* build fw_ri_res_wr */
 223         wr_len = sizeof *res_wr + 2 * sizeof *res;
 224
 225         skb = alloc_skb(wr_len, GFP_KERNEL);
 226         if (!skb) {
 227                 ret = -ENOMEM;
 228                 goto free_dma;
 229         }
 230         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
 231
 232         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
 233         memset(res_wr, 0, wr_len);
 234         res_wr->op_nres = cpu_to_be32(
 235                         FW_WR_OP(FW_RI_RES_WR) |
 236                         V_FW_RI_RES_WR_NRES(2) |
 237                         FW_WR_COMPL(1));
 238         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
 239         res_wr->cookie = (unsigned long) &wr_wait;
 240         res = res_wr->res;
 241         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 242         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 243
 244         /*
 245          * eqsize is the number of 64B entries plus the status page size.
 246          */
 247         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 248
 249         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 250                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 251                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 252                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 253                 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
 254                 V_FW_RI_RES_WR_IQID(scq->cqid));
 255         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 256                 V_FW_RI_RES_WR_DCAEN(0) |
 257                 V_FW_RI_RES_WR_DCACPU(0) |
 258                 V_FW_RI_RES_WR_FBMIN(2) |
 259                 V_FW_RI_RES_WR_FBMAX(2) |
 260                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 261                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 262                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 263         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
 264         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
 265         res++;
 266         res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
 267         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 268
 269         /*
 270          * eqsize is the number of 64B entries plus the status page size.
 271          */
 272         eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 273         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 274                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 275                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 276                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 277                 V_FW_RI_RES_WR_IQID(rcq->cqid));
 278         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 279                 V_FW_RI_RES_WR_DCAEN(0) |
 280                 V_FW_RI_RES_WR_DCACPU(0) |
 281                 V_FW_RI_RES_WR_FBMIN(2) |
 282                 V_FW_RI_RES_WR_FBMAX(2) |
 283                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 284                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 285                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 286         res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
 287         res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
 288
 289         c4iw_init_wr_wait(&wr_wait);
 290
 291         ret = c4iw_ofld_send(rdev, skb);
 292         if (ret)
 293                 goto free_dma;
 294         ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
 295         if (ret)
 296                 goto free_dma;
 297
 298         PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
 299              __func__, wq->sq.qid, wq->rq.qid, wq->db,
 300              (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
 301
 302         return 0;
 303 free_dma:
 304         dma_free_coherent(&(rdev->lldi.pdev->dev),
 305                           wq->rq.memsize, wq->rq.queue,
 306                           dma_unmap_addr(&wq->rq, mapping));
 307 free_sq:
 308         dealloc_sq(rdev, &wq->sq);
 309 free_hwaddr:
 310         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 311 free_sw_rq:
 312         kfree(wq->rq.sw_rq);
 313 free_sw_sq:
 314         kfree(wq->sq.sw_sq);
 315 free_rq_qid:
 316         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 317 free_sq_qid:
 318         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 319         return ret;
 320 }
 321
 322 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 323                       struct ib_send_wr *wr, int max, u32 *plenp)
 324 {
 325         u8 *dstp, *srcp;
 326         u32 plen = 0;
 327         int i;
 328         int rem, len;
 329
 330         dstp = (u8 *)immdp->data;
 331         for (i = 0; i < wr->num_sge; i++) {
 332                 if ((plen + wr->sg_list[i].length) > max)
 333                         return -EMSGSIZE;
 334                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
 335                 plen += wr->sg_list[i].length;
 336                 rem = wr->sg_list[i].length;
 337                 while (rem) {
 338                         if (dstp == (u8 *)&sq->queue[sq->size])
 339                                 dstp = (u8 *)sq->queue;
 340                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
 341                                 len = rem;
 342                         else
 343                                 len = (u8 *)&sq->queue[sq->size] - dstp;
 344                         memcpy(dstp, srcp, len);
 345                         dstp += len;
 346                         srcp += len;
 347                         rem -= len;
 348                 }
 349         }
 350         len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
 351         if (len)
 352                 memset(dstp, 0, len);
 353         immdp->op = FW_RI_DATA_IMMD;
 354         immdp->r1 = 0;
 355         immdp->r2 = 0;
 356         immdp->immdlen = cpu_to_be32(plen);
 357         *plenp = plen;
 358         return 0;
 359 }
 360
 361 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 362                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
 363                       int num_sge, u32 *plenp)
 364
 365 {
 366         int i;
 367         u32 plen = 0;
 368         __be64 *flitp = (__be64 *)isglp->sge;
 369
 370         for (i = 0; i < num_sge; i++) {
 371                 if ((plen + sg_list[i].length) < plen)
 372                         return -EMSGSIZE;
 373                 plen += sg_list[i].length;
 374                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
 375                                      sg_list[i].length);
 376                 if (++flitp == queue_end)
 377                         flitp = queue_start;
 378                 *flitp = cpu_to_be64(sg_list[i].addr);
 379                 if (++flitp == queue_end)
 380                         flitp = queue_start;
 381         }
 382         *flitp = (__force __be64)0;
 383         isglp->op = FW_RI_DATA_ISGL;
 384         isglp->r1 = 0;
 385         isglp->nsge = cpu_to_be16(num_sge);
 386         isglp->r2 = 0;
 387         if (plenp)
 388                 *plenp = plen;
 389         return 0;
 390 }
 391
 392 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
 393                            struct ib_send_wr *wr, u8 *len16)
 394 {
 395         u32 plen;
 396         int size;
 397         int ret;
 398
 399         if (wr->num_sge > T4_MAX_SEND_SGE)
 400                 return -EINVAL;
 401         switch (wr->opcode) {
 402         case IB_WR_SEND:
 403                 if (wr->send_flags & IB_SEND_SOLICITED)
 404                         wqe->send.sendop_pkd = cpu_to_be32(
 405                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
 406                 else
 407                         wqe->send.sendop_pkd = cpu_to_be32(
 408                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
 409                 wqe->send.stag_inv = 0;
 410                 break;
 411         case IB_WR_SEND_WITH_INV:
 412                 if (wr->send_flags & IB_SEND_SOLICITED)
 413                         wqe->send.sendop_pkd = cpu_to_be32(
 414                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
 415                 else
 416                         wqe->send.sendop_pkd = cpu_to_be32(
 417                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
 418                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 419                 break;
 420
 421         default:
 422                 return -EINVAL;
 423         }
 424
 425         plen = 0;
 426         if (wr->num_sge) {
 427                 if (wr->send_flags & IB_SEND_INLINE) {
 428                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
 429                                          T4_MAX_SEND_INLINE, &plen);
 430                         if (ret)
 431                                 return ret;
 432                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
 433                                plen;
 434                 } else {
 435                         ret = build_isgl((__be64 *)sq->queue,
 436                                          (__be64 *)&sq->queue[sq->size],
 437                                          wqe->send.u.isgl_src,
 438                                          wr->sg_list, wr->num_sge, &plen);
 439                         if (ret)
 440                                 return ret;
 441                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
 442                                wr->num_sge * sizeof(struct fw_ri_sge);
 443                 }
 444         } else {
 445                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
 446                 wqe->send.u.immd_src[0].r1 = 0;
 447                 wqe->send.u.immd_src[0].r2 = 0;
 448                 wqe->send.u.immd_src[0].immdlen = 0;
 449                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
 450                 plen = 0;
 451         }
 452         *len16 = DIV_ROUND_UP(size, 16);
 453         wqe->send.plen = cpu_to_be32(plen);
 454         return 0;
 455 }
 456
 457 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
 458                             struct ib_send_wr *wr, u8 *len16)
 459 {
 460         u32 plen;
 461         int size;
 462         int ret;
 463
 464         if (wr->num_sge > T4_MAX_SEND_SGE)
 465                 return -EINVAL;
 466         wqe->write.r2 = 0;
 467         wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
 468         wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
 469         if (wr->num_sge) {
 470                 if (wr->send_flags & IB_SEND_INLINE) {
 471                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
 472                                          T4_MAX_WRITE_INLINE, &plen);
 473                         if (ret)
 474                                 return ret;
 475                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
 476                                plen;
 477                 } else {
 478                         ret = build_isgl((__be64 *)sq->queue,
 479                                          (__be64 *)&sq->queue[sq->size],
 480                                          wqe->write.u.isgl_src,
 481                                          wr->sg_list, wr->num_sge, &plen);
 482                         if (ret)
 483                                 return ret;
 484                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
 485                                wr->num_sge * sizeof(struct fw_ri_sge);
 486                 }
 487         } else {
 488                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
 489                 wqe->write.u.immd_src[0].r1 = 0;
 490                 wqe->write.u.immd_src[0].r2 = 0;
 491                 wqe->write.u.immd_src[0].immdlen = 0;
 492                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
 493                 plen = 0;
 494         }
 495         *len16 = DIV_ROUND_UP(size, 16);
 496         wqe->write.plen = cpu_to_be32(plen);
 497         return 0;
 498 }
 499
 500 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
 501 {
 502         if (wr->num_sge > 1)
 503                 return -EINVAL;
 504         if (wr->num_sge) {
 505                 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
 506                 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
 507                                                         >> 32));
 508                 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
 509                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
 510                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
 511                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
 512                                                          >> 32));
 513                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
 514         } else {
 515                 wqe->read.stag_src = cpu_to_be32(2);
 516                 wqe->read.to_src_hi = 0;
 517                 wqe->read.to_src_lo = 0;
 518                 wqe->read.stag_sink = cpu_to_be32(2);
 519                 wqe->read.plen = 0;
 520                 wqe->read.to_sink_hi = 0;
 521                 wqe->read.to_sink_lo = 0;
 522         }
 523         wqe->read.r2 = 0;
 524         wqe->read.r5 = 0;
 525         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
 526         return 0;
 527 }
 528
 529 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
 530                            struct ib_recv_wr *wr, u8 *len16)
 531 {
 532         int ret;
 533
 534         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
 535                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
 536                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 537         if (ret)
 538                 return ret;
 539         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
 540                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 541         return 0;
 542 }
 543
 544 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
 545                          struct ib_send_wr *wr, u8 *len16, u8 t5dev)
 546 {
 547
 548         struct fw_ri_immd *imdp;
 549         __be64 *p;
 550         int i;
 551         int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
 552         int rem;
 553
 554         if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
 555                 return -EINVAL;
 556
 557         wqe->fr.qpbinde_to_dcacpu = 0;
 558         wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
 559         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
 560         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
 561         wqe->fr.len_hi = 0;
 562         wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
 563         wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
 564         wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
 565         wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
 566                                         0xffffffff);
 567
 568         if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
 569                 struct c4iw_fr_page_list *c4pl =
 570                         to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
 571                 struct fw_ri_dsgl *sglp;
 572
 573                 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
 574                         wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
 575                                 cpu_to_be64((u64)
 576                                 wr->wr.fast_reg.page_list->page_list[i]);
 577                 }
 578
 579                 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
 580                 sglp->op = FW_RI_DATA_DSGL;
 581                 sglp->r1 = 0;
 582                 sglp->nsge = cpu_to_be16(1);
 583                 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
 584                 sglp->len0 = cpu_to_be32(pbllen);
 585
 586                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
 587         } else {
 588                 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
 589                 imdp->op = FW_RI_DATA_IMMD;
 590                 imdp->r1 = 0;
 591                 imdp->r2 = 0;
 592                 imdp->immdlen = cpu_to_be32(pbllen);
 593                 p = (__be64 *)(imdp + 1);
 594                 rem = pbllen;
 595                 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
 596                         *p = cpu_to_be64(
 597                                 (u64)wr->wr.fast_reg.page_list->page_list[i]);
 598                         rem -= sizeof(*p);
 599                         if (++p == (__be64 *)&sq->queue[sq->size])
 600                                 p = (__be64 *)sq->queue;
 601                 }
 602                 BUG_ON(rem < 0);
 603                 while (rem) {
 604                         *p = 0;
 605                         rem -= sizeof(*p);
 606                         if (++p == (__be64 *)&sq->queue[sq->size])
 607                                 p = (__be64 *)sq->queue;
 608                 }
 609                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
 610                                       + pbllen, 16);
 611         }
 612         return 0;
 613 }
 614
 615 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
 616                           u8 *len16)
 617 {
 618         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 619         wqe->inv.r2 = 0;
 620         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 621         return 0;
 622 }
 623
 624 void c4iw_qp_add_ref(struct ib_qp *qp)
 625 {
 626         PDBG("%s ib_qp %p\n", __func__, qp);
 627         atomic_inc(&(to_c4iw_qp(qp)->refcnt));
 628 }
 629
 630 void c4iw_qp_rem_ref(struct ib_qp *qp)
 631 {
 632         PDBG("%s ib_qp %p\n", __func__, qp);
 633         if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
 634                 wake_up(&(to_c4iw_qp(qp)->wait));
 635 }
 636
 637 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 638                    struct ib_send_wr **bad_wr)
 639 {
 640         int err = 0;
 641         u8 len16 = 0;
 642         enum fw_wr_opcodes fw_opcode = 0;
 643         enum fw_ri_wr_flags fw_flags;
 644         struct c4iw_qp *qhp;
 645         union t4_wr *wqe;
 646         u32 num_wrs;
 647         struct t4_swsqe *swsqe;
 648         unsigned long flag;
 649         u16 idx = 0;
 650
 651         qhp = to_c4iw_qp(ibqp);
 652         spin_lock_irqsave(&qhp->lock, flag);
 653         if (t4_wq_in_error(&qhp->wq)) {
 654                 spin_unlock_irqrestore(&qhp->lock, flag);
 655                 return -EINVAL;
 656         }
 657         num_wrs = t4_sq_avail(&qhp->wq);
 658         if (num_wrs == 0) {
 659                 spin_unlock_irqrestore(&qhp->lock, flag);
 660                 return -ENOMEM;
 661         }
 662         while (wr) {
 663                 if (num_wrs == 0) {
 664                         err = -ENOMEM;
 665                         *bad_wr = wr;
 666                         break;
 667                 }
 668                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
 669                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
 670
 671                 fw_flags = 0;
 672                 if (wr->send_flags & IB_SEND_SOLICITED)
 673                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
 674                 if (wr->send_flags & IB_SEND_SIGNALED)
 675                         fw_flags |= FW_RI_COMPLETION_FLAG;
 676                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
 677                 switch (wr->opcode) {
 678                 case IB_WR_SEND_WITH_INV:
 679                 case IB_WR_SEND:
 680                         if (wr->send_flags & IB_SEND_FENCE)
 681                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
 682                         fw_opcode = FW_RI_SEND_WR;
 683                         if (wr->opcode == IB_WR_SEND)
 684                                 swsqe->opcode = FW_RI_SEND;
 685                         else
 686                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
 687                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
 688                         break;
 689                 case IB_WR_RDMA_WRITE:
 690                         fw_opcode = FW_RI_RDMA_WRITE_WR;
 691                         swsqe->opcode = FW_RI_RDMA_WRITE;
 692                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
 693                         break;
 694                 case IB_WR_RDMA_READ:
 695                 case IB_WR_RDMA_READ_WITH_INV:
 696                         fw_opcode = FW_RI_RDMA_READ_WR;
 697                         swsqe->opcode = FW_RI_READ_REQ;
 698                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
 699                                 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
 700                         else
 701                                 fw_flags = 0;
 702                         err = build_rdma_read(wqe, wr, &len16);
 703                         if (err)
 704                                 break;
 705                         swsqe->read_len = wr->sg_list[0].length;
 706                         if (!qhp->wq.sq.oldest_read)
 707                                 qhp->wq.sq.oldest_read = swsqe;
 708                         break;
 709                 case IB_WR_FAST_REG_MR:
 710                         fw_opcode = FW_RI_FR_NSMR_WR;
 711                         swsqe->opcode = FW_RI_FAST_REGISTER;
 712                         err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
 713                                             is_t5(
 714                                             qhp->rhp->rdev.lldi.adapter_type) ?
 715                                             1 : 0);
 716                         break;
 717                 case IB_WR_LOCAL_INV:
 718                         if (wr->send_flags & IB_SEND_FENCE)
 719                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
 720                         fw_opcode = FW_RI_INV_LSTAG_WR;
 721                         swsqe->opcode = FW_RI_LOCAL_INV;
 722                         err = build_inv_stag(wqe, wr, &len16);
 723                         break;
 724                 default:
 725                         PDBG("%s post of type=%d TBD!\n", __func__,
 726                              wr->opcode);
 727                         err = -EINVAL;
 728                 }
 729                 if (err) {
 730                         *bad_wr = wr;
 731                         break;
 732                 }
 733                 swsqe->idx = qhp->wq.sq.pidx;
 734                 swsqe->complete = 0;
 735                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
 736                 swsqe->wr_id = wr->wr_id;
 737
 738                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
 739
 740                 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
 741                      __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
 742                      swsqe->opcode, swsqe->read_len);
 743                 wr = wr->next;
 744                 num_wrs--;
 745                 t4_sq_produce(&qhp->wq, len16);
 746                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 747         }
 748         if (t4_wq_db_enabled(&qhp->wq))
 749                 t4_ring_sq_db(&qhp->wq, idx);
 750         spin_unlock_irqrestore(&qhp->lock, flag);
 751         return err;
 752 }
 753
 754 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 755                       struct ib_recv_wr **bad_wr)
 756 {
 757         int err = 0;
 758         struct c4iw_qp *qhp;
 759         union t4_recv_wr *wqe;
 760         u32 num_wrs;
 761         u8 len16 = 0;
 762         unsigned long flag;
 763         u16 idx = 0;
 764
 765         qhp = to_c4iw_qp(ibqp);
 766         spin_lock_irqsave(&qhp->lock, flag);
 767         if (t4_wq_in_error(&qhp->wq)) {
 768                 spin_unlock_irqrestore(&qhp->lock, flag);
 769                 return -EINVAL;
 770         }
 771         num_wrs = t4_rq_avail(&qhp->wq);
 772         if (num_wrs == 0) {
 773                 spin_unlock_irqrestore(&qhp->lock, flag);
 774                 return -ENOMEM;
 775         }
 776         while (wr) {
 777                 if (wr->num_sge > T4_MAX_RECV_SGE) {
 778                         err = -EINVAL;
 779                         *bad_wr = wr;
 780                         break;
 781                 }
 782                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
 783                                            qhp->wq.rq.wq_pidx *
 784                                            T4_EQ_ENTRY_SIZE);
 785                 if (num_wrs)
 786                         err = build_rdma_recv(qhp, wqe, wr, &len16);
 787                 else
 788                         err = -ENOMEM;
 789                 if (err) {
 790                         *bad_wr = wr;
 791                         break;
 792                 }
 793
 794                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
 795
 796                 wqe->recv.opcode = FW_RI_RECV_WR;
 797                 wqe->recv.r1 = 0;
 798                 wqe->recv.wrid = qhp->wq.rq.pidx;
 799                 wqe->recv.r2[0] = 0;
 800                 wqe->recv.r2[1] = 0;
 801                 wqe->recv.r2[2] = 0;
 802                 wqe->recv.len16 = len16;
 803                 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
 804                      (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
 805                 t4_rq_produce(&qhp->wq, len16);
 806                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 807                 wr = wr->next;
 808                 num_wrs--;
 809         }
 810         if (t4_wq_db_enabled(&qhp->wq))
 811                 t4_ring_rq_db(&qhp->wq, idx);
 812         spin_unlock_irqrestore(&qhp->lock, flag);
 813         return err;
 814 }
 815
 816 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
 817 {
 818         return -ENOSYS;
 819 }
 820
 821 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
 822                                     u8 *ecode)
 823 {
 824         int status;
 825         int tagged;
 826         int opcode;
 827         int rqtype;
 828         int send_inv;
 829
 830         if (!err_cqe) {
 831                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 832                 *ecode = 0;
 833                 return;
 834         }
 835
 836         status = CQE_STATUS(err_cqe);
 837         opcode = CQE_OPCODE(err_cqe);
 838         rqtype = RQ_TYPE(err_cqe);
 839         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
 840                    (opcode == FW_RI_SEND_WITH_SE_INV);
 841         tagged = (opcode == FW_RI_RDMA_WRITE) ||
 842                  (rqtype && (opcode == FW_RI_READ_RESP));
 843
 844         switch (status) {
 845         case T4_ERR_STAG:
 846                 if (send_inv) {
 847                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 848                         *ecode = RDMAP_CANT_INV_STAG;
 849                 } else {
 850                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 851                         *ecode = RDMAP_INV_STAG;
 852                 }
 853                 break;
 854         case T4_ERR_PDID:
 855                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 856                 if ((opcode == FW_RI_SEND_WITH_INV) ||
 857                     (opcode == FW_RI_SEND_WITH_SE_INV))
 858                         *ecode = RDMAP_CANT_INV_STAG;
 859                 else
 860                         *ecode = RDMAP_STAG_NOT_ASSOC;
 861                 break;
 862         case T4_ERR_QPID:
 863                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 864                 *ecode = RDMAP_STAG_NOT_ASSOC;
 865                 break;
 866         case T4_ERR_ACCESS:
 867                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 868                 *ecode = RDMAP_ACC_VIOL;
 869                 break;
 870         case T4_ERR_WRAP:
 871                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 872                 *ecode = RDMAP_TO_WRAP;
 873                 break;
 874         case T4_ERR_BOUND:
 875                 if (tagged) {
 876                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 877                         *ecode = DDPT_BASE_BOUNDS;
 878                 } else {
 879                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 880                         *ecode = RDMAP_BASE_BOUNDS;
 881                 }
 882                 break;
 883         case T4_ERR_INVALIDATE_SHARED_MR:
 884         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
 885                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 886                 *ecode = RDMAP_CANT_INV_STAG;
 887                 break;
 888         case T4_ERR_ECC:
 889         case T4_ERR_ECC_PSTAG:
 890         case T4_ERR_INTERNAL_ERR:
 891                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
 892                 *ecode = 0;
 893                 break;
 894         case T4_ERR_OUT_OF_RQE:
 895                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 896                 *ecode = DDPU_INV_MSN_NOBUF;
 897                 break;
 898         case T4_ERR_PBL_ADDR_BOUND:
 899                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 900                 *ecode = DDPT_BASE_BOUNDS;
 901                 break;
 902         case T4_ERR_CRC:
 903                 *layer_type = LAYER_MPA|DDP_LLP;
 904                 *ecode = MPA_CRC_ERR;
 905                 break;
 906         case T4_ERR_MARKER:
 907                 *layer_type = LAYER_MPA|DDP_LLP;
 908                 *ecode = MPA_MARKER_ERR;
 909                 break;
 910         case T4_ERR_PDU_LEN_ERR:
 911                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 912                 *ecode = DDPU_MSG_TOOBIG;
 913                 break;
 914         case T4_ERR_DDP_VERSION:
 915                 if (tagged) {
 916                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 917                         *ecode = DDPT_INV_VERS;
 918                 } else {
 919                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 920                         *ecode = DDPU_INV_VERS;
 921                 }
 922                 break;
 923         case T4_ERR_RDMA_VERSION:
 924                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 925                 *ecode = RDMAP_INV_VERS;
 926                 break;
 927         case T4_ERR_OPCODE:
 928                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 929                 *ecode = RDMAP_INV_OPCODE;
 930                 break;
 931         case T4_ERR_DDP_QUEUE_NUM:
 932                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 933                 *ecode = DDPU_INV_QN;
 934                 break;
 935         case T4_ERR_MSN:
 936         case T4_ERR_MSN_GAP:
 937         case T4_ERR_MSN_RANGE:
 938         case T4_ERR_IRD_OVERFLOW:
 939                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 940                 *ecode = DDPU_INV_MSN_RANGE;
 941                 break;
 942         case T4_ERR_TBIT:
 943                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
 944                 *ecode = 0;
 945                 break;
 946         case T4_ERR_MO:
 947                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 948                 *ecode = DDPU_INV_MO;
 949                 break;
 950         default:
 951                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 952                 *ecode = 0;
 953                 break;
 954         }
 955 }
 956
 957 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
 958                            gfp_t gfp)
 959 {
 960         struct fw_ri_wr *wqe;
 961         struct sk_buff *skb;
 962         struct terminate_message *term;
 963
 964         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
 965              qhp->ep->hwtid);
 966
 967         skb = alloc_skb(sizeof *wqe, gfp);
 968         if (!skb)
 969                 return;
 970         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
 971
 972         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
 973         memset(wqe, 0, sizeof *wqe);
 974         wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
 975         wqe->flowid_len16 = cpu_to_be32(
 976                 FW_WR_FLOWID(qhp->ep->hwtid) |
 977                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
 978
 979         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
 980         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
 981         term = (struct terminate_message *)wqe->u.terminate.termmsg;
 982         if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
 983                 term->layer_etype = qhp->attr.layer_etype;
 984                 term->ecode = qhp->attr.ecode;
 985         } else
 986                 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
 987         c4iw_ofld_send(&qhp->rhp->rdev, skb);
 988 }
 989
 990 /*
 991  * Assumes qhp lock is held.
 992  */
 993 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
 994                        struct c4iw_cq *schp)
 995 {
 996         int count;
 997         int flushed;
 998         unsigned long flag;
 999
1000         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1001
1002         /* locking hierarchy: cq lock first, then qp lock. */
1003         spin_lock_irqsave(&rchp->lock, flag);
1004         spin_lock(&qhp->lock);
1005         c4iw_flush_hw_cq(&rchp->cq);
1006         c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1007         flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1008         spin_unlock(&qhp->lock);
1009         spin_unlock_irqrestore(&rchp->lock, flag);
1010         if (flushed) {
1011                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1012                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1013                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1014         }
1015
1016         /* locking hierarchy: cq lock first, then qp lock. */
1017         spin_lock_irqsave(&schp->lock, flag);
1018         spin_lock(&qhp->lock);
1019         c4iw_flush_hw_cq(&schp->cq);
1020         c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
1021         flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
1022         spin_unlock(&qhp->lock);
1023         spin_unlock_irqrestore(&schp->lock, flag);
1024         if (flushed) {
1025                 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1026                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
1027                 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1028         }
1029 }
1030
1031 static void flush_qp(struct c4iw_qp *qhp)
1032 {
1033         struct c4iw_cq *rchp, *schp;
1034         unsigned long flag;
1035
1036         rchp = get_chp(qhp->rhp, qhp->attr.rcq);
1037         schp = get_chp(qhp->rhp, qhp->attr.scq);
1038
1039         if (qhp->ibqp.uobject) {
1040                 t4_set_wq_in_error(&qhp->wq);
1041                 t4_set_cq_in_error(&rchp->cq);
1042                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1043                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1044                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1045                 if (schp != rchp) {
1046                         t4_set_cq_in_error(&schp->cq);
1047                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1048                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1049                                         schp->ibcq.cq_context);
1050                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1051                 }
1052                 return;
1053         }
1054         __flush_qp(qhp, rchp, schp);
1055 }
1056
1057 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1058                      struct c4iw_ep *ep)
1059 {
1060         struct fw_ri_wr *wqe;
1061         int ret;
1062         struct sk_buff *skb;
1063
1064         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1065              ep->hwtid);
1066
1067         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1068         if (!skb)
1069                 return -ENOMEM;
1070         set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1071
1072         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1073         memset(wqe, 0, sizeof *wqe);
1074         wqe->op_compl = cpu_to_be32(
1075                 FW_WR_OP(FW_RI_INIT_WR) |
1076                 FW_WR_COMPL(1));
1077         wqe->flowid_len16 = cpu_to_be32(
1078                 FW_WR_FLOWID(ep->hwtid) |
1079                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1080         wqe->cookie = (unsigned long) &ep->com.wr_wait;
1081
1082         wqe->u.fini.type = FW_RI_TYPE_FINI;
1083         ret = c4iw_ofld_send(&rhp->rdev, skb);
1084         if (ret)
1085                 goto out;
1086
1087         ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1088                              qhp->wq.sq.qid, __func__);
1089 out:
1090         PDBG("%s ret %d\n", __func__, ret);
1091         return ret;
1092 }
1093
1094 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1095 {
1096         PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1097         memset(&init->u, 0, sizeof init->u);
1098         switch (p2p_type) {
1099         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1100                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1101                 init->u.write.stag_sink = cpu_to_be32(1);
1102                 init->u.write.to_sink = cpu_to_be64(1);
1103                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1104                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1105                                                    sizeof(struct fw_ri_immd),
1106                                                    16);
1107                 break;
1108         case FW_RI_INIT_P2PTYPE_READ_REQ:
1109                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1110                 init->u.read.stag_src = cpu_to_be32(1);
1111                 init->u.read.to_src_lo = cpu_to_be32(1);
1112                 init->u.read.stag_sink = cpu_to_be32(1);
1113                 init->u.read.to_sink_lo = cpu_to_be32(1);
1114                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1115                 break;
1116         }
1117 }
1118
1119 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1120 {
1121         struct fw_ri_wr *wqe;
1122         int ret;
1123         struct sk_buff *skb;
1124
1125         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1126              qhp->ep->hwtid);
1127
1128         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1129         if (!skb)
1130                 return -ENOMEM;
1131         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1132
1133         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1134         memset(wqe, 0, sizeof *wqe);
1135         wqe->op_compl = cpu_to_be32(
1136                 FW_WR_OP(FW_RI_INIT_WR) |
1137                 FW_WR_COMPL(1));
1138         wqe->flowid_len16 = cpu_to_be32(
1139                 FW_WR_FLOWID(qhp->ep->hwtid) |
1140                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1141
1142         wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1143
1144         wqe->u.init.type = FW_RI_TYPE_INIT;
1145         wqe->u.init.mpareqbit_p2ptype =
1146                 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1147                 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1148         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1149         if (qhp->attr.mpa_attr.recv_marker_enabled)
1150                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1151         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1152                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1153         if (qhp->attr.mpa_attr.crc_enabled)
1154                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1155
1156         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1157                             FW_RI_QP_RDMA_WRITE_ENABLE |
1158                             FW_RI_QP_BIND_ENABLE;
1159         if (!qhp->ibqp.uobject)
1160                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1161                                      FW_RI_QP_STAG0_ENABLE;
1162         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1163         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1164         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1165         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1166         wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1167         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1168         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1169         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1170         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1171         wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1172         wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1173         wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1174         wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1175                                          rhp->rdev.lldi.vr->rq.start);
1176         if (qhp->attr.mpa_attr.initiator)
1177                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1178
1179         ret = c4iw_ofld_send(&rhp->rdev, skb);
1180         if (ret)
1181                 goto out;
1182
1183         ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1184                                   qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1185 out:
1186         PDBG("%s ret %d\n", __func__, ret);
1187         return ret;
1188 }
1189
1190 /*
1191  * Called by the library when the qp has user dbs disabled due to
1192  * a DB_FULL condition.  This function will single-thread all user
1193  * DB rings to avoid overflowing the hw db-fifo.
1194  */
1195 static int ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 inc)
1196 {
1197         int delay = db_delay_usecs;
1198
1199         mutex_lock(&qhp->rhp->db_mutex);
1200         do {
1201
1202                 /*
1203                  * The interrupt threshold is dbfifo_int_thresh << 6. So
1204                  * make sure we don't cross that and generate an interrupt.
1205                  */
1206                 if (cxgb4_dbfifo_count(qhp->rhp->rdev.lldi.ports[0], 1) <
1207                     (qhp->rhp->rdev.lldi.dbfifo_int_thresh << 5)) {
1208                         writel(QID(qid) | PIDX(inc), qhp->wq.db);
1209                         break;
1210                 }
1211                 set_current_state(TASK_UNINTERRUPTIBLE);
1212                 schedule_timeout(usecs_to_jiffies(delay));
1213                 delay = min(delay << 1, 2000);
1214         } while (1);
1215         mutex_unlock(&qhp->rhp->db_mutex);
1216         return 0;
1217 }
1218
1219 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1220                    enum c4iw_qp_attr_mask mask,
1221                    struct c4iw_qp_attributes *attrs,
1222                    int internal)
1223 {
1224         int ret = 0;
1225         struct c4iw_qp_attributes newattr = qhp->attr;
1226         int disconnect = 0;
1227         int terminate = 0;
1228         int abort = 0;
1229         int free = 0;
1230         struct c4iw_ep *ep = NULL;
1231
1232         PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1233              qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1234              (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1235
1236         mutex_lock(&qhp->mutex);
1237
1238         /* Process attr changes if in IDLE */
1239         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1240                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1241                         ret = -EIO;
1242                         goto out;
1243                 }
1244                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1245                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1246                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1247                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1248                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1249                         newattr.enable_bind = attrs->enable_bind;
1250                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1251                         if (attrs->max_ord > c4iw_max_read_depth) {
1252                                 ret = -EINVAL;
1253                                 goto out;
1254                         }
1255                         newattr.max_ord = attrs->max_ord;
1256                 }
1257                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1258                         if (attrs->max_ird > c4iw_max_read_depth) {
1259                                 ret = -EINVAL;
1260                                 goto out;
1261                         }
1262                         newattr.max_ird = attrs->max_ird;
1263                 }
1264                 qhp->attr = newattr;
1265         }
1266
1267         if (mask & C4IW_QP_ATTR_SQ_DB) {
1268                 ret = ring_kernel_db(qhp, qhp->wq.sq.qid, attrs->sq_db_inc);
1269                 goto out;
1270         }
1271         if (mask & C4IW_QP_ATTR_RQ_DB) {
1272                 ret = ring_kernel_db(qhp, qhp->wq.rq.qid, attrs->rq_db_inc);
1273                 goto out;
1274         }
1275
1276         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1277                 goto out;
1278         if (qhp->attr.state == attrs->next_state)
1279                 goto out;
1280
1281         switch (qhp->attr.state) {
1282         case C4IW_QP_STATE_IDLE:
1283                 switch (attrs->next_state) {
1284                 case C4IW_QP_STATE_RTS:
1285                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1286                                 ret = -EINVAL;
1287                                 goto out;
1288                         }
1289                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1290                                 ret = -EINVAL;
1291                                 goto out;
1292                         }
1293                         qhp->attr.mpa_attr = attrs->mpa_attr;
1294                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1295                         qhp->ep = qhp->attr.llp_stream_handle;
1296                         set_state(qhp, C4IW_QP_STATE_RTS);
1297
1298                         /*
1299                          * Ref the endpoint here and deref when we
1300                          * disassociate the endpoint from the QP.  This
1301                          * happens in CLOSING->IDLE transition or *->ERROR
1302                          * transition.
1303                          */
1304                         c4iw_get_ep(&qhp->ep->com);
1305                         ret = rdma_init(rhp, qhp);
1306                         if (ret)
1307                                 goto err;
1308                         break;
1309                 case C4IW_QP_STATE_ERROR:
1310                         set_state(qhp, C4IW_QP_STATE_ERROR);
1311                         flush_qp(qhp);
1312                         break;
1313                 default:
1314                         ret = -EINVAL;
1315                         goto out;
1316                 }
1317                 break;
1318         case C4IW_QP_STATE_RTS:
1319                 switch (attrs->next_state) {
1320                 case C4IW_QP_STATE_CLOSING:
1321                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1322                         set_state(qhp, C4IW_QP_STATE_CLOSING);
1323                         ep = qhp->ep;
1324                         if (!internal) {
1325                                 abort = 0;
1326                                 disconnect = 1;
1327                                 c4iw_get_ep(&qhp->ep->com);
1328                         }
1329                         if (qhp->ibqp.uobject)
1330                                 t4_set_wq_in_error(&qhp->wq);
1331                         ret = rdma_fini(rhp, qhp, ep);
1332                         if (ret)
1333                                 goto err;
1334                         break;
1335                 case C4IW_QP_STATE_TERMINATE:
1336                         set_state(qhp, C4IW_QP_STATE_TERMINATE);
1337                         qhp->attr.layer_etype = attrs->layer_etype;
1338                         qhp->attr.ecode = attrs->ecode;
1339                         if (qhp->ibqp.uobject)
1340                                 t4_set_wq_in_error(&qhp->wq);
1341                         ep = qhp->ep;
1342                         if (!internal)
1343                                 terminate = 1;
1344                         disconnect = 1;
1345                         c4iw_get_ep(&qhp->ep->com);
1346                         break;
1347                 case C4IW_QP_STATE_ERROR:
1348                         set_state(qhp, C4IW_QP_STATE_ERROR);
1349                         if (qhp->ibqp.uobject)
1350                                 t4_set_wq_in_error(&qhp->wq);
1351                         if (!internal) {
1352                                 abort = 1;
1353                                 disconnect = 1;
1354                                 ep = qhp->ep;
1355                                 c4iw_get_ep(&qhp->ep->com);
1356                         }
1357                         goto err;
1358                         break;
1359                 default:
1360                         ret = -EINVAL;
1361                         goto out;
1362                 }
1363                 break;
1364         case C4IW_QP_STATE_CLOSING:
1365                 if (!internal) {
1366                         ret = -EINVAL;
1367                         goto out;
1368                 }
1369                 switch (attrs->next_state) {
1370                 case C4IW_QP_STATE_IDLE:
1371                         flush_qp(qhp);
1372                         set_state(qhp, C4IW_QP_STATE_IDLE);
1373                         qhp->attr.llp_stream_handle = NULL;
1374                         c4iw_put_ep(&qhp->ep->com);
1375                         qhp->ep = NULL;
1376                         wake_up(&qhp->wait);
1377                         break;
1378                 case C4IW_QP_STATE_ERROR:
1379                         goto err;
1380                 default:
1381                         ret = -EINVAL;
1382                         goto err;
1383                 }
1384                 break;
1385         case C4IW_QP_STATE_ERROR:
1386                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1387                         ret = -EINVAL;
1388                         goto out;
1389                 }
1390                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1391                         ret = -EINVAL;
1392                         goto out;
1393                 }
1394                 set_state(qhp, C4IW_QP_STATE_IDLE);
1395                 break;
1396         case C4IW_QP_STATE_TERMINATE:
1397                 if (!internal) {
1398                         ret = -EINVAL;
1399                         goto out;
1400                 }
1401                 goto err;
1402                 break;
1403         default:
1404                 printk(KERN_ERR "%s in a bad state %d\n",
1405                        __func__, qhp->attr.state);
1406                 ret = -EINVAL;
1407                 goto err;
1408                 break;
1409         }
1410         goto out;
1411 err:
1412         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1413              qhp->wq.sq.qid);
1414
1415         /* disassociate the LLP connection */
1416         qhp->attr.llp_stream_handle = NULL;
1417         if (!ep)
1418                 ep = qhp->ep;
1419         qhp->ep = NULL;
1420         set_state(qhp, C4IW_QP_STATE_ERROR);
1421         free = 1;
1422         abort = 1;
1423         wake_up(&qhp->wait);
1424         BUG_ON(!ep);
1425         flush_qp(qhp);
1426 out:
1427         mutex_unlock(&qhp->mutex);
1428
1429         if (terminate)
1430                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1431
1432         /*
1433          * If disconnect is 1, then we need to initiate a disconnect
1434          * on the EP.  This can be a normal close (RTS->CLOSING) or
1435          * an abnormal close (RTS/CLOSING->ERROR).
1436          */
1437         if (disconnect) {
1438                 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1439                                                          GFP_KERNEL);
1440                 c4iw_put_ep(&ep->com);
1441         }
1442
1443         /*
1444          * If free is 1, then we've disassociated the EP from the QP
1445          * and we need to dereference the EP.
1446          */
1447         if (free)
1448                 c4iw_put_ep(&ep->com);
1449         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1450         return ret;
1451 }
1452
1453 static int enable_qp_db(int id, void *p, void *data)
1454 {
1455         struct c4iw_qp *qp = p;
1456
1457         t4_enable_wq_db(&qp->wq);
1458         return 0;
1459 }
1460
1461 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1462 {
1463         struct c4iw_dev *rhp;
1464         struct c4iw_qp *qhp;
1465         struct c4iw_qp_attributes attrs;
1466         struct c4iw_ucontext *ucontext;
1467
1468         qhp = to_c4iw_qp(ib_qp);
1469         rhp = qhp->rhp;
1470
1471         attrs.next_state = C4IW_QP_STATE_ERROR;
1472         if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1473                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1474         else
1475                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1476         wait_event(qhp->wait, !qhp->ep);
1477
1478         spin_lock_irq(&rhp->lock);
1479         remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1480         rhp->qpcnt--;
1481         BUG_ON(rhp->qpcnt < 0);
1482         if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) {
1483                 rhp->rdev.stats.db_state_transitions++;
1484                 rhp->db_state = NORMAL;
1485                 idr_for_each(&rhp->qpidr, enable_qp_db, NULL);
1486         }
1487         if (db_coalescing_threshold >= 0)
1488                 if (rhp->qpcnt <= db_coalescing_threshold)
1489                         cxgb4_enable_db_coalescing(rhp->rdev.lldi.ports[0]);
1490         spin_unlock_irq(&rhp->lock);
1491         atomic_dec(&qhp->refcnt);
1492         wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1493
1494         ucontext = ib_qp->uobject ?
1495                    to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1496         destroy_qp(&rhp->rdev, &qhp->wq,
1497                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1498
1499         PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1500         kfree(qhp);
1501         return 0;
1502 }
1503
1504 static int disable_qp_db(int id, void *p, void *data)
1505 {
1506         struct c4iw_qp *qp = p;
1507
1508         t4_disable_wq_db(&qp->wq);
1509         return 0;
1510 }
1511
1512 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1513                              struct ib_udata *udata)
1514 {
1515         struct c4iw_dev *rhp;
1516         struct c4iw_qp *qhp;
1517         struct c4iw_pd *php;
1518         struct c4iw_cq *schp;
1519         struct c4iw_cq *rchp;
1520         struct c4iw_create_qp_resp uresp;
1521         int sqsize, rqsize;
1522         struct c4iw_ucontext *ucontext;
1523         int ret;
1524         struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1525
1526         PDBG("%s ib_pd %p\n", __func__, pd);
1527
1528         if (attrs->qp_type != IB_QPT_RC)
1529                 return ERR_PTR(-EINVAL);
1530
1531         php = to_c4iw_pd(pd);
1532         rhp = php->rhp;
1533         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1534         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1535         if (!schp || !rchp)
1536                 return ERR_PTR(-EINVAL);
1537
1538         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1539                 return ERR_PTR(-EINVAL);
1540
1541         rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1542         if (rqsize > T4_MAX_RQ_SIZE)
1543                 return ERR_PTR(-E2BIG);
1544
1545         sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1546         if (sqsize > T4_MAX_SQ_SIZE)
1547                 return ERR_PTR(-E2BIG);
1548
1549         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1550
1551
1552         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1553         if (!qhp)
1554                 return ERR_PTR(-ENOMEM);
1555         qhp->wq.sq.size = sqsize;
1556         qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1557         qhp->wq.rq.size = rqsize;
1558         qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1559
1560         if (ucontext) {
1561                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1562                 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1563         }
1564
1565         PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1566              __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1567
1568         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1569                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1570         if (ret)
1571                 goto err1;
1572
1573         attrs->cap.max_recv_wr = rqsize - 1;
1574         attrs->cap.max_send_wr = sqsize - 1;
1575         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1576
1577         qhp->rhp = rhp;
1578         qhp->attr.pd = php->pdid;
1579         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1580         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1581         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1582         qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1583         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1584         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1585         qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1586         qhp->attr.state = C4IW_QP_STATE_IDLE;
1587         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1588         qhp->attr.enable_rdma_read = 1;
1589         qhp->attr.enable_rdma_write = 1;
1590         qhp->attr.enable_bind = 1;
1591         qhp->attr.max_ord = 1;
1592         qhp->attr.max_ird = 1;
1593         spin_lock_init(&qhp->lock);
1594         mutex_init(&qhp->mutex);
1595         init_waitqueue_head(&qhp->wait);
1596         atomic_set(&qhp->refcnt, 1);
1597
1598         spin_lock_irq(&rhp->lock);
1599         if (rhp->db_state != NORMAL)
1600                 t4_disable_wq_db(&qhp->wq);
1601         rhp->qpcnt++;
1602         if (rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) {
1603                 rhp->rdev.stats.db_state_transitions++;
1604                 rhp->db_state = FLOW_CONTROL;
1605                 idr_for_each(&rhp->qpidr, disable_qp_db, NULL);
1606         }
1607         if (db_coalescing_threshold >= 0)
1608                 if (rhp->qpcnt > db_coalescing_threshold)
1609                         cxgb4_disable_db_coalescing(rhp->rdev.lldi.ports[0]);
1610         ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1611         spin_unlock_irq(&rhp->lock);
1612         if (ret)
1613                 goto err2;
1614
1615         if (udata) {
1616                 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1617                 if (!mm1) {
1618                         ret = -ENOMEM;
1619                         goto err3;
1620                 }
1621                 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1622                 if (!mm2) {
1623                         ret = -ENOMEM;
1624                         goto err4;
1625                 }
1626                 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1627                 if (!mm3) {
1628                         ret = -ENOMEM;
1629                         goto err5;
1630                 }
1631                 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1632                 if (!mm4) {
1633                         ret = -ENOMEM;
1634                         goto err6;
1635                 }
1636                 if (t4_sq_onchip(&qhp->wq.sq)) {
1637                         mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1638                         if (!mm5) {
1639                                 ret = -ENOMEM;
1640                                 goto err7;
1641                         }
1642                         uresp.flags = C4IW_QPF_ONCHIP;
1643                 } else
1644                         uresp.flags = 0;
1645                 uresp.qid_mask = rhp->rdev.qpmask;
1646                 uresp.sqid = qhp->wq.sq.qid;
1647                 uresp.sq_size = qhp->wq.sq.size;
1648                 uresp.sq_memsize = qhp->wq.sq.memsize;
1649                 uresp.rqid = qhp->wq.rq.qid;
1650                 uresp.rq_size = qhp->wq.rq.size;
1651                 uresp.rq_memsize = qhp->wq.rq.memsize;
1652                 spin_lock(&ucontext->mmap_lock);
1653                 if (mm5) {
1654                         uresp.ma_sync_key = ucontext->key;
1655                         ucontext->key += PAGE_SIZE;
1656                 }
1657                 uresp.sq_key = ucontext->key;
1658                 ucontext->key += PAGE_SIZE;
1659                 uresp.rq_key = ucontext->key;
1660                 ucontext->key += PAGE_SIZE;
1661                 uresp.sq_db_gts_key = ucontext->key;
1662                 ucontext->key += PAGE_SIZE;
1663                 uresp.rq_db_gts_key = ucontext->key;
1664                 ucontext->key += PAGE_SIZE;
1665                 spin_unlock(&ucontext->mmap_lock);
1666                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1667                 if (ret)
1668                         goto err8;
1669                 mm1->key = uresp.sq_key;
1670                 mm1->addr = qhp->wq.sq.phys_addr;
1671                 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1672                 insert_mmap(ucontext, mm1);
1673                 mm2->key = uresp.rq_key;
1674                 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1675                 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1676                 insert_mmap(ucontext, mm2);
1677                 mm3->key = uresp.sq_db_gts_key;
1678                 mm3->addr = qhp->wq.sq.udb;
1679                 mm3->len = PAGE_SIZE;
1680                 insert_mmap(ucontext, mm3);
1681                 mm4->key = uresp.rq_db_gts_key;
1682                 mm4->addr = qhp->wq.rq.udb;
1683                 mm4->len = PAGE_SIZE;
1684                 insert_mmap(ucontext, mm4);
1685                 if (mm5) {
1686                         mm5->key = uresp.ma_sync_key;
1687                         mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1688                                     + A_PCIE_MA_SYNC) & PAGE_MASK;
1689                         mm5->len = PAGE_SIZE;
1690                         insert_mmap(ucontext, mm5);
1691                 }
1692         }
1693         qhp->ibqp.qp_num = qhp->wq.sq.qid;
1694         init_timer(&(qhp->timer));
1695         PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1696              __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1697              qhp->wq.sq.qid);
1698         return &qhp->ibqp;
1699 err8:
1700         kfree(mm5);
1701 err7:
1702         kfree(mm4);
1703 err6:
1704         kfree(mm3);
1705 err5:
1706         kfree(mm2);
1707 err4:
1708         kfree(mm1);
1709 err3:
1710         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1711 err2:
1712         destroy_qp(&rhp->rdev, &qhp->wq,
1713                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1714 err1:
1715         kfree(qhp);
1716         return ERR_PTR(ret);
1717 }
1718
1719 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1720                       int attr_mask, struct ib_udata *udata)
1721 {
1722         struct c4iw_dev *rhp;
1723         struct c4iw_qp *qhp;
1724         enum c4iw_qp_attr_mask mask = 0;
1725         struct c4iw_qp_attributes attrs;
1726
1727         PDBG("%s ib_qp %p\n", __func__, ibqp);
1728
1729         /* iwarp does not support the RTR state */
1730         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1731                 attr_mask &= ~IB_QP_STATE;
1732
1733         /* Make sure we still have something left to do */
1734         if (!attr_mask)
1735                 return 0;
1736
1737         memset(&attrs, 0, sizeof attrs);
1738         qhp = to_c4iw_qp(ibqp);
1739         rhp = qhp->rhp;
1740
1741         attrs.next_state = c4iw_convert_state(attr->qp_state);
1742         attrs.enable_rdma_read = (attr->qp_access_flags &
1743                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
1744         attrs.enable_rdma_write = (attr->qp_access_flags &
1745                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1746         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1747
1748
1749         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1750         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1751                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1752                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1753                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1754
1755         /*
1756          * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1757          * ringing the queue db when we're in DB_FULL mode.
1758          */
1759         attrs.sq_db_inc = attr->sq_psn;
1760         attrs.rq_db_inc = attr->rq_psn;
1761         mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1762         mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1763
1764         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1765 }
1766
1767 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1768 {
1769         PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1770         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1771 }
1772
1773 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1774                      int attr_mask, struct ib_qp_init_attr *init_attr)
1775 {
1776         struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1777
1778         memset(attr, 0, sizeof *attr);
1779         memset(init_attr, 0, sizeof *init_attr);
1780         attr->qp_state = to_ib_qp_state(qhp->attr.state);
1781         return 0;
1782 }