2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include "t4fw_ri_api.h"
39 #define T4_MAX_NUM_PD 65536
40 #define T4_MAX_MR_SIZE (~0ULL)
41 #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
42 #define T4_STAG_UNSET 0xffffffff
44 #define PCIE_MA_SYNC_A 0x30b4
46 struct t4_status_page {
47 __be32 rsvd1; /* flit 0 - hw owns */
52 u8 qp_err; /* flit 1 - sw owns */
60 #define T4_EQ_ENTRY_SIZE 64
62 #define T4_SQ_NUM_SLOTS 5
63 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
64 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
65 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
66 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
67 sizeof(struct fw_ri_immd)))
68 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
69 sizeof(struct fw_ri_rdma_write_wr) - \
70 sizeof(struct fw_ri_immd)))
71 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
72 sizeof(struct fw_ri_rdma_write_wr) - \
73 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
74 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
75 sizeof(struct fw_ri_immd)) & ~31UL)
76 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
77 #define T4_MAX_FR_DSGL 1024
78 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
80 static inline int t4_max_fr_depth(int use_dsgl)
82 return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
85 #define T4_RQ_NUM_SLOTS 2
86 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
87 #define T4_MAX_RECV_SGE 4
90 struct fw_ri_res_wr res;
92 struct fw_ri_rdma_write_wr write;
93 struct fw_ri_send_wr send;
94 struct fw_ri_rdma_read_wr read;
95 struct fw_ri_bind_mw_wr bind;
96 struct fw_ri_fr_nsmr_wr fr;
97 struct fw_ri_inv_lstag_wr inv;
98 struct t4_status_page status;
99 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
103 struct fw_ri_recv_wr recv;
104 struct t4_status_page status;
105 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
108 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
109 enum fw_wr_opcodes opcode, u8 flags, u8 len16)
111 wqe->send.opcode = (u8)opcode;
112 wqe->send.flags = flags;
113 wqe->send.wrid = wrid;
117 wqe->send.len16 = len16;
120 /* CQE/AE status codes */
121 #define T4_ERR_SUCCESS 0x0
122 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */
123 /* STAG is offlimt, being 0, */
124 /* or STAG_key mismatch */
125 #define T4_ERR_PDID 0x2 /* PDID mismatch */
126 #define T4_ERR_QPID 0x3 /* QPID mismatch */
127 #define T4_ERR_ACCESS 0x4 /* Invalid access right */
128 #define T4_ERR_WRAP 0x5 /* Wrap error */
129 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */
130 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
131 /* shared memory region */
132 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
133 /* shared memory region */
134 #define T4_ERR_ECC 0x9 /* ECC error detected */
135 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
136 /* reading PSTAG for a MW */
138 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
140 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
141 #define T4_ERR_CRC 0x10 /* CRC error */
142 #define T4_ERR_MARKER 0x11 /* Marker error */
143 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
144 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
145 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
146 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
147 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
148 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
149 #define T4_ERR_MSN 0x18 /* MSN error */
150 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
151 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
153 #define T4_ERR_MSN_GAP 0x1B
154 #define T4_ERR_MSN_RANGE 0x1C
155 #define T4_ERR_IRD_OVERFLOW 0x1D
156 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
158 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
185 /* macros for flit 0 of the cqe */
187 #define CQE_QPID_S 12
188 #define CQE_QPID_M 0xFFFFF
189 #define CQE_QPID_G(x) ((((x) >> CQE_QPID_S)) & CQE_QPID_M)
190 #define CQE_QPID_V(x) ((x)<<CQE_QPID_S)
192 #define CQE_SWCQE_S 11
193 #define CQE_SWCQE_M 0x1
194 #define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M)
195 #define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S)
197 #define CQE_STATUS_S 5
198 #define CQE_STATUS_M 0x1F
199 #define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M)
200 #define CQE_STATUS_V(x) ((x)<<CQE_STATUS_S)
203 #define CQE_TYPE_M 0x1
204 #define CQE_TYPE_G(x) ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M)
205 #define CQE_TYPE_V(x) ((x)<<CQE_TYPE_S)
207 #define CQE_OPCODE_S 0
208 #define CQE_OPCODE_M 0xF
209 #define CQE_OPCODE_G(x) ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M)
210 #define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S)
212 #define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header)))
213 #define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header)))
214 #define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header)))
215 #define SQ_TYPE(x) (CQE_TYPE((x)))
216 #define RQ_TYPE(x) (!CQE_TYPE((x)))
217 #define CQE_STATUS(x) (CQE_STATUS_G(be32_to_cpu((x)->header)))
218 #define CQE_OPCODE(x) (CQE_OPCODE_G(be32_to_cpu((x)->header)))
220 #define CQE_SEND_OPCODE(x)( \
221 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
222 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
223 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
224 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
226 #define CQE_LEN(x) (be32_to_cpu((x)->len))
228 /* used for RQ completion processing */
229 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
230 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
232 /* used for SQ completion processing */
233 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
235 /* generic accessor macros */
236 #define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi))
237 #define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low))
239 /* macros for flit 3 of the cqe */
240 #define CQE_GENBIT_S 63
241 #define CQE_GENBIT_M 0x1
242 #define CQE_GENBIT_G(x) (((x) >> CQE_GENBIT_S) & CQE_GENBIT_M)
243 #define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S)
245 #define CQE_OVFBIT_S 62
246 #define CQE_OVFBIT_M 0x1
247 #define CQE_OVFBIT_G(x) ((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M)
249 #define CQE_IQTYPE_S 60
250 #define CQE_IQTYPE_M 0x3
251 #define CQE_IQTYPE_G(x) ((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M)
253 #define CQE_TS_M 0x0fffffffffffffffULL
254 #define CQE_TS_G(x) ((x) & CQE_TS_M)
256 #define CQE_OVFBIT(x) ((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts)))
257 #define CQE_GENBIT(x) ((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts)))
258 #define CQE_TS(x) (CQE_TS_G(be64_to_cpu((x)->bits_type_ts)))
269 struct timespec host_ts;
273 static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
275 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
276 return pgprot_writecombine(prot);
278 return pgprot_noncached(prot);
283 T4_SQ_ONCHIP = (1<<0),
289 DEFINE_DMA_UNMAP_ADDR(mapping);
290 unsigned long phys_addr;
291 struct t4_swsqe *sw_sq;
292 struct t4_swsqe *oldest_read;
308 struct timespec host_ts;
313 union t4_recv_wr *queue;
315 DEFINE_DMA_UNMAP_ADDR(mapping);
316 struct t4_swrqe *sw_rq;
336 struct c4iw_rdev *rdev;
340 static inline int t4_rqes_posted(struct t4_wq *wq)
342 return wq->rq.in_use;
345 static inline int t4_rq_empty(struct t4_wq *wq)
347 return wq->rq.in_use == 0;
350 static inline int t4_rq_full(struct t4_wq *wq)
352 return wq->rq.in_use == (wq->rq.size - 1);
355 static inline u32 t4_rq_avail(struct t4_wq *wq)
357 return wq->rq.size - 1 - wq->rq.in_use;
360 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
363 if (++wq->rq.pidx == wq->rq.size)
365 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
366 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
367 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
370 static inline void t4_rq_consume(struct t4_wq *wq)
374 if (++wq->rq.cidx == wq->rq.size)
378 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
380 return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
383 static inline u16 t4_rq_wq_size(struct t4_wq *wq)
385 return wq->rq.size * T4_RQ_NUM_SLOTS;
388 static inline int t4_sq_onchip(struct t4_sq *sq)
390 return sq->flags & T4_SQ_ONCHIP;
393 static inline int t4_sq_empty(struct t4_wq *wq)
395 return wq->sq.in_use == 0;
398 static inline int t4_sq_full(struct t4_wq *wq)
400 return wq->sq.in_use == (wq->sq.size - 1);
403 static inline u32 t4_sq_avail(struct t4_wq *wq)
405 return wq->sq.size - 1 - wq->sq.in_use;
408 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
411 if (++wq->sq.pidx == wq->sq.size)
413 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
414 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
415 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
418 static inline void t4_sq_consume(struct t4_wq *wq)
420 BUG_ON(wq->sq.in_use < 1);
421 if (wq->sq.cidx == wq->sq.flush_cidx)
422 wq->sq.flush_cidx = -1;
424 if (++wq->sq.cidx == wq->sq.size)
428 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
430 return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
433 static inline u16 t4_sq_wq_size(struct t4_wq *wq)
435 return wq->sq.size * T4_SQ_NUM_SLOTS;
438 /* This function copies 64 byte coalesced work request to memory
439 * mapped BAR2 space. For coalesced WRs, the SGE fetches data
440 * from the FIFO instead of from Host.
442 static inline void pio_copy(u64 __iomem *dst, u64 *src)
454 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
458 /* Flush host queue memory writes. */
461 if (inc == 1 && wqe) {
462 PDBG("%s: WC wq->sq.pidx = %d\n",
463 __func__, wq->sq.pidx);
464 pio_copy(wq->sq.udb + 7, (void *)wqe);
466 PDBG("%s: DB wq->sq.pidx = %d\n",
467 __func__, wq->sq.pidx);
468 writel(PIDX_T5_V(inc), wq->sq.udb);
471 /* Flush user doorbell area writes. */
475 writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db);
478 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
479 union t4_recv_wr *wqe)
482 /* Flush host queue memory writes. */
485 if (inc == 1 && wqe) {
486 PDBG("%s: WC wq->rq.pidx = %d\n",
487 __func__, wq->rq.pidx);
488 pio_copy(wq->rq.udb + 7, (void *)wqe);
490 PDBG("%s: DB wq->rq.pidx = %d\n",
491 __func__, wq->rq.pidx);
492 writel(PIDX_T5_V(inc), wq->rq.udb);
495 /* Flush user doorbell area writes. */
499 writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db);
502 static inline int t4_wq_in_error(struct t4_wq *wq)
504 return wq->rq.queue[wq->rq.size].status.qp_err;
507 static inline void t4_set_wq_in_error(struct t4_wq *wq)
509 wq->rq.queue[wq->rq.size].status.qp_err = 1;
512 static inline void t4_disable_wq_db(struct t4_wq *wq)
514 wq->rq.queue[wq->rq.size].status.db_off = 1;
517 static inline void t4_enable_wq_db(struct t4_wq *wq)
519 wq->rq.queue[wq->rq.size].status.db_off = 0;
522 static inline int t4_wq_db_enabled(struct t4_wq *wq)
524 return !wq->rq.queue[wq->rq.size].status.db_off;
532 struct t4_cqe *queue;
534 DEFINE_DMA_UNMAP_ADDR(mapping);
535 struct t4_cqe *sw_queue;
537 struct c4iw_rdev *rdev;
543 u16 size; /* including status page */
554 static inline int t4_clear_cq_armed(struct t4_cq *cq)
556 return test_and_clear_bit(CQ_ARMED, &cq->flags);
559 static inline int t4_arm_cq(struct t4_cq *cq, int se)
563 set_bit(CQ_ARMED, &cq->flags);
564 while (cq->cidx_inc > CIDXINC_M) {
565 val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7) |
566 INGRESSQID_V(cq->cqid);
567 writel(val, cq->gts);
568 cq->cidx_inc -= CIDXINC_M;
570 val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6) |
571 INGRESSQID_V(cq->cqid);
572 writel(val, cq->gts);
577 static inline void t4_swcq_produce(struct t4_cq *cq)
580 if (cq->sw_in_use == cq->size) {
581 PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
585 if (++cq->sw_pidx == cq->size)
589 static inline void t4_swcq_consume(struct t4_cq *cq)
591 BUG_ON(cq->sw_in_use < 1);
593 if (++cq->sw_cidx == cq->size)
597 static inline void t4_hwcq_consume(struct t4_cq *cq)
599 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
600 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) {
603 val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7) |
604 INGRESSQID_V(cq->cqid);
605 writel(val, cq->gts);
608 if (++cq->cidx == cq->size) {
614 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
616 return (CQE_GENBIT(cqe) == cq->gen);
619 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
625 prev_cidx = cq->size - 1;
627 prev_cidx = cq->cidx - 1;
629 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
632 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
634 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
636 /* Ensure CQE is flushed to memory */
638 *cqe = &cq->queue[cq->cidx];
645 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
647 if (cq->sw_in_use == cq->size) {
648 PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
654 return &cq->sw_queue[cq->sw_cidx];
658 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
664 else if (cq->sw_in_use)
665 *cqe = &cq->sw_queue[cq->sw_cidx];
667 ret = t4_next_hw_cqe(cq, cqe);
671 static inline int t4_cq_in_error(struct t4_cq *cq)
673 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
676 static inline void t4_set_cq_in_error(struct t4_cq *cq)
678 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
682 struct t4_dev_status_page {