2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
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6 * General Public License (GPL) Version 2, available from the file
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15 * copyright notice, this list of conditions and the following
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20 * provided with the distribution.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include "t4fw_ri_api.h"
39 #define T4_QID_BASE 1024
40 #define T4_MAX_QIDS 256
41 #define T4_MAX_NUM_QP (1<<16)
42 #define T4_MAX_NUM_CQ (1<<15)
43 #define T4_MAX_NUM_PD (1<<15)
44 #define T4_MAX_PBL_SIZE 256
45 #define T4_MAX_RQ_SIZE 1024
46 #define T4_MAX_SQ_SIZE 1024
47 #define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE-1)
48 #define T4_MAX_CQ_DEPTH 8192
49 #define T4_MAX_NUM_STAG (1<<15)
50 #define T4_MAX_MR_SIZE (~0ULL - 1)
51 #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
52 #define T4_STAG_UNSET 0xffffffff
54 #define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
56 struct t4_status_page {
57 __be32 rsvd1; /* flit 0 - hw owns */
62 u8 qp_err; /* flit 1 - sw owns */
68 #define T4_SQ_NUM_SLOTS 4
69 #define T4_SQ_NUM_BYTES (T4_EQ_SIZE * T4_SQ_NUM_SLOTS)
70 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
71 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
72 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
73 sizeof(struct fw_ri_immd)))
74 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
75 sizeof(struct fw_ri_rdma_write_wr) - \
76 sizeof(struct fw_ri_immd)))
77 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
78 sizeof(struct fw_ri_rdma_write_wr) - \
79 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
80 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
81 sizeof(struct fw_ri_immd)))
82 #define T4_MAX_FR_DEPTH 255
84 #define T4_RQ_NUM_SLOTS 2
85 #define T4_RQ_NUM_BYTES (T4_EQ_SIZE * T4_RQ_NUM_SLOTS)
86 #define T4_MAX_RECV_SGE ((T4_RQ_NUM_BYTES - sizeof(struct fw_ri_recv_wr) - \
87 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
90 struct fw_ri_res_wr res;
92 struct fw_ri_rdma_write_wr write;
93 struct fw_ri_send_wr send;
94 struct fw_ri_rdma_read_wr read;
95 struct fw_ri_bind_mw_wr bind;
96 struct fw_ri_fr_nsmr_wr fr;
97 struct fw_ri_inv_lstag_wr inv;
98 struct t4_status_page status;
99 __be64 flits[T4_EQ_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
103 struct fw_ri_recv_wr recv;
104 struct t4_status_page status;
105 __be64 flits[T4_EQ_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
108 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
109 enum fw_wr_opcodes opcode, u8 flags, u8 len16)
113 wqe->send.opcode = (u8)opcode;
114 wqe->send.flags = flags;
115 wqe->send.wrid = wrid;
119 wqe->send.len16 = len16;
121 slots_used = DIV_ROUND_UP(len16*16, T4_EQ_SIZE);
122 while (slots_used < T4_SQ_NUM_SLOTS) {
123 wqe->flits[slots_used * T4_EQ_SIZE / sizeof(__be64)] = 0;
128 /* CQE/AE status codes */
129 #define T4_ERR_SUCCESS 0x0
130 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */
131 /* STAG is offlimt, being 0, */
132 /* or STAG_key mismatch */
133 #define T4_ERR_PDID 0x2 /* PDID mismatch */
134 #define T4_ERR_QPID 0x3 /* QPID mismatch */
135 #define T4_ERR_ACCESS 0x4 /* Invalid access right */
136 #define T4_ERR_WRAP 0x5 /* Wrap error */
137 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */
138 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
139 /* shared memory region */
140 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
141 /* shared memory region */
142 #define T4_ERR_ECC 0x9 /* ECC error detected */
143 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
144 /* reading PSTAG for a MW */
146 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
148 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
149 #define T4_ERR_CRC 0x10 /* CRC error */
150 #define T4_ERR_MARKER 0x11 /* Marker error */
151 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
152 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
153 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
154 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
155 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
156 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
157 #define T4_ERR_MSN 0x18 /* MSN error */
158 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
159 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
161 #define T4_ERR_MSN_GAP 0x1B
162 #define T4_ERR_MSN_RANGE 0x1C
163 #define T4_ERR_IRD_OVERFLOW 0x1D
164 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
166 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
193 /* macros for flit 0 of the cqe */
195 #define S_CQE_QPID 12
196 #define M_CQE_QPID 0xFFFFF
197 #define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
198 #define V_CQE_QPID(x) ((x)<<S_CQE_QPID)
200 #define S_CQE_SWCQE 11
201 #define M_CQE_SWCQE 0x1
202 #define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
203 #define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE)
205 #define S_CQE_STATUS 5
206 #define M_CQE_STATUS 0x1F
207 #define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
208 #define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS)
211 #define M_CQE_TYPE 0x1
212 #define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
213 #define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE)
215 #define S_CQE_OPCODE 0
216 #define M_CQE_OPCODE 0xF
217 #define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
218 #define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE)
220 #define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header)))
221 #define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header)))
222 #define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header)))
223 #define SQ_TYPE(x) (CQE_TYPE((x)))
224 #define RQ_TYPE(x) (!CQE_TYPE((x)))
225 #define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header)))
226 #define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header)))
228 #define CQE_SEND_OPCODE(x)( \
229 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
230 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
231 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
232 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
234 #define CQE_LEN(x) (be32_to_cpu((x)->len))
236 /* used for RQ completion processing */
237 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
238 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
240 /* used for SQ completion processing */
241 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
243 /* generic accessor macros */
244 #define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi)
245 #define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low)
247 /* macros for flit 3 of the cqe */
248 #define S_CQE_GENBIT 63
249 #define M_CQE_GENBIT 0x1
250 #define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
251 #define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
253 #define S_CQE_OVFBIT 62
254 #define M_CQE_OVFBIT 0x1
255 #define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
257 #define S_CQE_IQTYPE 60
258 #define M_CQE_IQTYPE 0x3
259 #define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
261 #define M_CQE_TS 0x0fffffffffffffffULL
262 #define G_CQE_TS(x) ((x) & M_CQE_TS)
264 #define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
265 #define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
266 #define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
281 DECLARE_PCI_UNMAP_ADDR(mapping);
282 struct t4_swsqe *sw_sq;
283 struct t4_swsqe *oldest_read;
298 union t4_recv_wr *queue;
300 DECLARE_PCI_UNMAP_ADDR(mapping);
301 struct t4_swrqe *sw_rq;
319 struct c4iw_rdev *rdev;
322 static inline int t4_rqes_posted(struct t4_wq *wq)
324 return wq->rq.in_use;
327 static inline int t4_rq_empty(struct t4_wq *wq)
329 return wq->rq.in_use == 0;
332 static inline int t4_rq_full(struct t4_wq *wq)
334 return wq->rq.in_use == (wq->rq.size - 1);
337 static inline u32 t4_rq_avail(struct t4_wq *wq)
339 return wq->rq.size - 1 - wq->rq.in_use;
342 static inline void t4_rq_produce(struct t4_wq *wq)
345 if (++wq->rq.pidx == wq->rq.size)
349 static inline void t4_rq_consume(struct t4_wq *wq)
353 if (++wq->rq.cidx == wq->rq.size)
357 static inline int t4_sq_empty(struct t4_wq *wq)
359 return wq->sq.in_use == 0;
362 static inline int t4_sq_full(struct t4_wq *wq)
364 return wq->sq.in_use == (wq->sq.size - 1);
367 static inline u32 t4_sq_avail(struct t4_wq *wq)
369 return wq->sq.size - 1 - wq->sq.in_use;
372 static inline void t4_sq_produce(struct t4_wq *wq)
375 if (++wq->sq.pidx == wq->sq.size)
379 static inline void t4_sq_consume(struct t4_wq *wq)
382 if (++wq->sq.cidx == wq->sq.size)
386 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc)
388 inc *= T4_SQ_NUM_SLOTS;
390 writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
393 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc)
395 inc *= T4_RQ_NUM_SLOTS;
397 writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
400 static inline int t4_wq_in_error(struct t4_wq *wq)
402 return wq->sq.queue[wq->sq.size].status.qp_err;
405 static inline void t4_set_wq_in_error(struct t4_wq *wq)
407 wq->sq.queue[wq->sq.size].status.qp_err = 1;
408 wq->rq.queue[wq->rq.size].status.qp_err = 1;
411 static inline void t4_disable_wq_db(struct t4_wq *wq)
413 wq->sq.queue[wq->sq.size].status.db_off = 1;
414 wq->rq.queue[wq->rq.size].status.db_off = 1;
417 static inline void t4_enable_wq_db(struct t4_wq *wq)
419 wq->sq.queue[wq->sq.size].status.db_off = 0;
420 wq->rq.queue[wq->rq.size].status.db_off = 0;
423 static inline int t4_wq_db_enabled(struct t4_wq *wq)
425 return !wq->sq.queue[wq->sq.size].status.db_off;
429 struct t4_cqe *queue;
431 DECLARE_PCI_UNMAP_ADDR(mapping);
432 struct t4_cqe *sw_queue;
434 struct c4iw_rdev *rdev;
439 u16 size; /* including status page */
449 static inline int t4_arm_cq(struct t4_cq *cq, int se)
456 * inc must be less the both the max update value -and-
457 * the size of the CQ.
459 inc = cq->cidx_inc <= CIDXINC_MASK ? cq->cidx_inc :
461 inc = inc <= (cq->size - 1) ? inc : (cq->size - 1);
462 if (inc == cq->cidx_inc)
463 val = SEINTARM(se) | CIDXINC(inc) | TIMERREG(6) |
464 INGRESSQID(cq->cqid);
466 val = SEINTARM(0) | CIDXINC(inc) | TIMERREG(7) |
467 INGRESSQID(cq->cqid);
469 writel(val, cq->gts);
470 } while (cq->cidx_inc);
474 static inline void t4_swcq_produce(struct t4_cq *cq)
477 if (++cq->sw_pidx == cq->size)
481 static inline void t4_swcq_consume(struct t4_cq *cq)
484 if (++cq->sw_cidx == cq->size)
488 static inline void t4_hwcq_consume(struct t4_cq *cq)
491 if (++cq->cidx == cq->size) {
497 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
499 return (CQE_GENBIT(cqe) == cq->gen);
502 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
505 u64 bits_type_ts = be64_to_cpu(cq->queue[cq->cidx].bits_type_ts);
507 if (G_CQE_GENBIT(bits_type_ts) == cq->gen) {
508 *cqe = &cq->queue[cq->cidx];
509 cq->timestamp = G_CQE_TS(bits_type_ts);
510 } else if (G_CQE_TS(bits_type_ts) > cq->timestamp)
514 if (ret == -EOVERFLOW) {
515 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
521 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
524 return &cq->sw_queue[cq->sw_cidx];
528 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
534 else if (cq->sw_in_use)
535 *cqe = &cq->sw_queue[cq->sw_cidx];
537 ret = t4_next_hw_cqe(cq, cqe);
541 static inline int t4_cq_in_error(struct t4_cq *cq)
543 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
546 static inline void t4_set_cq_in_error(struct t4_cq *cq)
548 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;