2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/spinlock.h>
35 #include <linux/idr.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/vmalloc.h>
41 #include "ipath_kernel.h"
42 #include "ipath_layer.h"
43 #include "ipath_verbs.h"
44 #include "ipath_common.h"
46 static void ipath_update_pio_bufs(struct ipath_devdata *);
48 const char *ipath_get_unit_name(int unit)
50 static char iname[16];
51 snprintf(iname, sizeof iname, "infinipath%u", unit);
55 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
56 #define PFX IPATH_DRV_NAME ": "
59 * The size has to be longer than this string, so we can append
60 * board/chip information to it in the init code.
62 const char ipath_core_version[] = IPATH_IDSTR "\n";
64 static struct idr unit_table;
65 DEFINE_SPINLOCK(ipath_devs_lock);
66 LIST_HEAD(ipath_dev_list);
68 wait_queue_head_t ipath_sma_state_wait;
70 unsigned ipath_debug = __IPATH_INFO;
72 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
73 MODULE_PARM_DESC(debug, "mask for debug prints");
74 EXPORT_SYMBOL_GPL(ipath_debug);
76 MODULE_LICENSE("GPL");
77 MODULE_AUTHOR("QLogic <support@pathscale.com>");
78 MODULE_DESCRIPTION("QLogic InfiniPath driver");
80 const char *ipath_ibcstatus_str[] = {
87 "LState6", /* unused */
88 "LState7", /* unused */
94 "LState0xD", /* unused */
100 * These variables are initialized in the chip-specific files
101 * but are defined here.
103 u16 ipath_gpio_sda_num, ipath_gpio_scl_num;
104 u64 ipath_gpio_sda, ipath_gpio_scl;
105 u64 infinipath_i_bitsextant;
106 ipath_err_t infinipath_e_bitsextant, infinipath_hwe_bitsextant;
107 u32 infinipath_i_rcvavail_mask, infinipath_i_rcvurg_mask;
109 static void __devexit ipath_remove_one(struct pci_dev *);
110 static int __devinit ipath_init_one(struct pci_dev *,
111 const struct pci_device_id *);
113 /* Only needed for registration, nothing else needs this info */
114 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
115 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
116 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
118 static const struct pci_device_id ipath_pci_tbl[] = {
119 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
120 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
124 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
126 static struct pci_driver ipath_driver = {
127 .name = IPATH_DRV_NAME,
128 .probe = ipath_init_one,
129 .remove = __devexit_p(ipath_remove_one),
130 .id_table = ipath_pci_tbl,
134 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
135 u32 *bar0, u32 *bar1)
139 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
141 ipath_dev_err(dd, "failed to read bar0 before enable: "
144 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
146 ipath_dev_err(dd, "failed to read bar1 before enable: "
149 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
152 static void ipath_free_devdata(struct pci_dev *pdev,
153 struct ipath_devdata *dd)
157 pci_set_drvdata(pdev, NULL);
159 if (dd->ipath_unit != -1) {
160 spin_lock_irqsave(&ipath_devs_lock, flags);
161 idr_remove(&unit_table, dd->ipath_unit);
162 list_del(&dd->ipath_list);
163 spin_unlock_irqrestore(&ipath_devs_lock, flags);
168 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
171 struct ipath_devdata *dd;
174 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
175 dd = ERR_PTR(-ENOMEM);
179 dd = vmalloc(sizeof(*dd));
181 dd = ERR_PTR(-ENOMEM);
184 memset(dd, 0, sizeof(*dd));
187 spin_lock_irqsave(&ipath_devs_lock, flags);
189 ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
191 printk(KERN_ERR IPATH_DRV_NAME
192 ": Could not allocate unit ID: error %d\n", -ret);
193 ipath_free_devdata(pdev, dd);
199 pci_set_drvdata(pdev, dd);
201 list_add(&dd->ipath_list, &ipath_dev_list);
204 spin_unlock_irqrestore(&ipath_devs_lock, flags);
210 static inline struct ipath_devdata *__ipath_lookup(int unit)
212 return idr_find(&unit_table, unit);
215 struct ipath_devdata *ipath_lookup(int unit)
217 struct ipath_devdata *dd;
220 spin_lock_irqsave(&ipath_devs_lock, flags);
221 dd = __ipath_lookup(unit);
222 spin_unlock_irqrestore(&ipath_devs_lock, flags);
227 int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp)
229 int nunits, npresent, nup;
230 struct ipath_devdata *dd;
234 nunits = npresent = nup = maxports = 0;
236 spin_lock_irqsave(&ipath_devs_lock, flags);
238 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
240 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
243 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
246 if (dd->ipath_cfgports > maxports)
247 maxports = dd->ipath_cfgports;
250 spin_unlock_irqrestore(&ipath_devs_lock, flags);
253 *npresentp = npresent;
257 *maxportsp = maxports;
263 * These next two routines are placeholders in case we don't have per-arch
264 * code for controlling write combining. If explicit control of write
265 * combining is not available, performance will probably be awful.
268 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
273 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
277 static int __devinit ipath_init_one(struct pci_dev *pdev,
278 const struct pci_device_id *ent)
281 struct ipath_devdata *dd;
282 unsigned long long addr;
283 u32 bar0 = 0, bar1 = 0;
286 dd = ipath_alloc_devdata(pdev);
289 printk(KERN_ERR IPATH_DRV_NAME
290 ": Could not allocate devdata: error %d\n", -ret);
294 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
296 read_bars(dd, pdev, &bar0, &bar1);
298 ret = pci_enable_device(pdev);
300 /* This can happen iff:
302 * We did a chip reset, and then failed to reprogram the
303 * BAR, or the chip reset due to an internal error. We then
304 * unloaded the driver and reloaded it.
306 * Both reset cases set the BAR back to initial state. For
307 * the latter case, the AER sticky error bit at offset 0x718
308 * should be set, but the Linux kernel doesn't yet know
309 * about that, it appears. If the original BAR was retained
310 * in the kernel data structures, this may be OK.
312 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
313 dd->ipath_unit, -ret);
316 addr = pci_resource_start(pdev, 0);
317 len = pci_resource_len(pdev, 0);
318 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d irq %x, vend %x/%x "
319 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
320 ent->device, ent->driver_data);
322 read_bars(dd, pdev, &bar0, &bar1);
324 if (!bar1 && !(bar0 & ~0xf)) {
326 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
327 "rewriting as %llx\n", addr);
328 ret = pci_write_config_dword(
329 pdev, PCI_BASE_ADDRESS_0, addr);
331 ipath_dev_err(dd, "rewrite of BAR0 "
332 "failed: err %d\n", -ret);
335 ret = pci_write_config_dword(
336 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
338 ipath_dev_err(dd, "rewrite of BAR1 "
339 "failed: err %d\n", -ret);
343 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
344 "not usable until reboot\n");
350 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
352 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
353 "err %d\n", dd->ipath_unit, -ret);
357 ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
360 * if the 64 bit setup fails, try 32 bit. Some systems
361 * do not setup 64 bit maps on systems with 2GB or less
364 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
367 "Unable to set DMA mask for unit %u: %d\n",
368 dd->ipath_unit, ret);
372 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
373 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
376 "Unable to set DMA consistent mask "
378 dd->ipath_unit, ret);
383 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
386 "Unable to set DMA consistent mask "
388 dd->ipath_unit, ret);
391 pci_set_master(pdev);
394 * Save BARs to rewrite after device reset. Save all 64 bits of
397 dd->ipath_pcibar0 = addr;
398 dd->ipath_pcibar1 = addr >> 32;
399 dd->ipath_deviceid = ent->device; /* save for later use */
400 dd->ipath_vendorid = ent->vendor;
402 /* setup the chip-specific functions, as early as possible. */
403 switch (ent->device) {
404 case PCI_DEVICE_ID_INFINIPATH_HT:
405 ipath_init_ht400_funcs(dd);
407 case PCI_DEVICE_ID_INFINIPATH_PE800:
408 ipath_init_pe800_funcs(dd);
411 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
412 "failing\n", ent->device);
416 for (j = 0; j < 6; j++) {
417 if (!pdev->resource[j].start)
419 ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
420 j, (unsigned long long)pdev->resource[j].start,
421 (unsigned long long)pdev->resource[j].end,
422 (unsigned long long)pci_resource_len(pdev, j));
426 ipath_dev_err(dd, "No valid address in BAR 0!\n");
431 dd->ipath_deviceid = ent->device; /* save for later use */
432 dd->ipath_vendorid = ent->vendor;
434 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
436 ipath_dev_err(dd, "Failed to read PCI revision ID unit "
437 "%u: err %d\n", dd->ipath_unit, -ret);
438 goto bail_regions; /* shouldn't ever happen */
440 dd->ipath_pcirev = rev;
442 #if defined(__powerpc__)
443 /* There isn't a generic way to specify writethrough mappings */
444 dd->ipath_kregbase = __ioremap(addr, len,
445 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
447 dd->ipath_kregbase = ioremap_nocache(addr, len);
450 if (!dd->ipath_kregbase) {
451 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
456 dd->ipath_kregend = (u64 __iomem *)
457 ((void __iomem *)dd->ipath_kregbase + len);
458 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
460 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
461 addr, dd->ipath_kregbase);
464 * clear ipath_flags here instead of in ipath_init_chip as it is set
465 * by ipath_setup_htconfig.
468 dd->ipath_lli_counter = 0;
469 dd->ipath_lli_errors = 0;
471 if (dd->ipath_f_bus(dd, pdev))
472 ipath_dev_err(dd, "Failed to setup config space; "
473 "continuing anyway\n");
476 * set up our interrupt handler; IRQF_SHARED probably not needed,
477 * since MSI interrupts shouldn't be shared but won't hurt for now.
478 * check 0 irq after we return from chip-specific bus setup, since
479 * that can affect this due to setup
482 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
485 ret = request_irq(pdev->irq, ipath_intr, IRQF_SHARED,
488 ipath_dev_err(dd, "Couldn't setup irq handler, "
489 "irq=%u: %d\n", pdev->irq, ret);
494 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
498 ret = ipath_enable_wc(dd);
501 ipath_dev_err(dd, "Write combining not enabled "
502 "(err %d): performance may be poor\n",
507 ipath_device_create_group(&pdev->dev, dd);
508 ipathfs_add_device(dd);
512 ipath_register_ib_device(dd);
517 iounmap((volatile void __iomem *) dd->ipath_kregbase);
520 pci_release_regions(pdev);
523 pci_disable_device(pdev);
526 ipath_free_devdata(pdev, dd);
532 static void __devexit ipath_remove_one(struct pci_dev *pdev)
534 struct ipath_devdata *dd;
536 ipath_cdbg(VERBOSE, "removing, pdev=%p\n", pdev);
540 dd = pci_get_drvdata(pdev);
541 ipath_unregister_ib_device(dd->verbs_dev);
542 ipath_layer_remove(dd);
543 ipath_diag_remove(dd);
544 ipath_user_remove(dd);
545 ipathfs_remove_device(dd);
546 ipath_device_remove_group(&pdev->dev, dd);
547 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
548 "unit %u\n", dd, (u32) dd->ipath_unit);
549 if (dd->ipath_kregbase) {
550 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n",
552 iounmap((volatile void __iomem *) dd->ipath_kregbase);
553 dd->ipath_kregbase = NULL;
555 pci_release_regions(pdev);
556 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
557 pci_disable_device(pdev);
559 ipath_free_devdata(pdev, dd);
562 /* general driver use */
563 DEFINE_MUTEX(ipath_mutex);
565 static DEFINE_SPINLOCK(ipath_pioavail_lock);
568 * ipath_disarm_piobufs - cancel a range of PIO buffers
569 * @dd: the infinipath device
570 * @first: the first PIO buffer to cancel
571 * @cnt: the number of PIO buffers to cancel
573 * cancel a range of PIO buffers, used when they might be armed, but
574 * not triggered. Used at init to ensure buffer state, and also user
575 * process close, in case it died while writing to a PIO buffer
578 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
581 unsigned i, last = first + cnt;
582 u64 sendctrl, sendorig;
584 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
585 sendorig = dd->ipath_sendctrl | INFINIPATH_S_DISARM;
586 for (i = first; i < last; i++) {
587 sendctrl = sendorig |
588 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT);
589 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
594 * Write it again with current value, in case ipath_sendctrl changed
595 * while we were looping; no critical bits that would require
598 * Write a 0, and then the original value, reading scratch in
599 * between. This seems to avoid a chip timing race that causes
600 * pioavail updates to memory to stop.
602 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
604 sendorig = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
605 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
610 * ipath_wait_linkstate - wait for an IB link state change to occur
611 * @dd: the infinipath device
612 * @state: the state to wait for
613 * @msecs: the number of milliseconds to wait
615 * wait up to msecs milliseconds for IB link state change to occur for
616 * now, take the easy polling route. Currently used only by
617 * ipath_layer_set_linkstate. Returns 0 if state reached, otherwise
618 * -ETIMEDOUT state can have multiple states set, for any of several
621 int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, int msecs)
623 dd->ipath_sma_state_wanted = state;
624 wait_event_interruptible_timeout(ipath_sma_state_wait,
625 (dd->ipath_flags & state),
626 msecs_to_jiffies(msecs));
627 dd->ipath_sma_state_wanted = 0;
629 if (!(dd->ipath_flags & state)) {
631 ipath_cdbg(SMA, "Didn't reach linkstate %s within %u ms\n",
632 /* test INIT ahead of DOWN, both can be set */
633 (state & IPATH_LINKINIT) ? "INIT" :
634 ((state & IPATH_LINKDOWN) ? "DOWN" :
635 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
637 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
638 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
639 (unsigned long long) ipath_read_kreg64(
640 dd, dd->ipath_kregs->kr_ibcctrl),
641 (unsigned long long) val,
642 ipath_ibcstatus_str[val & 0xf]);
644 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
647 void ipath_decode_err(char *buf, size_t blen, ipath_err_t err)
650 if (err & INFINIPATH_E_RHDRLEN)
651 strlcat(buf, "rhdrlen ", blen);
652 if (err & INFINIPATH_E_RBADTID)
653 strlcat(buf, "rbadtid ", blen);
654 if (err & INFINIPATH_E_RBADVERSION)
655 strlcat(buf, "rbadversion ", blen);
656 if (err & INFINIPATH_E_RHDR)
657 strlcat(buf, "rhdr ", blen);
658 if (err & INFINIPATH_E_RLONGPKTLEN)
659 strlcat(buf, "rlongpktlen ", blen);
660 if (err & INFINIPATH_E_RSHORTPKTLEN)
661 strlcat(buf, "rshortpktlen ", blen);
662 if (err & INFINIPATH_E_RMAXPKTLEN)
663 strlcat(buf, "rmaxpktlen ", blen);
664 if (err & INFINIPATH_E_RMINPKTLEN)
665 strlcat(buf, "rminpktlen ", blen);
666 if (err & INFINIPATH_E_RFORMATERR)
667 strlcat(buf, "rformaterr ", blen);
668 if (err & INFINIPATH_E_RUNSUPVL)
669 strlcat(buf, "runsupvl ", blen);
670 if (err & INFINIPATH_E_RUNEXPCHAR)
671 strlcat(buf, "runexpchar ", blen);
672 if (err & INFINIPATH_E_RIBFLOW)
673 strlcat(buf, "ribflow ", blen);
674 if (err & INFINIPATH_E_REBP)
675 strlcat(buf, "EBP ", blen);
676 if (err & INFINIPATH_E_SUNDERRUN)
677 strlcat(buf, "sunderrun ", blen);
678 if (err & INFINIPATH_E_SPIOARMLAUNCH)
679 strlcat(buf, "spioarmlaunch ", blen);
680 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
681 strlcat(buf, "sunexperrpktnum ", blen);
682 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
683 strlcat(buf, "sdroppeddatapkt ", blen);
684 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
685 strlcat(buf, "sdroppedsmppkt ", blen);
686 if (err & INFINIPATH_E_SMAXPKTLEN)
687 strlcat(buf, "smaxpktlen ", blen);
688 if (err & INFINIPATH_E_SMINPKTLEN)
689 strlcat(buf, "sminpktlen ", blen);
690 if (err & INFINIPATH_E_SUNSUPVL)
691 strlcat(buf, "sunsupVL ", blen);
692 if (err & INFINIPATH_E_SPKTLEN)
693 strlcat(buf, "spktlen ", blen);
694 if (err & INFINIPATH_E_INVALIDADDR)
695 strlcat(buf, "invalidaddr ", blen);
696 if (err & INFINIPATH_E_RICRC)
697 strlcat(buf, "CRC ", blen);
698 if (err & INFINIPATH_E_RVCRC)
699 strlcat(buf, "VCRC ", blen);
700 if (err & INFINIPATH_E_RRCVEGRFULL)
701 strlcat(buf, "rcvegrfull ", blen);
702 if (err & INFINIPATH_E_RRCVHDRFULL)
703 strlcat(buf, "rcvhdrfull ", blen);
704 if (err & INFINIPATH_E_IBSTATUSCHANGED)
705 strlcat(buf, "ibcstatuschg ", blen);
706 if (err & INFINIPATH_E_RIBLOSTLINK)
707 strlcat(buf, "riblostlink ", blen);
708 if (err & INFINIPATH_E_HARDWARE)
709 strlcat(buf, "hardware ", blen);
710 if (err & INFINIPATH_E_RESET)
711 strlcat(buf, "reset ", blen);
715 * get_rhf_errstring - decode RHF errors
716 * @err: the err number
717 * @msg: the output buffer
718 * @len: the length of the output buffer
720 * only used one place now, may want more later
722 static void get_rhf_errstring(u32 err, char *msg, size_t len)
724 /* if no errors, and so don't need to check what's first */
727 if (err & INFINIPATH_RHF_H_ICRCERR)
728 strlcat(msg, "icrcerr ", len);
729 if (err & INFINIPATH_RHF_H_VCRCERR)
730 strlcat(msg, "vcrcerr ", len);
731 if (err & INFINIPATH_RHF_H_PARITYERR)
732 strlcat(msg, "parityerr ", len);
733 if (err & INFINIPATH_RHF_H_LENERR)
734 strlcat(msg, "lenerr ", len);
735 if (err & INFINIPATH_RHF_H_MTUERR)
736 strlcat(msg, "mtuerr ", len);
737 if (err & INFINIPATH_RHF_H_IHDRERR)
738 /* infinipath hdr checksum error */
739 strlcat(msg, "ipathhdrerr ", len);
740 if (err & INFINIPATH_RHF_H_TIDERR)
741 strlcat(msg, "tiderr ", len);
742 if (err & INFINIPATH_RHF_H_MKERR)
743 /* bad port, offset, etc. */
744 strlcat(msg, "invalid ipathhdr ", len);
745 if (err & INFINIPATH_RHF_H_IBERR)
746 strlcat(msg, "iberr ", len);
747 if (err & INFINIPATH_RHF_L_SWA)
748 strlcat(msg, "swA ", len);
749 if (err & INFINIPATH_RHF_L_SWB)
750 strlcat(msg, "swB ", len);
754 * ipath_get_egrbuf - get an eager buffer
755 * @dd: the infinipath device
756 * @bufnum: the eager buffer to get
759 * must only be called if ipath_pd[port] is known to be allocated
761 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum,
764 return dd->ipath_port0_skbs ?
765 (void *)dd->ipath_port0_skbs[bufnum]->data : NULL;
769 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
770 * @dd: the infinipath device
771 * @gfp_mask: the sk_buff SFP mask
773 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
780 * Only fully supported way to handle this is to allocate lots
781 * extra, align as needed, and then do skb_reserve(). That wastes
782 * a lot of memory... I'll have to hack this into infinipath_copy
787 * We need 4 extra bytes for unaligned transfer copying
789 if (dd->ipath_flags & IPATH_4BYTE_TID) {
790 /* we need a 4KB multiple alignment, and there is no way
791 * to do it except to allocate extra and then skb_reserve
792 * enough to bring it up to the right alignment.
794 len = dd->ipath_ibmaxlen + 4 + (1 << 11) - 1;
797 len = dd->ipath_ibmaxlen + 4;
798 skb = __dev_alloc_skb(len, gfp_mask);
800 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
804 if (dd->ipath_flags & IPATH_4BYTE_TID) {
805 u32 una = ((1 << 11) - 1) & (unsigned long)(skb->data + 4);
807 skb_reserve(skb, 4 + (1 << 11) - una);
818 * ipath_rcv_layer - receive a packet for the layered (ethernet) driver
819 * @dd: the infinipath device
820 * @etail: the sk_buff number
821 * @tlen: the total packet length
822 * @hdr: the ethernet header
824 * Separate routine for better overall optimization
826 static void ipath_rcv_layer(struct ipath_devdata *dd, u32 etail,
827 u32 tlen, struct ether_header *hdr)
831 struct sk_buff *skb, *nskb;
833 if (dd->ipath_port0_skbs &&
834 hdr->sub_opcode == IPATH_ITH4X_OPCODE_ENCAP) {
836 * Allocate a new sk_buff to replace the one we give
837 * to the network stack.
839 nskb = ipath_alloc_skb(dd, GFP_ATOMIC);
841 /* count OK packets that we drop */
842 ipath_stats.sps_krdrops++;
846 bthbytes = (u8 *) hdr->bth;
847 pad = (bthbytes[1] >> 4) & 3;
849 elen = tlen - (sizeof(*hdr) + pad + sizeof(u32));
851 skb = dd->ipath_port0_skbs[etail];
852 dd->ipath_port0_skbs[etail] = nskb;
855 dd->ipath_f_put_tid(dd, etail + (u64 __iomem *)
856 ((char __iomem *) dd->ipath_kregbase
857 + dd->ipath_rcvegrbase), 0,
858 virt_to_phys(nskb->data));
860 __ipath_layer_rcv(dd, hdr, skb);
862 /* another ether packet received */
863 ipath_stats.sps_ether_rpkts++;
865 else if (hdr->sub_opcode == IPATH_ITH4X_OPCODE_LID_ARP)
866 __ipath_layer_rcv_lid(dd, hdr);
869 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
876 struct ipath_message_header *hdr;
878 get_rhf_errstring(eflags, emsg, sizeof emsg);
879 hdr = (struct ipath_message_header *)&rc[1];
880 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
881 "tlen=%x opcode=%x egridx=%x: %s\n",
883 ipath_hdrget_rcv_type((__le32 *) rc),
884 ipath_hdrget_length_in_bytes((__le32 *) rc),
885 be32_to_cpu(hdr->bth[0]) >> 24,
888 /* Count local link integrity errors. */
889 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
890 u8 n = (dd->ipath_ibcctrl >>
891 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
892 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
894 if (++dd->ipath_lli_counter > n) {
895 dd->ipath_lli_counter = 0;
896 dd->ipath_lli_errors++;
902 * ipath_kreceive - receive a packet
903 * @dd: the infinipath device
905 * called from interrupt handler for errors or receive interrupt
907 void ipath_kreceive(struct ipath_devdata *dd)
911 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
912 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
913 u32 etail = -1, l, hdrqtail;
914 struct ipath_message_header *hdr;
915 u32 eflags, i, etype, tlen, pkttot = 0, updegr=0, reloop=0;
916 static u64 totcalls; /* stats, may eventually remove */
918 if (!dd->ipath_hdrqtailptr) {
920 "hdrqtailptr not set, can't do receives\n");
924 /* There is already a thread processing this queue. */
925 if (test_and_set_bit(0, &dd->ipath_rcv_pending))
928 l = dd->ipath_port0head;
929 hdrqtail = (u32) le64_to_cpu(*dd->ipath_hdrqtailptr);
934 for (i = 0; l != hdrqtail; i++) {
938 rc = (u64 *) (dd->ipath_pd[0]->port_rcvhdrq + (l << 2));
939 hdr = (struct ipath_message_header *)&rc[1];
941 * could make a network order version of IPATH_KD_QP, and
942 * do the obvious shift before masking to speed this up.
944 qp = ntohl(hdr->bth[1]) & 0xffffff;
945 bthbytes = (u8 *) hdr->bth;
947 eflags = ipath_hdrget_err_flags((__le32 *) rc);
948 etype = ipath_hdrget_rcv_type((__le32 *) rc);
950 tlen = ipath_hdrget_length_in_bytes((__le32 *) rc);
952 if (etype != RCVHQ_RCV_TYPE_EXPECTED) {
954 * it turns out that the chips uses an eager buffer
955 * for all non-expected packets, whether it "needs"
956 * one or not. So always get the index, but don't
957 * set ebuf (so we try to copy data) unless the
958 * length requires it.
960 etail = ipath_hdrget_index((__le32 *) rc);
961 if (tlen > sizeof(*hdr) ||
962 etype == RCVHQ_RCV_TYPE_NON_KD)
963 ebuf = ipath_get_egrbuf(dd, etail, 0);
967 * both tiderr and ipathhdrerr are set for all plain IB
968 * packets; only ipathhdrerr should be set.
971 if (etype != RCVHQ_RCV_TYPE_NON_KD && etype !=
972 RCVHQ_RCV_TYPE_ERROR && ipath_hdrget_ipath_ver(
973 hdr->iph.ver_port_tid_offset) !=
975 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
979 if (unlikely(eflags))
980 ipath_rcv_hdrerr(dd, eflags, l, etail, rc);
981 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
982 ipath_ib_rcv(dd->verbs_dev, rc + 1, ebuf,
984 if (dd->ipath_lli_counter)
985 dd->ipath_lli_counter--;
987 } else if (etype == RCVHQ_RCV_TYPE_EAGER) {
988 if (qp == IPATH_KD_QP &&
989 bthbytes[0] == ipath_layer_rcv_opcode &&
991 ipath_rcv_layer(dd, etail, tlen,
992 (struct ether_header *)hdr);
994 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
995 "qp=%x), len %x; ignored\n",
996 etype, bthbytes[0], qp, tlen);
998 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
999 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1000 be32_to_cpu(hdr->bth[0]) & 0xff);
1003 * error packet, type of error unknown.
1004 * Probably type 3, but we don't know, so don't
1005 * even try to print the opcode, etc.
1007 ipath_dbg("Error Pkt, but no eflags! egrbuf %x, "
1008 "len %x\nhdrq@%lx;hdrq+%x rhf: %llx; "
1009 "hdr %llx %llx %llx %llx %llx\n",
1010 etail, tlen, (unsigned long) rc, l,
1011 (unsigned long long) rc[0],
1012 (unsigned long long) rc[1],
1013 (unsigned long long) rc[2],
1014 (unsigned long long) rc[3],
1015 (unsigned long long) rc[4],
1016 (unsigned long long) rc[5]);
1021 if (etype != RCVHQ_RCV_TYPE_EXPECTED)
1024 * update head regs on last packet, and every 16 packets.
1025 * Reduce bus traffic, while still trying to prevent
1026 * rcvhdrq overflows, for when the queue is nearly full
1028 if (l == hdrqtail || (i && !(i&0xf))) {
1030 if (l == hdrqtail) /* PE-800 interrupt only on last */
1031 lval = dd->ipath_rhdrhead_intr_off | l;
1034 (void)ipath_write_ureg(dd, ur_rcvhdrhead, lval, 0);
1036 (void)ipath_write_ureg(dd, ur_rcvegrindexhead,
1043 if (!dd->ipath_rhdrhead_intr_off && !reloop) {
1044 /* HT-400 workaround; we can have a race clearing chip
1045 * interrupt with another interrupt about to be delivered,
1046 * and can clear it before it is delivered on the GPIO
1047 * workaround. By doing the extra check here for the
1048 * in-memory tail register updating while we were doing
1049 * earlier packets, we "almost" guarantee we have covered
1052 u32 hqtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr);
1053 if (hqtail != hdrqtail) {
1055 reloop = 1; /* loop 1 extra time at most */
1062 dd->ipath_port0head = l;
1064 if (pkttot > ipath_stats.sps_maxpkts_call)
1065 ipath_stats.sps_maxpkts_call = pkttot;
1066 ipath_stats.sps_port0pkts += pkttot;
1067 ipath_stats.sps_avgpkts_call =
1068 ipath_stats.sps_port0pkts / ++totcalls;
1071 clear_bit(0, &dd->ipath_rcv_pending);
1072 smp_mb__after_clear_bit();
1078 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1079 * @dd: the infinipath device
1081 * called whenever our local copy indicates we have run out of send buffers
1082 * NOTE: This can be called from interrupt context by some code
1083 * and from non-interrupt context by ipath_getpiobuf().
1086 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1088 unsigned long flags;
1090 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1092 /* If the generation (check) bits have changed, then we update the
1093 * busy bit for the corresponding PIO buffer. This algorithm will
1094 * modify positions to the value they already have in some cases
1095 * (i.e., no change), but it's faster than changing only the bits
1096 * that have changed.
1098 * We would like to do this atomicly, to avoid spinlocks in the
1099 * critical send path, but that's not really possible, given the
1100 * type of changes, and that this routine could be called on
1101 * multiple cpu's simultaneously, so we lock in this routine only,
1102 * to avoid conflicting updates; all we change is the shadow, and
1103 * it's a single 64 bit memory location, so by definition the update
1104 * is atomic in terms of what other cpu's can see in testing the
1105 * bits. The spin_lock overhead isn't too bad, since it only
1106 * happens when all buffers are in use, so only cpu overhead, not
1107 * latency or bandwidth is affected.
1109 #define _IPATH_ALL_CHECKBITS 0x5555555555555555ULL
1110 if (!dd->ipath_pioavailregs_dma) {
1111 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1114 if (ipath_debug & __IPATH_VERBDBG) {
1115 /* only if packet debug and verbose */
1116 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1117 unsigned long *shadow = dd->ipath_pioavailshadow;
1119 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1120 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1122 (unsigned long long) le64_to_cpu(dma[0]),
1124 (unsigned long long) le64_to_cpu(dma[1]),
1126 (unsigned long long) le64_to_cpu(dma[2]),
1128 (unsigned long long) le64_to_cpu(dma[3]),
1132 PKT, "2nd group, dma4=%llx shad4=%lx, "
1133 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1135 (unsigned long long) le64_to_cpu(dma[4]),
1137 (unsigned long long) le64_to_cpu(dma[5]),
1139 (unsigned long long) le64_to_cpu(dma[6]),
1141 (unsigned long long) le64_to_cpu(dma[7]),
1144 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1145 for (i = 0; i < piobregs; i++) {
1146 u64 pchbusy, pchg, piov, pnew;
1148 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1153 dd->ipath_pioavailregs_dma[i - 1]);
1156 dd->ipath_pioavailregs_dma[i + 1]);
1158 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1159 pchg = _IPATH_ALL_CHECKBITS &
1160 ~(dd->ipath_pioavailshadow[i] ^ piov);
1161 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1162 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1163 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1164 pnew |= piov & pchbusy;
1165 dd->ipath_pioavailshadow[i] = pnew;
1168 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1172 * ipath_setrcvhdrsize - set the receive header size
1173 * @dd: the infinipath device
1174 * @rhdrsize: the receive header size
1176 * called from user init code, and also layered driver init
1178 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1182 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1183 if (dd->ipath_rcvhdrsize != rhdrsize) {
1184 dev_info(&dd->pcidev->dev,
1185 "Error: can't set protocol header "
1186 "size %u, already %u\n",
1187 rhdrsize, dd->ipath_rcvhdrsize);
1190 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1191 "size %u\n", dd->ipath_rcvhdrsize);
1192 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1193 (sizeof(u64) / sizeof(u32)))) {
1194 ipath_dbg("Error: can't set protocol header size %u "
1195 "(> max %u)\n", rhdrsize,
1196 dd->ipath_rcvhdrentsize -
1197 (u32) (sizeof(u64) / sizeof(u32)));
1200 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1201 dd->ipath_rcvhdrsize = rhdrsize;
1202 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1203 dd->ipath_rcvhdrsize);
1204 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1205 dd->ipath_rcvhdrsize);
1211 * ipath_getpiobuf - find an available pio buffer
1212 * @dd: the infinipath device
1213 * @pbufnum: the buffer number is placed here
1215 * do appropriate marking as busy, etc.
1216 * returns buffer number if one found (>=0), negative number is error.
1217 * Used by ipath_sma_send_pkt and ipath_layer_send
1219 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 * pbufnum)
1221 int i, j, starti, updated = 0;
1222 unsigned piobcnt, iter;
1223 unsigned long flags;
1224 unsigned long *shadow = dd->ipath_pioavailshadow;
1227 piobcnt = (unsigned)(dd->ipath_piobcnt2k
1228 + dd->ipath_piobcnt4k);
1229 starti = dd->ipath_lastport_piobuf;
1230 iter = piobcnt - starti;
1231 if (dd->ipath_upd_pio_shadow) {
1233 * Minor optimization. If we had no buffers on last call,
1234 * start out by doing the update; continue and do scan even
1235 * if no buffers were updated, to be paranoid
1237 ipath_update_pio_bufs(dd);
1238 /* we scanned here, don't do it at end of scan */
1242 i = dd->ipath_lastpioindex;
1246 * while test_and_set_bit() is atomic, we do that and then the
1247 * change_bit(), and the pair is not. See if this is the cause
1248 * of the remaining armlaunch errors.
1250 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1251 for (j = 0; j < iter; j++, i++) {
1255 * To avoid bus lock overhead, we first find a candidate
1256 * buffer, then do the test and set, and continue if that
1259 if (test_bit((2 * i) + 1, shadow) ||
1260 test_and_set_bit((2 * i) + 1, shadow))
1262 /* flip generation bit */
1263 change_bit(2 * i, shadow);
1266 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1269 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1272 * first time through; shadow exhausted, but may be real
1273 * buffers available, so go see; if any updated, rescan
1277 ipath_update_pio_bufs(dd);
1282 dd->ipath_upd_pio_shadow = 1;
1284 * not atomic, but if we lose one once in a while, that's OK
1286 ipath_stats.sps_nopiobufs++;
1287 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1289 "%u pio sends with no bufavail; dmacopy: "
1290 "%llx %llx %llx %llx; shadow: "
1291 "%lx %lx %lx %lx\n",
1292 dd->ipath_consec_nopiobuf,
1293 (unsigned long long) le64_to_cpu(dma[0]),
1294 (unsigned long long) le64_to_cpu(dma[1]),
1295 (unsigned long long) le64_to_cpu(dma[2]),
1296 (unsigned long long) le64_to_cpu(dma[3]),
1297 shadow[0], shadow[1], shadow[2],
1300 * 4 buffers per byte, 4 registers above, cover rest
1303 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1304 (sizeof(shadow[0]) * 4 * 4))
1305 ipath_dbg("2nd group: dmacopy: %llx %llx "
1306 "%llx %llx; shadow: %lx %lx "
1308 (unsigned long long)
1309 le64_to_cpu(dma[4]),
1310 (unsigned long long)
1311 le64_to_cpu(dma[5]),
1312 (unsigned long long)
1313 le64_to_cpu(dma[6]),
1314 (unsigned long long)
1315 le64_to_cpu(dma[7]),
1316 shadow[4], shadow[5],
1317 shadow[6], shadow[7]);
1325 * ran out of bufs, now some (at least this one we just
1326 * got) are now available, so tell the layered driver.
1328 __ipath_layer_intr(dd, IPATH_LAYER_INT_SEND_CONTINUE);
1331 * set next starting place. Since it's just an optimization,
1332 * it doesn't matter who wins on this, so no locking
1334 dd->ipath_lastpioindex = i + 1;
1335 if (dd->ipath_upd_pio_shadow)
1336 dd->ipath_upd_pio_shadow = 0;
1337 if (dd->ipath_consec_nopiobuf)
1338 dd->ipath_consec_nopiobuf = 0;
1339 if (i < dd->ipath_piobcnt2k)
1340 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1341 i * dd->ipath_palign);
1343 buf = (u32 __iomem *)
1344 (dd->ipath_pio4kbase +
1345 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1346 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1347 i, (i < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1356 * ipath_create_rcvhdrq - create a receive header queue
1357 * @dd: the infinipath device
1358 * @pd: the port data
1360 * this must be contiguous memory (from an i/o perspective), and must be
1361 * DMA'able (which means for some systems, it will go through an IOMMU,
1362 * or be forced into a low address range).
1364 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1365 struct ipath_portdata *pd)
1369 if (!pd->port_rcvhdrq) {
1370 dma_addr_t phys_hdrqtail;
1371 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1372 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1373 sizeof(u32), PAGE_SIZE);
1375 pd->port_rcvhdrq = dma_alloc_coherent(
1376 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1379 if (!pd->port_rcvhdrq) {
1380 ipath_dev_err(dd, "attempt to allocate %d bytes "
1381 "for port %u rcvhdrq failed\n",
1382 amt, pd->port_port);
1386 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1387 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail, GFP_KERNEL);
1388 if (!pd->port_rcvhdrtail_kvaddr) {
1389 ipath_dev_err(dd, "attempt to allocate 1 page "
1390 "for port %u rcvhdrqtailaddr failed\n",
1395 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1397 pd->port_rcvhdrq_size = amt;
1399 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1400 "for port %u rcvhdr Q\n",
1401 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1402 (unsigned long) pd->port_rcvhdrq_phys,
1403 (unsigned long) pd->port_rcvhdrq_size,
1406 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx physical\n",
1408 (unsigned long long) phys_hdrqtail);
1411 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1412 "hdrtailaddr@%p %llx physical\n",
1413 pd->port_port, pd->port_rcvhdrq,
1414 pd->port_rcvhdrq_phys, pd->port_rcvhdrtail_kvaddr,
1415 (unsigned long long)pd->port_rcvhdrqtailaddr_phys);
1417 /* clear for security and sanity on each use */
1418 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1419 memset((void *)pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1422 * tell chip each time we init it, even if we are re-using previous
1423 * memory (we zero the register at process close)
1425 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1426 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1427 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1428 pd->port_port, pd->port_rcvhdrq_phys);
1435 int ipath_waitfor_complete(struct ipath_devdata *dd, ipath_kreg reg_id,
1436 u64 bits_to_wait_for, u64 * valp)
1438 unsigned long timeout;
1442 lastval = ipath_read_kreg64(dd, reg_id);
1443 /* wait a ridiculously long time */
1444 timeout = jiffies + msecs_to_jiffies(5);
1446 val = ipath_read_kreg64(dd, reg_id);
1447 /* set so they have something, even on failures. */
1449 if ((val & bits_to_wait_for) == bits_to_wait_for) {
1454 ipath_cdbg(VERBOSE, "Changed from %llx to %llx, "
1455 "waiting for %llx bits\n",
1456 (unsigned long long) lastval,
1457 (unsigned long long) val,
1458 (unsigned long long) bits_to_wait_for);
1460 if (time_after(jiffies, timeout)) {
1461 ipath_dbg("Didn't get bits %llx in register 0x%x, "
1463 (unsigned long long) bits_to_wait_for,
1464 reg_id, (unsigned long long) *valp);
1474 * ipath_waitfor_mdio_cmdready - wait for last command to complete
1475 * @dd: the infinipath device
1477 * Like ipath_waitfor_complete(), but we wait for the CMDVALID bit to go
1478 * away indicating the last command has completed. It doesn't return data
1480 int ipath_waitfor_mdio_cmdready(struct ipath_devdata *dd)
1482 unsigned long timeout;
1486 /* wait a ridiculously long time */
1487 timeout = jiffies + msecs_to_jiffies(5);
1489 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_mdio);
1490 if (!(val & IPATH_MDIO_CMDVALID)) {
1495 if (time_after(jiffies, timeout)) {
1496 ipath_dbg("CMDVALID stuck in mdio reg? (%llx)\n",
1497 (unsigned long long) val);
1506 void ipath_set_ib_lstate(struct ipath_devdata *dd, int which)
1508 static const char *what[4] = {
1510 [INFINIPATH_IBCC_LINKCMD_INIT] = "INIT",
1511 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1512 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1514 int linkcmd = (which >> INFINIPATH_IBCC_LINKCMD_SHIFT) &
1515 INFINIPATH_IBCC_LINKCMD_MASK;
1517 ipath_cdbg(SMA, "Trying to move unit %u to %s, current ltstate "
1518 "is %s\n", dd->ipath_unit,
1520 ipath_ibcstatus_str[
1522 (dd, dd->ipath_kregs->kr_ibcstatus) >>
1523 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
1524 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK]);
1525 /* flush all queued sends when going to DOWN or INIT, to be sure that
1526 * they don't block SMA and other MAD packets */
1527 if (!linkcmd || linkcmd == INFINIPATH_IBCC_LINKCMD_INIT) {
1528 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1529 INFINIPATH_S_ABORT);
1530 ipath_disarm_piobufs(dd, dd->ipath_lastport_piobuf,
1531 (unsigned)(dd->ipath_piobcnt2k +
1532 dd->ipath_piobcnt4k) -
1533 dd->ipath_lastport_piobuf);
1536 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
1537 dd->ipath_ibcctrl | which);
1541 * ipath_read_kreg64_port - read a device's per-port 64-bit kernel register
1542 * @dd: the infinipath device
1543 * @regno: the register number to read
1544 * @port: the port containing the register
1546 * Registers that vary with the chip implementation constants (port)
1549 u64 ipath_read_kreg64_port(const struct ipath_devdata *dd, ipath_kreg regno,
1554 if (port < dd->ipath_portcnt &&
1555 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
1556 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
1557 where = regno + port;
1561 return ipath_read_kreg64(dd, where);
1565 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
1566 * @dd: the infinipath device
1567 * @regno: the register number to write
1568 * @port: the port containing the register
1569 * @value: the value to write
1571 * Registers that vary with the chip implementation constants (port)
1574 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
1575 unsigned port, u64 value)
1579 if (port < dd->ipath_portcnt &&
1580 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
1581 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
1582 where = regno + port;
1586 ipath_write_kreg(dd, where, value);
1590 * ipath_shutdown_device - shut down a device
1591 * @dd: the infinipath device
1593 * This is called to make the device quiet when we are about to
1594 * unload the driver, and also when the device is administratively
1595 * disabled. It does not free any data structures.
1596 * Everything it does has to be setup again by ipath_init_chip(dd,1)
1598 void ipath_shutdown_device(struct ipath_devdata *dd)
1602 ipath_dbg("Shutting down the device\n");
1604 dd->ipath_flags |= IPATH_LINKUNK;
1605 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
1606 IPATH_LINKINIT | IPATH_LINKARMED |
1608 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
1609 IPATH_STATUS_IB_READY);
1611 /* mask interrupts, but not errors */
1612 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
1614 dd->ipath_rcvctrl = 0;
1615 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1619 * gracefully stop all sends allowing any in progress to trickle out
1622 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 0ULL);
1624 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1626 * enough for anything that's going to trickle out to have actually
1632 * abort any armed or launched PIO buffers that didn't go. (self
1633 * clearing). Will cause any packet currently being transmitted to
1634 * go out with an EBP, and may also cause a short packet error on
1637 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1638 INFINIPATH_S_ABORT);
1640 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
1641 INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1644 * we are shutting down, so tell the layered driver. We don't do
1645 * this on just a link state change, much like ethernet, a cable
1646 * unplug, etc. doesn't change driver state
1648 ipath_layer_intr(dd, IPATH_LAYER_INT_IF_DOWN);
1651 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
1652 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1653 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
1656 * clear SerdesEnable and turn the leds off; do this here because
1657 * we are unloading, so don't count on interrupts to move along
1658 * Turn the LEDs off explictly for the same reason.
1660 dd->ipath_f_quiet_serdes(dd);
1661 dd->ipath_f_setextled(dd, 0, 0);
1663 if (dd->ipath_stats_timer_active) {
1664 del_timer_sync(&dd->ipath_stats_timer);
1665 dd->ipath_stats_timer_active = 0;
1669 * clear all interrupts and errors, so that the next time the driver
1670 * is loaded or device is enabled, we know that whatever is set
1671 * happened while we were unloaded
1673 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1674 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
1675 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
1676 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
1680 * ipath_free_pddata - free a port's allocated data
1681 * @dd: the infinipath device
1682 * @pd: the portdata structure
1684 * free up any allocated data for a port
1685 * This should not touch anything that would affect a simultaneous
1686 * re-allocation of port data, because it is called after ipath_mutex
1687 * is released (and can be called from reinit as well).
1688 * It should never change any chip state, or global driver state.
1689 * (The only exception to global state is freeing the port0 port0_skbs.)
1691 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
1696 if (pd->port_rcvhdrq) {
1697 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
1698 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
1699 (unsigned long) pd->port_rcvhdrq_size);
1700 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
1701 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
1702 pd->port_rcvhdrq = NULL;
1703 if (pd->port_rcvhdrtail_kvaddr) {
1704 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1705 (void *)pd->port_rcvhdrtail_kvaddr,
1706 pd->port_rcvhdrqtailaddr_phys);
1707 pd->port_rcvhdrtail_kvaddr = NULL;
1710 if (pd->port_port && pd->port_rcvegrbuf) {
1713 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
1714 void *base = pd->port_rcvegrbuf[e];
1715 size_t size = pd->port_rcvegrbuf_size;
1717 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
1718 "chunk %u/%u\n", base,
1719 (unsigned long) size,
1720 e, pd->port_rcvegrbuf_chunks);
1721 dma_free_coherent(&dd->pcidev->dev, size,
1722 base, pd->port_rcvegrbuf_phys[e]);
1724 vfree(pd->port_rcvegrbuf);
1725 pd->port_rcvegrbuf = NULL;
1726 vfree(pd->port_rcvegrbuf_phys);
1727 pd->port_rcvegrbuf_phys = NULL;
1728 pd->port_rcvegrbuf_chunks = 0;
1729 } else if (pd->port_port == 0 && dd->ipath_port0_skbs) {
1731 struct sk_buff **skbs = dd->ipath_port0_skbs;
1733 dd->ipath_port0_skbs = NULL;
1734 ipath_cdbg(VERBOSE, "free closed port %d ipath_port0_skbs "
1735 "@ %p\n", pd->port_port, skbs);
1736 for (e = 0; e < dd->ipath_rcvegrcnt; e++)
1738 dev_kfree_skb(skbs[e]);
1741 kfree(pd->port_tid_pg_list);
1745 static int __init infinipath_init(void)
1749 ipath_dbg(KERN_INFO DRIVER_LOAD_MSG "%s", ipath_core_version);
1752 * These must be called before the driver is registered with
1753 * the PCI subsystem.
1755 idr_init(&unit_table);
1756 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
1761 ret = pci_register_driver(&ipath_driver);
1763 printk(KERN_ERR IPATH_DRV_NAME
1764 ": Unable to register driver: error %d\n", -ret);
1768 ret = ipath_driver_create_group(&ipath_driver.driver);
1770 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create driver "
1771 "sysfs entries: error %d\n", -ret);
1775 ret = ipath_init_ipathfs();
1777 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
1778 "ipathfs: error %d\n", -ret);
1785 ipath_driver_remove_group(&ipath_driver.driver);
1788 pci_unregister_driver(&ipath_driver);
1791 idr_destroy(&unit_table);
1797 static void cleanup_device(struct ipath_devdata *dd)
1801 ipath_shutdown_device(dd);
1803 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
1804 /* can't do anything more with chip; needs re-init */
1805 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
1806 if (dd->ipath_kregbase) {
1808 * if we haven't already cleaned up before these are
1809 * to ensure any register reads/writes "fail" until
1812 dd->ipath_kregbase = NULL;
1813 dd->ipath_uregbase = 0;
1814 dd->ipath_sregbase = 0;
1815 dd->ipath_cregbase = 0;
1816 dd->ipath_kregsize = 0;
1818 ipath_disable_wc(dd);
1821 if (dd->ipath_pioavailregs_dma) {
1822 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1823 (void *) dd->ipath_pioavailregs_dma,
1824 dd->ipath_pioavailregs_phys);
1825 dd->ipath_pioavailregs_dma = NULL;
1827 if (dd->ipath_dummy_hdrq) {
1828 dma_free_coherent(&dd->pcidev->dev,
1829 dd->ipath_pd[0]->port_rcvhdrq_size,
1830 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
1831 dd->ipath_dummy_hdrq = NULL;
1834 if (dd->ipath_pageshadow) {
1835 struct page **tmpp = dd->ipath_pageshadow;
1838 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
1840 for (port = 0; port < dd->ipath_cfgports; port++) {
1841 int port_tidbase = port * dd->ipath_rcvtidcnt;
1842 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
1843 for (i = port_tidbase; i < maxtid; i++) {
1846 ipath_release_user_pages(&tmpp[i], 1);
1852 ipath_stats.sps_pageunlocks += cnt;
1853 ipath_cdbg(VERBOSE, "There were still %u expTID "
1854 "entries locked\n", cnt);
1856 if (ipath_stats.sps_pagelocks ||
1857 ipath_stats.sps_pageunlocks)
1858 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
1859 "unlocked via ipath_m{un}lock\n",
1860 (unsigned long long)
1861 ipath_stats.sps_pagelocks,
1862 (unsigned long long)
1863 ipath_stats.sps_pageunlocks);
1865 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
1866 dd->ipath_pageshadow);
1867 vfree(dd->ipath_pageshadow);
1868 dd->ipath_pageshadow = NULL;
1872 * free any resources still in use (usually just kernel ports)
1873 * at unload; we do for portcnt, not cfgports, because cfgports
1874 * could have changed while we were loaded.
1876 for (port = 0; port < dd->ipath_portcnt; port++) {
1877 struct ipath_portdata *pd = dd->ipath_pd[port];
1878 dd->ipath_pd[port] = NULL;
1879 ipath_free_pddata(dd, pd);
1881 kfree(dd->ipath_pd);
1883 * debuggability, in case some cleanup path tries to use it
1886 dd->ipath_pd = NULL;
1889 static void __exit infinipath_cleanup(void)
1891 struct ipath_devdata *dd, *tmp;
1892 unsigned long flags;
1894 ipath_exit_ipathfs();
1896 ipath_driver_remove_group(&ipath_driver.driver);
1898 spin_lock_irqsave(&ipath_devs_lock, flags);
1901 * turn off rcv, send, and interrupts for all ports, all drivers
1902 * should also hard reset the chip here?
1903 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
1904 * for all versions of the driver, if they were allocated
1906 list_for_each_entry_safe(dd, tmp, &ipath_dev_list, ipath_list) {
1907 spin_unlock_irqrestore(&ipath_devs_lock, flags);
1909 if (dd->ipath_kregbase)
1913 if (dd->pcidev->irq) {
1915 "unit %u free_irq of irq %x\n",
1916 dd->ipath_unit, dd->pcidev->irq);
1917 free_irq(dd->pcidev->irq, dd);
1919 ipath_dbg("irq is 0, not doing free_irq "
1920 "for unit %u\n", dd->ipath_unit);
1923 * we check for NULL here, because it's outside
1924 * the kregbase check, and we need to call it
1925 * after the free_irq. Thus it's possible that
1926 * the function pointers were never initialized.
1928 if (dd->ipath_f_cleanup)
1929 /* clean up chip-specific stuff */
1930 dd->ipath_f_cleanup(dd);
1934 spin_lock_irqsave(&ipath_devs_lock, flags);
1937 spin_unlock_irqrestore(&ipath_devs_lock, flags);
1939 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
1940 pci_unregister_driver(&ipath_driver);
1942 idr_destroy(&unit_table);
1946 * ipath_reset_device - reset the chip if possible
1947 * @unit: the device to reset
1949 * Whether or not reset is successful, we attempt to re-initialize the chip
1950 * (that is, much like a driver unload/reload). We clear the INITTED flag
1951 * so that the various entry points will fail until we reinitialize. For
1952 * now, we only allow this if no user ports are open that use chip resources
1954 int ipath_reset_device(int unit)
1957 struct ipath_devdata *dd = ipath_lookup(unit);
1964 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
1966 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
1967 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
1968 "not initialized or not present\n", unit);
1974 for (i = 1; i < dd->ipath_cfgports; i++) {
1975 if (dd->ipath_pd[i] && dd->ipath_pd[i]->port_cnt) {
1976 ipath_dbg("unit %u port %d is in use "
1977 "(PID %u cmd %s), can't reset\n",
1979 dd->ipath_pd[i]->port_pid,
1980 dd->ipath_pd[i]->port_comm);
1986 dd->ipath_flags &= ~IPATH_INITTED;
1987 ret = dd->ipath_f_reset(dd);
1989 ipath_dbg("reset was not successful\n");
1990 ipath_dbg("Trying to reinitialize unit %u after reset attempt\n",
1992 ret = ipath_init_chip(dd, 1);
1994 ipath_dev_err(dd, "Reinitialize unit %u after "
1995 "reset failed with %d\n", unit, ret);
1997 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
1998 "resetting\n", unit);
2004 module_init(infinipath_init);
2005 module_exit(infinipath_cleanup);