2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * This file contains all of the code that is specific to the InfiniPath
39 #include <linux/vmalloc.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/htirq.h>
44 #include "ipath_kernel.h"
45 #include "ipath_registers.h"
47 static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64);
51 * This lists the InfiniPath registers, in the actual chip layout.
52 * This structure should never be directly accessed.
54 * The names are in InterCap form because they're taken straight from
55 * the chip specification. Since they're only used in this file, they
56 * don't pollute the rest of the source.
59 struct _infinipath_do_not_use_kernel_regs {
60 unsigned long long Revision;
61 unsigned long long Control;
62 unsigned long long PageAlign;
63 unsigned long long PortCnt;
64 unsigned long long DebugPortSelect;
65 unsigned long long DebugPort;
66 unsigned long long SendRegBase;
67 unsigned long long UserRegBase;
68 unsigned long long CounterRegBase;
69 unsigned long long Scratch;
70 unsigned long long ReservedMisc1;
71 unsigned long long InterruptConfig;
72 unsigned long long IntBlocked;
73 unsigned long long IntMask;
74 unsigned long long IntStatus;
75 unsigned long long IntClear;
76 unsigned long long ErrorMask;
77 unsigned long long ErrorStatus;
78 unsigned long long ErrorClear;
79 unsigned long long HwErrMask;
80 unsigned long long HwErrStatus;
81 unsigned long long HwErrClear;
82 unsigned long long HwDiagCtrl;
83 unsigned long long MDIO;
84 unsigned long long IBCStatus;
85 unsigned long long IBCCtrl;
86 unsigned long long ExtStatus;
87 unsigned long long ExtCtrl;
88 unsigned long long GPIOOut;
89 unsigned long long GPIOMask;
90 unsigned long long GPIOStatus;
91 unsigned long long GPIOClear;
92 unsigned long long RcvCtrl;
93 unsigned long long RcvBTHQP;
94 unsigned long long RcvHdrSize;
95 unsigned long long RcvHdrCnt;
96 unsigned long long RcvHdrEntSize;
97 unsigned long long RcvTIDBase;
98 unsigned long long RcvTIDCnt;
99 unsigned long long RcvEgrBase;
100 unsigned long long RcvEgrCnt;
101 unsigned long long RcvBufBase;
102 unsigned long long RcvBufSize;
103 unsigned long long RxIntMemBase;
104 unsigned long long RxIntMemSize;
105 unsigned long long RcvPartitionKey;
106 unsigned long long ReservedRcv[10];
107 unsigned long long SendCtrl;
108 unsigned long long SendPIOBufBase;
109 unsigned long long SendPIOSize;
110 unsigned long long SendPIOBufCnt;
111 unsigned long long SendPIOAvailAddr;
112 unsigned long long TxIntMemBase;
113 unsigned long long TxIntMemSize;
114 unsigned long long ReservedSend[9];
115 unsigned long long SendBufferError;
116 unsigned long long SendBufferErrorCONT1;
117 unsigned long long SendBufferErrorCONT2;
118 unsigned long long SendBufferErrorCONT3;
119 unsigned long long ReservedSBE[4];
120 unsigned long long RcvHdrAddr0;
121 unsigned long long RcvHdrAddr1;
122 unsigned long long RcvHdrAddr2;
123 unsigned long long RcvHdrAddr3;
124 unsigned long long RcvHdrAddr4;
125 unsigned long long RcvHdrAddr5;
126 unsigned long long RcvHdrAddr6;
127 unsigned long long RcvHdrAddr7;
128 unsigned long long RcvHdrAddr8;
129 unsigned long long ReservedRHA[7];
130 unsigned long long RcvHdrTailAddr0;
131 unsigned long long RcvHdrTailAddr1;
132 unsigned long long RcvHdrTailAddr2;
133 unsigned long long RcvHdrTailAddr3;
134 unsigned long long RcvHdrTailAddr4;
135 unsigned long long RcvHdrTailAddr5;
136 unsigned long long RcvHdrTailAddr6;
137 unsigned long long RcvHdrTailAddr7;
138 unsigned long long RcvHdrTailAddr8;
139 unsigned long long ReservedRHTA[7];
140 unsigned long long Sync; /* Software only */
141 unsigned long long Dump; /* Software only */
142 unsigned long long SimVer; /* Software only */
143 unsigned long long ReservedSW[5];
144 unsigned long long SerdesConfig0;
145 unsigned long long SerdesConfig1;
146 unsigned long long SerdesStatus;
147 unsigned long long XGXSConfig;
148 unsigned long long ReservedSW2[4];
151 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
152 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
153 #define IPATH_CREG_OFFSET(field) (offsetof( \
154 struct infinipath_counters, field) / sizeof(u64))
156 static const struct ipath_kregs ipath_ht_kregs = {
157 .kr_control = IPATH_KREG_OFFSET(Control),
158 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
159 .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
160 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
161 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
162 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
163 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
164 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
165 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
166 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
167 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
168 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
169 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
170 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
171 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
172 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
173 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
174 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
175 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
176 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
177 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
178 .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
179 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
180 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
181 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
182 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
183 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
184 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
185 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
186 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
187 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
188 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
189 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
190 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
191 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
192 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
193 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
194 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
195 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
196 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
197 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
198 .kr_revision = IPATH_KREG_OFFSET(Revision),
199 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
200 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
201 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
202 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
203 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
204 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
205 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
206 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
207 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
208 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
209 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
210 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
211 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
212 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
213 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
215 * These should not be used directly via ipath_write_kreg64(),
216 * use them with ipath_write_kreg64_port(),
218 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
219 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
222 static const struct ipath_cregs ipath_ht_cregs = {
223 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
224 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
225 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
226 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
227 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
228 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
229 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
230 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
231 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
232 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
233 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
234 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
235 /* calc from Reg_CounterRegBase + offset */
236 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
237 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
238 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
239 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
240 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
241 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
242 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
243 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
244 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
245 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
246 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
247 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
248 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
249 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
250 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
251 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
252 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
253 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
254 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
255 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
256 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
259 /* kr_intstatus, kr_intclear, kr_intmask bits */
260 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
261 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
263 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
264 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
265 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
266 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR 0x0000000000800000ULL
267 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR 0x0000000001000000ULL
268 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR 0x0000000002000000ULL
269 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR 0x0000000004000000ULL
270 #define INFINIPATH_HWE_HTCMISCERR4 0x0000000008000000ULL
271 #define INFINIPATH_HWE_HTCMISCERR5 0x0000000010000000ULL
272 #define INFINIPATH_HWE_HTCMISCERR6 0x0000000020000000ULL
273 #define INFINIPATH_HWE_HTCMISCERR7 0x0000000040000000ULL
274 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR 0x0000000080000000ULL
275 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
276 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR 0x0000000200000000ULL
277 #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
278 #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
279 #define INFINIPATH_HWE_HTBPLL_FBSLIP 0x0200000000000000ULL
280 #define INFINIPATH_HWE_HTBPLL_RFSLIP 0x0400000000000000ULL
281 #define INFINIPATH_HWE_HTAPLL_FBSLIP 0x0800000000000000ULL
282 #define INFINIPATH_HWE_HTAPLL_RFSLIP 0x1000000000000000ULL
283 #define INFINIPATH_HWE_SERDESPLLFAILED 0x2000000000000000ULL
285 /* kr_extstatus bits */
286 #define INFINIPATH_EXTS_FREQSEL 0x2
287 #define INFINIPATH_EXTS_SERDESSEL 0x4
288 #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
289 #define INFINIPATH_EXTS_MEMBIST_CORRECT 0x0000000000008000
292 /* TID entries (memory), HT-only */
293 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
294 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
295 #define INFINIPATH_RT_ADDR_SHIFT 0
296 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
297 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
300 * masks and bits that are different in different chips, or present only
303 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
304 INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
305 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
306 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
308 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
309 INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
310 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
311 INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
312 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
313 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
314 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
315 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
317 #define _IPATH_GPIO_SDA_NUM 1
318 #define _IPATH_GPIO_SCL_NUM 0
320 #define IPATH_GPIO_SDA \
321 (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
322 #define IPATH_GPIO_SCL \
323 (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
325 /* keep the code below somewhat more readonable; not used elsewhere */
326 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
327 infinipath_hwe_htclnkabyte1crcerr)
328 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr | \
329 infinipath_hwe_htclnkbbyte1crcerr)
330 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
331 infinipath_hwe_htclnkbbyte0crcerr)
332 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr | \
333 infinipath_hwe_htclnkbbyte1crcerr)
335 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
336 char *msg, size_t msgl)
339 ipath_err_t crcbits = hwerrs &
340 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
341 /* don't check if 8bit HT */
342 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
343 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
344 /* don't check if 8bit HT */
345 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
346 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
348 * we'll want to ignore link errors on link that is
349 * not in use, if any. For now, complain about both
353 snprintf(bitsmsg, sizeof bitsmsg,
354 "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
355 !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
356 "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
357 ? "1 (B)" : "0+1 (A+B)"),
358 !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
359 : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
360 "0+1"), (unsigned long long) crcbits);
361 strlcat(msg, bitsmsg, msgl);
364 * print extra info for debugging. slave/primary
365 * config word 4, 8 (link control 0, 1)
368 if (pci_read_config_word(dd->pcidev,
369 dd->ipath_ht_slave_off + 0x4,
371 dev_info(&dd->pcidev->dev, "Couldn't read "
372 "linkctrl0 of slave/primary "
374 else if (!(ctrl0 & 1 << 6))
375 /* not if EOC bit set */
376 ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
377 ((ctrl0 >> 8) & 7) ? " CRC" : "",
378 ((ctrl0 >> 4) & 1) ? "linkfail" :
380 if (pci_read_config_word(dd->pcidev,
381 dd->ipath_ht_slave_off + 0x8,
383 dev_info(&dd->pcidev->dev, "Couldn't read "
384 "linkctrl1 of slave/primary "
386 else if (!(ctrl1 & 1 << 6))
387 /* not if EOC bit set */
388 ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
389 ((ctrl1 >> 8) & 7) ? " CRC" : "",
390 ((ctrl1 >> 4) & 1) ? "linkfail" :
393 /* disable until driver reloaded */
394 dd->ipath_hwerrmask &= ~crcbits;
395 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
396 dd->ipath_hwerrmask);
397 ipath_dbg("HT crc errs: %s\n", msg);
399 ipath_dbg("ignoring HT crc errors 0x%llx, "
400 "not in use\n", (unsigned long long)
401 (hwerrs & (_IPATH_HTLINK0_CRCBITS |
402 _IPATH_HTLINK1_CRCBITS)));
405 /* 6110 specific hardware errors... */
406 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
407 INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
408 INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
409 INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
410 INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
411 INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
412 INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
413 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
414 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
417 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
418 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
419 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
420 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
421 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
423 static int ipath_ht_txe_recover(struct ipath_devdata *);
426 * ipath_ht_handle_hwerrors - display hardware errors.
427 * @dd: the infinipath device
428 * @msg: the output buffer
429 * @msgl: the size of the output buffer
431 * Use same msg buffer as regular errors to avoid excessive stack
432 * use. Most hardware errors are catastrophic, but for right now,
433 * we'll print them and continue. We reuse the same message buffer as
434 * ipath_handle_errors() to avoid excessive stack usage.
436 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
445 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
448 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
450 * better than printing cofusing messages
451 * This seems to be related to clearing the crc error, or
452 * the pll error during init.
455 } else if (hwerrs == -1LL) {
456 ipath_dev_err(dd, "Read of hardware error status failed "
457 "(all bits set); ignoring\n");
460 ipath_stats.sps_hwerrs++;
462 /* Always clear the error status register, except MEMBISTFAIL,
463 * regardless of whether we continue or stop using the chip.
464 * We want that set so we know it failed, even across driver reload.
465 * We'll still ignore it in the hwerrmask. We do this partly for
466 * diagnostics, but also for support */
467 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
468 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
470 hwerrs &= dd->ipath_hwerrmask;
472 /* We log some errors to EEPROM, check if we have any of those. */
473 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
474 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
475 ipath_inc_eeprom_err(dd, log_idx, 1);
478 * make sure we get this much out, unless told to be quiet,
479 * it's a parity error we may recover from,
480 * or it's occurred within the last 5 seconds
482 if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
483 RXE_EAGER_PARITY)) ||
484 (ipath_debug & __IPATH_VERBDBG))
485 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
486 "(cleared)\n", (unsigned long long) hwerrs);
487 dd->ipath_lasthwerror |= hwerrs;
489 if (hwerrs & ~dd->ipath_hwe_bitsextant)
490 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
491 "%llx set\n", (unsigned long long)
492 (hwerrs & ~dd->ipath_hwe_bitsextant));
494 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
495 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
497 * parity errors in send memory are recoverable,
498 * just cancel the send (if indicated in * sendbuffererror),
499 * count the occurrence, unfreeze (if no other handled
500 * hardware error bits are set), and continue. They can
501 * occur if a processor speculative read is done to the PIO
502 * buffer while we are sending a packet, for example.
504 if ((hwerrs & TXE_PIO_PARITY) && ipath_ht_txe_recover(dd))
505 hwerrs &= ~TXE_PIO_PARITY;
506 if (hwerrs & RXE_EAGER_PARITY)
507 ipath_dev_err(dd, "RXE parity, Eager TID error is not "
510 ipath_dbg("Clearing freezemode on ignored or "
511 "recovered hardware error\n");
513 * clear all sends, becauase they have may been
514 * completed by usercode while in freeze mode, and
515 * therefore would not be sent, and eventually
516 * might cause the process to run out of bufs
518 ipath_cancel_sends(dd);
519 ctrl &= ~INFINIPATH_C_FREEZEMODE;
520 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
528 * may someday want to decode into which bits are which
529 * functional area for parity errors, etc.
531 if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
532 << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
533 bits = (u32) ((hwerrs >>
534 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
535 INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
536 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
538 strlcat(msg, bitsmsg, msgl);
541 ipath_format_hwerrors(hwerrs,
542 ipath_6110_hwerror_msgs,
543 sizeof(ipath_6110_hwerror_msgs) /
544 sizeof(ipath_6110_hwerror_msgs[0]),
547 if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
548 hwerr_crcbits(dd, hwerrs, msg, msgl);
550 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
551 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
553 /* ignore from now on, so disable until driver reloaded */
554 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
555 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
556 dd->ipath_hwerrmask);
558 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
559 INFINIPATH_HWE_COREPLL_RFSLIP | \
560 INFINIPATH_HWE_HTBPLL_FBSLIP | \
561 INFINIPATH_HWE_HTBPLL_RFSLIP | \
562 INFINIPATH_HWE_HTAPLL_FBSLIP | \
563 INFINIPATH_HWE_HTAPLL_RFSLIP)
565 if (hwerrs & _IPATH_PLL_FAIL) {
566 snprintf(bitsmsg, sizeof bitsmsg,
567 "[PLL failed (%llx), InfiniPath hardware unusable]",
568 (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
569 strlcat(msg, bitsmsg, msgl);
570 /* ignore from now on, so disable until driver reloaded */
571 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
572 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
573 dd->ipath_hwerrmask);
576 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
578 * If it occurs, it is left masked since the eternal
579 * interface is unused
581 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
582 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
583 dd->ipath_hwerrmask);
588 * if any set that we aren't ignoring; only
589 * make the complaint once, in case it's stuck
590 * or recurring, and we get here multiple
592 * force link down, so switch knows, and
593 * LEDs are turned off
595 if (dd->ipath_flags & IPATH_INITTED) {
596 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
597 ipath_setup_ht_setextled(dd,
598 INFINIPATH_IBCS_L_STATE_DOWN,
599 INFINIPATH_IBCS_LT_STATE_DISABLED);
600 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
601 "mode), no longer usable, SN %.16s\n",
605 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
606 /* mark as having had error */
607 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
609 * mark as not usable, at a minimum until driver
610 * is reloaded, probably until reboot, since no
611 * other reset is possible.
613 dd->ipath_flags &= ~IPATH_INITTED;
616 *msg = 0; /* recovered from all of them */
618 ipath_dev_err(dd, "%s hardware error\n", msg);
619 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
621 * for status file; if no trailing brace is copied,
622 * we'll know it was truncated.
624 snprintf(dd->ipath_freezemsg,
625 dd->ipath_freezelen, "{%s}", msg);
631 * ipath_ht_boardname - fill in the board name
632 * @dd: the infinipath device
633 * @name: the output buffer
634 * @namelen: the size of the output buffer
636 * fill in the board name, based on the board revision register
638 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
642 u8 boardrev = dd->ipath_boardrev;
646 case 4: /* Ponderosa is one of the bringup boards */
651 * original production board; two production levels, with
652 * different serial number ranges. See ipath_ht_early_init() for
653 * case where we enable IPATH_GPIO_INTR for later serial # range.
655 n = "InfiniPath_QHT7040";
661 /* small form factor production board */
662 n = "InfiniPath_QHT7140";
667 case 9: /* Comstock bringup test board */
674 n = "InfiniPath_HT-470"; /* obsoleted */
679 default: /* don't know, just print the number */
680 ipath_dev_err(dd, "Don't yet know about board "
681 "with ID %u\n", boardrev);
682 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
687 snprintf(name, namelen, "%s", n);
689 if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
690 dd->ipath_minrev > 4)) {
692 * This version of the driver only supports Rev 3.2 - 3.4
695 "Unsupported InfiniPath hardware revision %u.%u!\n",
696 dd->ipath_majrev, dd->ipath_minrev);
701 * pkt/word counters are 32 bit, and therefore wrap fast enough
702 * that we snapshot them from a timer, and maintain 64 bit shadow
705 dd->ipath_flags |= IPATH_32BITCOUNTERS;
706 if (dd->ipath_htspeed != 800)
708 "Incorrectly configured for HT @ %uMHz\n",
710 if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 ||
711 dd->ipath_boardrev == 6)
712 dd->ipath_flags |= IPATH_GPIO_INTR;
714 dd->ipath_flags |= IPATH_POLL_RX_INTR;
715 if (dd->ipath_boardrev == 8) { /* LS/X-1 */
717 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
718 if (val & INFINIPATH_EXTS_SERDESSEL) {
722 * This means that the chip is hardware disabled,
723 * and will not be able to bring up the link,
724 * in any case. We special case this and abort
725 * early, to avoid later messages. We also set
726 * the DISABLED status bit
728 ipath_dbg("Unit %u is hardware-disabled\n",
730 *dd->ipath_statusp |= IPATH_STATUS_DISABLED;
731 /* this value is handled differently */
742 static void ipath_check_htlink(struct ipath_devdata *dd)
744 u8 linkerr, link_off, i;
746 for (i = 0; i < 2; i++) {
747 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
748 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
749 dev_info(&dd->pcidev->dev, "Couldn't read "
750 "linkerror%d of HT slave/primary block\n",
752 else if (linkerr & 0xf0) {
753 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
754 "clearing\n", linkerr >> 4, i);
756 * writing the linkerr bits that are set should
759 if (pci_write_config_byte(dd->pcidev, link_off,
761 ipath_dbg("Failed write to clear HT "
763 if (pci_read_config_byte(dd->pcidev, link_off,
765 dev_info(&dd->pcidev->dev,
766 "Couldn't reread linkerror%d of "
767 "HT slave/primary block\n", i);
768 else if (linkerr & 0xf0)
769 dev_info(&dd->pcidev->dev,
770 "HT linkerror%d bits 0x%x "
771 "couldn't be cleared\n",
777 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
779 ipath_dbg("No reset possible for this InfiniPath hardware\n");
783 #define HT_INTR_DISC_CONFIG 0x80 /* HT interrupt and discovery cap */
784 #define HT_INTR_REG_INDEX 2 /* intconfig requires indirect accesses */
787 * Bits 13-15 of command==0 is slave/primary block. Clear any HT CRC
788 * errors. We only bother to do this at load time, because it's OK if
789 * it happened before we were loaded (first time after boot/reset),
790 * but any time after that, it's fatal anyway. Also need to not check
791 * for for upper byte errors if we are in 8 bit mode, so figure out
792 * our width. For now, at least, also complain if it's 8 bit.
794 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
795 int pos, u8 cap_type)
797 u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
801 dd->ipath_ht_slave_off = pos;
802 /* command word, master_host bit */
803 /* master host || slave */
804 if ((cap_type >> 2) & 1)
808 ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
809 link_a_b_off ? 1 : 0,
810 link_a_b_off ? 'B' : 'A');
815 * check both link control registers; clear both HT CRC sets if
818 for (i = 0; i < 2; i++) {
819 link_off = pos + i * 4 + 0x4;
820 if (pci_read_config_word(pdev, link_off, &linkctrl))
821 ipath_dev_err(dd, "Couldn't read HT link control%d "
823 else if (linkctrl & (0xf << 8)) {
824 ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
825 "bits %x\n", i, linkctrl & (0xf << 8));
827 * now write them back to clear the error.
829 pci_write_config_byte(pdev, link_off,
830 linkctrl & (0xf << 8));
835 * As with HT CRC bits, same for protocol errors that might occur
838 for (i = 0; i < 2; i++) {
839 link_off = pos + i * 4 + 0xd;
840 if (pci_read_config_byte(pdev, link_off, &linkerr))
841 dev_info(&pdev->dev, "Couldn't read linkerror%d "
842 "of HT slave/primary block\n", i);
843 else if (linkerr & 0xf0) {
844 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
845 "clearing\n", linkerr >> 4, i);
847 * writing the linkerr bits that are set will clear
850 if (pci_write_config_byte
851 (pdev, link_off, linkerr))
852 ipath_dbg("Failed write to clear HT "
854 if (pci_read_config_byte(pdev, link_off, &linkerr))
855 dev_info(&pdev->dev, "Couldn't reread "
856 "linkerror%d of HT slave/primary "
858 else if (linkerr & 0xf0)
859 dev_info(&pdev->dev, "HT linkerror%d bits "
860 "0x%x couldn't be cleared\n",
866 * this is just for our link to the host, not devices connected
870 if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
871 ipath_dev_err(dd, "Couldn't read HT link width "
872 "config register\n");
875 switch (linkwidth & 7) {
889 default: /* if wrong, assume 8 bit */
894 dd->ipath_htwidth = width;
896 if (linkwidth != 0x11) {
897 ipath_dev_err(dd, "Not configured for 16 bit HT "
898 "(%x)\n", linkwidth);
899 if (!(linkwidth & 0xf)) {
900 ipath_dbg("Will ignore HT lane1 errors\n");
901 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
907 * this is just for our link to the host, not devices connected
910 if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
911 ipath_dev_err(dd, "Couldn't read HT link frequency "
912 "config register\n");
915 switch (linkwidth & 0xf) {
936 * assume reserved and vendor-specific are 200...
942 dd->ipath_htspeed = speed;
946 static int ipath_ht_intconfig(struct ipath_devdata *dd)
950 if (dd->ipath_intconfig) {
951 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
952 dd->ipath_intconfig); /* interrupt address */
955 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
956 "interrupt address\n");
963 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
964 struct ht_irq_msg *msg)
966 struct ipath_devdata *dd = pci_get_drvdata(dev);
967 u64 prev_intconfig = dd->ipath_intconfig;
969 dd->ipath_intconfig = msg->address_lo;
970 dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
973 * If the previous value of dd->ipath_intconfig is zero, we're
974 * getting configured for the first time, and must not program the
975 * intconfig register here (it will be programmed later, when the
976 * hardware is ready). Otherwise, we should.
979 ipath_ht_intconfig(dd);
983 * ipath_setup_ht_config - setup the interruptconfig register
984 * @dd: the infinipath device
985 * @pdev: the PCI device
987 * setup the interruptconfig register from the HT config info.
988 * Also clear CRC errors in HT linkcontrol, if necessary.
989 * This is done only for the real hardware. It is done before
990 * chip address space is initted, so can't touch infinipath registers
992 static int ipath_setup_ht_config(struct ipath_devdata *dd,
993 struct pci_dev *pdev)
997 ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
999 ipath_dev_err(dd, "Couldn't create interrupt handler: "
1003 dd->ipath_irq = ret;
1007 * Handle clearing CRC errors in linkctrl register if necessary. We
1008 * do this early, before we ever enable errors or hardware errors,
1009 * mostly to avoid causing the chip to enter freeze mode.
1011 pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
1013 ipath_dev_err(dd, "Couldn't find HyperTransport "
1014 "capability; no interrupts\n");
1021 /* the HT capability type byte is 3 bytes after the
1024 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
1025 dev_info(&pdev->dev, "Couldn't read config "
1026 "command @ %d\n", pos);
1029 if (!(cap_type & 0xE0))
1030 slave_or_pri_blk(dd, pdev, pos, cap_type);
1031 } while ((pos = pci_find_next_capability(pdev, pos,
1039 * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1040 * @dd: the infinipath device
1042 * Called during driver unload.
1043 * This is currently a nop for the HT chip, not for all chips
1045 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1050 * ipath_setup_ht_setextled - set the state of the two external LEDs
1051 * @dd: the infinipath device
1053 * @ltst: the LT state
1055 * Set the state of the two external LEDs, to indicate physical and
1056 * logical state of IB link. For this chip (at least with recommended
1057 * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1060 * Note: We try to match the Mellanox HCA LED behavior as best
1061 * we can. Green indicates physical link state is OK (something is
1062 * plugged in, and we can train).
1063 * Amber indicates the link is logically up (ACTIVE).
1064 * Mellanox further blinks the amber LED to indicate data packet
1065 * activity, but we have no hardware support for that, so it would
1066 * require waking up every 10-20 msecs and checking the counters
1067 * on the chip, and then turning the LED off if appropriate. That's
1068 * visible overhead, so not something we will do.
1071 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1075 unsigned long flags = 0;
1077 /* the diags use the LED to indicate diag info, so we leave
1078 * the external LED alone when the diags are running */
1079 if (ipath_diag_inuse)
1082 /* Allow override of LED display for, e.g. Locating system in rack */
1083 if (dd->ipath_led_override) {
1084 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1085 ? INFINIPATH_IBCS_LT_STATE_LINKUP
1086 : INFINIPATH_IBCS_LT_STATE_DISABLED;
1087 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1088 ? INFINIPATH_IBCS_L_STATE_ACTIVE
1089 : INFINIPATH_IBCS_L_STATE_DOWN;
1092 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1094 * start by setting both LED control bits to off, then turn
1095 * on the appropriate bit(s).
1097 if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1099 * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1100 * is inverted, because it is normally used to indicate
1101 * a hardware fault at reset, if there were errors
1103 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1104 | INFINIPATH_EXTC_LEDGBLERR_OFF;
1105 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1106 extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1107 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1108 extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1111 extctl = dd->ipath_extctrl &
1112 ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1113 INFINIPATH_EXTC_LED2PRIPORT_ON);
1114 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1115 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1116 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1117 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1119 dd->ipath_extctrl = extctl;
1120 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1121 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1124 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1126 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1127 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1128 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1129 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1131 dd->ipath_i_bitsextant =
1132 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1133 (INFINIPATH_I_RCVAVAIL_MASK <<
1134 INFINIPATH_I_RCVAVAIL_SHIFT) |
1135 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1136 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1138 dd->ipath_e_bitsextant =
1139 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1140 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1141 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1142 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1143 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1144 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1145 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1146 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1147 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1148 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1149 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1150 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1151 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1152 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1153 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1154 INFINIPATH_E_HARDWARE;
1156 dd->ipath_hwe_bitsextant =
1157 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1158 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1159 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1160 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1161 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1162 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1163 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1164 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1165 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1166 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1167 INFINIPATH_HWE_HTCMISCERR4 |
1168 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1169 INFINIPATH_HWE_HTCMISCERR7 |
1170 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1171 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1172 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1173 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1174 INFINIPATH_HWE_MEMBISTFAILED |
1175 INFINIPATH_HWE_COREPLL_FBSLIP |
1176 INFINIPATH_HWE_COREPLL_RFSLIP |
1177 INFINIPATH_HWE_HTBPLL_FBSLIP |
1178 INFINIPATH_HWE_HTBPLL_RFSLIP |
1179 INFINIPATH_HWE_HTAPLL_FBSLIP |
1180 INFINIPATH_HWE_HTAPLL_RFSLIP |
1181 INFINIPATH_HWE_SERDESPLLFAILED |
1182 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1183 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1185 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1186 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1189 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1190 * 2 is Some Misc, 3 is reserved for future.
1192 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1193 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1194 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1196 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1197 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1198 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1200 dd->ipath_eep_st_masks[2].errs_to_log =
1201 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1206 * ipath_ht_init_hwerrors - enable hardware errors
1207 * @dd: the infinipath device
1209 * now that we have finished initializing everything that might reasonably
1210 * cause a hardware error, and cleared those errors bits as they occur,
1211 * we can enable hardware errors in the mask (potentially enabling
1212 * freeze mode), and enable hardware errors as errors (along with
1213 * everything else) in errormask
1215 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1220 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1222 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1223 ipath_dev_err(dd, "MemBIST did not complete!\n");
1224 if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1225 ipath_dbg("MemBIST corrected\n");
1227 ipath_check_htlink(dd);
1229 /* barring bugs, all hwerrors become interrupts, which can */
1231 /* don't look at crc lane1 if 8 bit */
1232 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1233 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1234 /* don't look at crc lane1 if 8 bit */
1235 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1236 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1239 * disable RXDSYNCMEMPARITY because external serdes is unused,
1240 * and therefore the logic will never be used or initialized,
1241 * and uninitialized state will normally result in this error
1242 * being asserted. Similarly for the external serdess pll
1245 val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1246 INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1249 * Disable MISCERR4 because of an inversion in the HT core
1250 * logic checking for errors that cause this bit to be set.
1251 * The errata can also cause the protocol error bit to be set
1252 * in the HT config space linkerror register(s).
1254 val &= ~INFINIPATH_HWE_HTCMISCERR4;
1257 * PLL ignored because MDIO interface has a logic problem
1258 * for reads, on Comstock and Ponderosa. BRINGUP
1260 if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1261 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1262 dd->ipath_hwerrmask = val;
1266 * ipath_ht_bringup_serdes - bring up the serdes
1267 * @dd: the infinipath device
1269 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1272 int ret = 0, change = 0;
1274 ipath_dbg("Trying to bringup serdes\n");
1276 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1277 INFINIPATH_HWE_SERDESPLLFAILED)
1279 ipath_dbg("At start, serdes PLL failed bit set in "
1280 "hwerrstatus, clearing and continuing\n");
1281 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1282 INFINIPATH_HWE_SERDESPLLFAILED);
1285 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1286 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1288 ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1289 "config1=%llx, sstatus=%llx xgxs %llx\n",
1290 (unsigned long long) val, (unsigned long long) config1,
1291 (unsigned long long)
1292 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1293 (unsigned long long)
1294 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1296 /* force reset on */
1297 val |= INFINIPATH_SERDC0_RESET_PLL
1298 /* | INFINIPATH_SERDC0_RESET_MASK */
1300 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1301 udelay(15); /* need pll reset set at least for a bit */
1303 if (val & INFINIPATH_SERDC0_RESET_PLL) {
1304 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1305 /* set lane resets, and tx idle, during pll reset */
1306 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1307 INFINIPATH_SERDC0_TXIDLE;
1308 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1309 "%llx)\n", (unsigned long long) val2);
1310 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1313 * be sure chip saw it
1315 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1317 * need pll reset clear at least 11 usec before lane
1318 * resets cleared; give it a few more
1321 val = val2; /* for check below */
1324 if (val & (INFINIPATH_SERDC0_RESET_PLL |
1325 INFINIPATH_SERDC0_RESET_MASK |
1326 INFINIPATH_SERDC0_TXIDLE)) {
1327 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1328 INFINIPATH_SERDC0_RESET_MASK |
1329 INFINIPATH_SERDC0_TXIDLE);
1331 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1335 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1336 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1337 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1338 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1339 INFINIPATH_XGXS_MDIOADDR_SHIFT);
1343 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1346 if (val & INFINIPATH_XGXS_RESET) {
1347 /* normally true after boot */
1348 val &= ~INFINIPATH_XGXS_RESET;
1351 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1352 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1353 /* need to compensate for Tx inversion in partner */
1354 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1355 INFINIPATH_XGXS_RX_POL_SHIFT);
1356 val |= dd->ipath_rx_pol_inv <<
1357 INFINIPATH_XGXS_RX_POL_SHIFT;
1361 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1363 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1365 /* clear current and de-emphasis bits */
1366 config1 &= ~0x0ffffffff00ULL;
1367 /* set current to 20ma */
1368 config1 |= 0x00000000000ULL;
1369 /* set de-emphasis to -5.68dB */
1370 config1 |= 0x0cccc000000ULL;
1371 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1373 ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1374 "config1=%llx, sstatus=%llx xgxs %llx\n",
1375 (unsigned long long) val, (unsigned long long) config1,
1376 (unsigned long long)
1377 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1378 (unsigned long long)
1379 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1381 if (!ipath_waitfor_mdio_cmdready(dd)) {
1382 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1383 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1384 IPATH_MDIO_CTRL_XGXS_REG_8,
1386 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1387 IPATH_MDIO_DATAVALID, &val))
1388 ipath_dbg("Never got MDIO data for XGXS status "
1391 ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1392 "'bank' 31 %x\n", (u32) val);
1394 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1396 return ret; /* for now, say we always succeeded */
1400 * ipath_ht_quiet_serdes - set serdes to txidle
1401 * @dd: the infinipath device
1402 * driver is being unloaded
1404 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1406 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1408 val |= INFINIPATH_SERDC0_TXIDLE;
1409 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1410 (unsigned long long) val);
1411 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1415 * ipath_pe_put_tid - write a TID in chip
1416 * @dd: the infinipath device
1417 * @tidptr: pointer to the expected TID (in chip) to udpate
1418 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1419 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1421 * This exists as a separate routine to allow for special locking etc.
1422 * It's used for both the full cleanup on exit, as well as the normal
1423 * setup and teardown.
1425 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1426 u64 __iomem *tidptr, u32 type,
1429 if (!dd->ipath_kregbase)
1432 if (pa != dd->ipath_tidinvalid) {
1433 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1434 dev_info(&dd->pcidev->dev,
1435 "physaddr %lx has more than "
1436 "40 bits, using only 40!!!\n", pa);
1437 pa &= INFINIPATH_RT_ADDR_MASK;
1439 if (type == RCVHQ_RCV_TYPE_EAGER)
1440 pa |= dd->ipath_tidtemplate;
1442 /* in words (fixed, full page). */
1443 u64 lenvalid = PAGE_SIZE >> 2;
1444 lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1445 pa |= lenvalid | INFINIPATH_RT_VALID;
1453 * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1454 * @dd: the infinipath device
1457 * Used from ipath_close(), and at chip initialization.
1459 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1461 u64 __iomem *tidbase;
1464 if (!dd->ipath_kregbase)
1467 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1470 * need to invalidate all of the expected TID entries for this
1471 * port, so we don't have valid entries that might somehow get
1472 * used (early in next use of this port, or through some bug)
1474 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1475 dd->ipath_rcvtidbase +
1476 port * dd->ipath_rcvtidcnt *
1478 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1479 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1480 dd->ipath_tidinvalid);
1482 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1483 dd->ipath_rcvegrbase +
1484 port * dd->ipath_rcvegrcnt *
1487 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1488 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1489 dd->ipath_tidinvalid);
1493 * ipath_ht_tidtemplate - setup constants for TID updates
1494 * @dd: the infinipath device
1496 * We setup stuff that we use a lot, to avoid calculating each time
1498 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1500 dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1501 dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1502 dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1505 * work around chip errata bug 7358, by marking invalid tids
1506 * as having max length
1508 dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1509 INFINIPATH_RT_BUFSIZE_SHIFT;
1512 static int ipath_ht_early_init(struct ipath_devdata *dd)
1514 u32 __iomem *piobuf;
1519 * one cache line; long IB headers will spill over into received
1522 dd->ipath_rcvhdrentsize = 16;
1523 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1526 * For HT, we allocate a somewhat overly large eager buffer,
1527 * such that we can guarantee that we can receive the largest
1528 * packet that we can send out. To truly support a 4KB MTU,
1529 * we need to bump this to a large value. To date, other than
1530 * testing, we have never encountered an HCA that can really
1531 * send 4KB MTU packets, so we do not handle that (we'll get
1532 * errors interrupts if we ever see one).
1534 dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1537 * the min() check here is currently a nop, but it may not
1538 * always be, depending on just how we do ipath_rcvegrbufsize
1540 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1541 dd->ipath_rcvegrbufsize);
1542 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1543 ipath_ht_tidtemplate(dd);
1546 * zero all the TID entries at startup. We do this for sanity,
1547 * in case of a previous driver crash of some kind, and also
1548 * because the chip powers up with these memories in an unknown
1549 * state. Use portcnt, not cfgports, since this is for the
1550 * full chip, not for current (possibly different) configuration
1552 * Chip Errata bug 6447
1554 for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1555 ipath_ht_clear_tids(dd, val32);
1558 * write the pbc of each buffer, to be sure it's initialized, then
1559 * cancel all the buffers, and also abort any packets that might
1560 * have been in flight for some reason (the latter is for driver
1561 * unload/reload, but isn't a bad idea at first init). PIO send
1562 * isn't enabled at this point, so there is no danger of sending
1563 * these out on the wire.
1564 * Chip Errata bug 6610
1566 piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1567 dd->ipath_piobufbase);
1568 pioincr = dd->ipath_palign / sizeof(*piobuf);
1569 for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1571 * reasonable word count, just to init pbc
1577 ipath_get_eeprom_info(dd);
1578 if (dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1579 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1581 * Later production QHT7040 has same changes as QHT7140, so
1582 * can use GPIO interrupts. They have serial #'s starting
1583 * with 128, rather than 112.
1585 dd->ipath_flags |= IPATH_GPIO_INTR;
1586 dd->ipath_flags &= ~IPATH_POLL_RX_INTR;
1592 static int ipath_ht_txe_recover(struct ipath_devdata *dd)
1594 int cnt = ++ipath_stats.sps_txeparity;
1595 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS) {
1596 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1598 "Too many attempts to recover from "
1599 "TXE parity, giving up\n");
1602 dev_info(&dd->pcidev->dev,
1603 "Recovering from TXE PIO parity error\n");
1609 * ipath_init_ht_get_base_info - set chip-specific flags for user code
1610 * @dd: the infinipath device
1611 * @kbase: ipath_base_info pointer
1613 * We set the PCIE flag because the lower bandwidth on PCIe vs
1614 * HyperTransport can affect some user packet algorithms.
1616 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1618 struct ipath_base_info *kinfo = kbase;
1620 kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1621 IPATH_RUNTIME_RCVHDR_COPY;
1626 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1628 free_irq(dd->ipath_irq, dd);
1629 ht_destroy_irq(dd->ipath_irq);
1631 dd->ipath_intconfig = 0;
1635 * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1636 * @dd: the infinipath device
1638 * This is global, and is called directly at init to set up the
1639 * chip-specific function pointers for later use.
1641 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1643 dd->ipath_f_intrsetup = ipath_ht_intconfig;
1644 dd->ipath_f_bus = ipath_setup_ht_config;
1645 dd->ipath_f_reset = ipath_setup_ht_reset;
1646 dd->ipath_f_get_boardname = ipath_ht_boardname;
1647 dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1648 dd->ipath_f_early_init = ipath_ht_early_init;
1649 dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1650 dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1651 dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1652 dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1653 dd->ipath_f_put_tid = ipath_ht_put_tid;
1654 dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1655 dd->ipath_f_setextled = ipath_setup_ht_setextled;
1656 dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1657 dd->ipath_f_free_irq = ipath_ht_free_irq;
1660 * initialize chip-specific variables
1662 dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1665 * setup the register offsets, since they are different for each
1668 dd->ipath_kregs = &ipath_ht_kregs;
1669 dd->ipath_cregs = &ipath_ht_cregs;
1672 * do very early init that is needed before ipath_f_bus is
1675 ipath_init_ht_variables(dd);