drivers/infiniband/hw/mlx4/cq.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/mlx4/cq.h>
  35 #include <linux/mlx4/qp.h>
  36 #include <linux/mlx4/srq.h>
  37 #include <linux/slab.h>
  38
  39 #include "mlx4_ib.h"
  40 #include "user.h"
  41
  42 static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
  43 {
  44         struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
  45         ibcq->comp_handler(ibcq, ibcq->cq_context);
  46 }
  47
  48 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
  49 {
  50         struct ib_event event;
  51         struct ib_cq *ibcq;
  52
  53         if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
  54                 pr_warn("Unexpected event type %d "
  55                        "on CQ %06x\n", type, cq->cqn);
  56                 return;
  57         }
  58
  59         ibcq = &to_mibcq(cq)->ibcq;
  60         if (ibcq->event_handler) {
  61                 event.device     = ibcq->device;
  62                 event.event      = IB_EVENT_CQ_ERR;
  63                 event.element.cq = ibcq;
  64                 ibcq->event_handler(&event, ibcq->cq_context);
  65         }
  66 }
  67
  68 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
  69 {
  70         return mlx4_buf_offset(&buf->buf, n * buf->entry_size);
  71 }
  72
  73 static void *get_cqe(struct mlx4_ib_cq *cq, int n)
  74 {
  75         return get_cqe_from_buf(&cq->buf, n);
  76 }
  77
  78 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
  79 {
  80         struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
  81         struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe);
  82
  83         return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
  84                 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
  85 }
  86
  87 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
  88 {
  89         return get_sw_cqe(cq, cq->mcq.cons_index);
  90 }
  91
  92 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
  93 {
  94         struct mlx4_ib_cq *mcq = to_mcq(cq);
  95         struct mlx4_ib_dev *dev = to_mdev(cq->device);
  96
  97         return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
  98 }
  99
 100 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
 101 {
 102         int err;
 103
 104         err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size,
 105                              PAGE_SIZE * 2, &buf->buf, GFP_KERNEL);
 106
 107         if (err)
 108                 goto out;
 109
 110         buf->entry_size = dev->dev->caps.cqe_size;
 111         err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
 112                                     &buf->mtt);
 113         if (err)
 114                 goto err_buf;
 115
 116         err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf, GFP_KERNEL);
 117         if (err)
 118                 goto err_mtt;
 119
 120         return 0;
 121
 122 err_mtt:
 123         mlx4_mtt_cleanup(dev->dev, &buf->mtt);
 124
 125 err_buf:
 126         mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf);
 127
 128 out:
 129         return err;
 130 }
 131
 132 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
 133 {
 134         mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf);
 135 }
 136
 137 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
 138                                struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
 139                                u64 buf_addr, int cqe)
 140 {
 141         int err;
 142         int cqe_size = dev->dev->caps.cqe_size;
 143
 144         *umem = ib_umem_get(context, buf_addr, cqe * cqe_size,
 145                             IB_ACCESS_LOCAL_WRITE, 1);
 146         if (IS_ERR(*umem))
 147                 return PTR_ERR(*umem);
 148
 149         err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
 150                             ilog2((*umem)->page_size), &buf->mtt);
 151         if (err)
 152                 goto err_buf;
 153
 154         err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
 155         if (err)
 156                 goto err_mtt;
 157
 158         return 0;
 159
 160 err_mtt:
 161         mlx4_mtt_cleanup(dev->dev, &buf->mtt);
 162
 163 err_buf:
 164         ib_umem_release(*umem);
 165
 166         return err;
 167 }
 168
 169 struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev,
 170                                 const struct ib_cq_init_attr *attr,
 171                                 struct ib_ucontext *context,
 172                                 struct ib_udata *udata)
 173 {
 174         int entries = attr->cqe;
 175         int vector = attr->comp_vector;
 176         struct mlx4_ib_dev *dev = to_mdev(ibdev);
 177         struct mlx4_ib_cq *cq;
 178         struct mlx4_uar *uar;
 179         int err;
 180
 181         if (attr->flags)
 182                 return ERR_PTR(-EINVAL);
 183
 184         if (entries < 1 || entries > dev->dev->caps.max_cqes)
 185                 return ERR_PTR(-EINVAL);
 186
 187         cq = kmalloc(sizeof *cq, GFP_KERNEL);
 188         if (!cq)
 189                 return ERR_PTR(-ENOMEM);
 190
 191         entries      = roundup_pow_of_two(entries + 1);
 192         cq->ibcq.cqe = entries - 1;
 193         mutex_init(&cq->resize_mutex);
 194         spin_lock_init(&cq->lock);
 195         cq->resize_buf = NULL;
 196         cq->resize_umem = NULL;
 197         INIT_LIST_HEAD(&cq->send_qp_list);
 198         INIT_LIST_HEAD(&cq->recv_qp_list);
 199
 200         if (context) {
 201                 struct mlx4_ib_create_cq ucmd;
 202
 203                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 204                         err = -EFAULT;
 205                         goto err_cq;
 206                 }
 207
 208                 err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
 209                                           ucmd.buf_addr, entries);
 210                 if (err)
 211                         goto err_cq;
 212
 213                 err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
 214                                           &cq->db);
 215                 if (err)
 216                         goto err_mtt;
 217
 218                 uar = &to_mucontext(context)->uar;
 219         } else {
 220                 err = mlx4_db_alloc(dev->dev, &cq->db, 1, GFP_KERNEL);
 221                 if (err)
 222                         goto err_cq;
 223
 224                 cq->mcq.set_ci_db  = cq->db.db;
 225                 cq->mcq.arm_db     = cq->db.db + 1;
 226                 *cq->mcq.set_ci_db = 0;
 227                 *cq->mcq.arm_db    = 0;
 228
 229                 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
 230                 if (err)
 231                         goto err_db;
 232
 233                 uar = &dev->priv_uar;
 234         }
 235
 236         if (dev->eq_table)
 237                 vector = dev->eq_table[vector % ibdev->num_comp_vectors];
 238
 239         err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
 240                             cq->db.dma, &cq->mcq, vector, 0, 0);
 241         if (err)
 242                 goto err_dbmap;
 243
 244         if (context)
 245                 cq->mcq.tasklet_ctx.comp = mlx4_ib_cq_comp;
 246         else
 247                 cq->mcq.comp = mlx4_ib_cq_comp;
 248         cq->mcq.event = mlx4_ib_cq_event;
 249
 250         if (context)
 251                 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
 252                         err = -EFAULT;
 253                         goto err_dbmap;
 254                 }
 255
 256         return &cq->ibcq;
 257
 258 err_dbmap:
 259         if (context)
 260                 mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
 261
 262 err_mtt:
 263         mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
 264
 265         if (context)
 266                 ib_umem_release(cq->umem);
 267         else
 268                 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
 269
 270 err_db:
 271         if (!context)
 272                 mlx4_db_free(dev->dev, &cq->db);
 273
 274 err_cq:
 275         kfree(cq);
 276
 277         return ERR_PTR(err);
 278 }
 279
 280 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
 281                                   int entries)
 282 {
 283         int err;
 284
 285         if (cq->resize_buf)
 286                 return -EBUSY;
 287
 288         cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
 289         if (!cq->resize_buf)
 290                 return -ENOMEM;
 291
 292         err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
 293         if (err) {
 294                 kfree(cq->resize_buf);
 295                 cq->resize_buf = NULL;
 296                 return err;
 297         }
 298
 299         cq->resize_buf->cqe = entries - 1;
 300
 301         return 0;
 302 }
 303
 304 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
 305                                    int entries, struct ib_udata *udata)
 306 {
 307         struct mlx4_ib_resize_cq ucmd;
 308         int err;
 309
 310         if (cq->resize_umem)
 311                 return -EBUSY;
 312
 313         if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
 314                 return -EFAULT;
 315
 316         cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
 317         if (!cq->resize_buf)
 318                 return -ENOMEM;
 319
 320         err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
 321                                   &cq->resize_umem, ucmd.buf_addr, entries);
 322         if (err) {
 323                 kfree(cq->resize_buf);
 324                 cq->resize_buf = NULL;
 325                 return err;
 326         }
 327
 328         cq->resize_buf->cqe = entries - 1;
 329
 330         return 0;
 331 }
 332
 333 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
 334 {
 335         u32 i;
 336
 337         i = cq->mcq.cons_index;
 338         while (get_sw_cqe(cq, i))
 339                 ++i;
 340
 341         return i - cq->mcq.cons_index;
 342 }
 343
 344 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
 345 {
 346         struct mlx4_cqe *cqe, *new_cqe;
 347         int i;
 348         int cqe_size = cq->buf.entry_size;
 349         int cqe_inc = cqe_size == 64 ? 1 : 0;
 350
 351         i = cq->mcq.cons_index;
 352         cqe = get_cqe(cq, i & cq->ibcq.cqe);
 353         cqe += cqe_inc;
 354
 355         while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
 356                 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
 357                                            (i + 1) & cq->resize_buf->cqe);
 358                 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size);
 359                 new_cqe += cqe_inc;
 360
 361                 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
 362                         (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
 363                 cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
 364                 cqe += cqe_inc;
 365         }
 366         ++cq->mcq.cons_index;
 367 }
 368
 369 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
 370 {
 371         struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
 372         struct mlx4_ib_cq *cq = to_mcq(ibcq);
 373         struct mlx4_mtt mtt;
 374         int outst_cqe;
 375         int err;
 376
 377         mutex_lock(&cq->resize_mutex);
 378         if (entries < 1 || entries > dev->dev->caps.max_cqes) {
 379                 err = -EINVAL;
 380                 goto out;
 381         }
 382
 383         entries = roundup_pow_of_two(entries + 1);
 384         if (entries == ibcq->cqe + 1) {
 385                 err = 0;
 386                 goto out;
 387         }
 388
 389         if (entries > dev->dev->caps.max_cqes + 1) {
 390                 err = -EINVAL;
 391                 goto out;
 392         }
 393
 394         if (ibcq->uobject) {
 395                 err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
 396                 if (err)
 397                         goto out;
 398         } else {
 399                 /* Can't be smaller than the number of outstanding CQEs */
 400                 outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
 401                 if (entries < outst_cqe + 1) {
 402                         err = -EINVAL;
 403                         goto out;
 404                 }
 405
 406                 err = mlx4_alloc_resize_buf(dev, cq, entries);
 407                 if (err)
 408                         goto out;
 409         }
 410
 411         mtt = cq->buf.mtt;
 412
 413         err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
 414         if (err)
 415                 goto err_buf;
 416
 417         mlx4_mtt_cleanup(dev->dev, &mtt);
 418         if (ibcq->uobject) {
 419                 cq->buf      = cq->resize_buf->buf;
 420                 cq->ibcq.cqe = cq->resize_buf->cqe;
 421                 ib_umem_release(cq->umem);
 422                 cq->umem     = cq->resize_umem;
 423
 424                 kfree(cq->resize_buf);
 425                 cq->resize_buf = NULL;
 426                 cq->resize_umem = NULL;
 427         } else {
 428                 struct mlx4_ib_cq_buf tmp_buf;
 429                 int tmp_cqe = 0;
 430
 431                 spin_lock_irq(&cq->lock);
 432                 if (cq->resize_buf) {
 433                         mlx4_ib_cq_resize_copy_cqes(cq);
 434                         tmp_buf = cq->buf;
 435                         tmp_cqe = cq->ibcq.cqe;
 436                         cq->buf      = cq->resize_buf->buf;
 437                         cq->ibcq.cqe = cq->resize_buf->cqe;
 438
 439                         kfree(cq->resize_buf);
 440                         cq->resize_buf = NULL;
 441                 }
 442                 spin_unlock_irq(&cq->lock);
 443
 444                 if (tmp_cqe)
 445                         mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
 446         }
 447
 448         goto out;
 449
 450 err_buf:
 451         mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
 452         if (!ibcq->uobject)
 453                 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
 454                                     cq->resize_buf->cqe);
 455
 456         kfree(cq->resize_buf);
 457         cq->resize_buf = NULL;
 458
 459         if (cq->resize_umem) {
 460                 ib_umem_release(cq->resize_umem);
 461                 cq->resize_umem = NULL;
 462         }
 463
 464 out:
 465         mutex_unlock(&cq->resize_mutex);
 466
 467         return err;
 468 }
 469
 470 int mlx4_ib_destroy_cq(struct ib_cq *cq)
 471 {
 472         struct mlx4_ib_dev *dev = to_mdev(cq->device);
 473         struct mlx4_ib_cq *mcq = to_mcq(cq);
 474
 475         mlx4_cq_free(dev->dev, &mcq->mcq);
 476         mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
 477
 478         if (cq->uobject) {
 479                 mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
 480                 ib_umem_release(mcq->umem);
 481         } else {
 482                 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
 483                 mlx4_db_free(dev->dev, &mcq->db);
 484         }
 485
 486         kfree(mcq);
 487
 488         return 0;
 489 }
 490
 491 static void dump_cqe(void *cqe)
 492 {
 493         __be32 *buf = cqe;
 494
 495         pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
 496                be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
 497                be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
 498                be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
 499 }
 500
 501 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
 502                                      struct ib_wc *wc)
 503 {
 504         if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
 505                 pr_debug("local QP operation err "
 506                        "(QPN %06x, WQE index %x, vendor syndrome %02x, "
 507                        "opcode = %02x)\n",
 508                        be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
 509                        cqe->vendor_err_syndrome,
 510                        cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
 511                 dump_cqe(cqe);
 512         }
 513
 514         switch (cqe->syndrome) {
 515         case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
 516                 wc->status = IB_WC_LOC_LEN_ERR;
 517                 break;
 518         case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
 519                 wc->status = IB_WC_LOC_QP_OP_ERR;
 520                 break;
 521         case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
 522                 wc->status = IB_WC_LOC_PROT_ERR;
 523                 break;
 524         case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
 525                 wc->status = IB_WC_WR_FLUSH_ERR;
 526                 break;
 527         case MLX4_CQE_SYNDROME_MW_BIND_ERR:
 528                 wc->status = IB_WC_MW_BIND_ERR;
 529                 break;
 530         case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
 531                 wc->status = IB_WC_BAD_RESP_ERR;
 532                 break;
 533         case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
 534                 wc->status = IB_WC_LOC_ACCESS_ERR;
 535                 break;
 536         case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
 537                 wc->status = IB_WC_REM_INV_REQ_ERR;
 538                 break;
 539         case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
 540                 wc->status = IB_WC_REM_ACCESS_ERR;
 541                 break;
 542         case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
 543                 wc->status = IB_WC_REM_OP_ERR;
 544                 break;
 545         case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
 546                 wc->status = IB_WC_RETRY_EXC_ERR;
 547                 break;
 548         case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
 549                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
 550                 break;
 551         case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
 552                 wc->status = IB_WC_REM_ABORT_ERR;
 553                 break;
 554         default:
 555                 wc->status = IB_WC_GENERAL_ERR;
 556                 break;
 557         }
 558
 559         wc->vendor_err = cqe->vendor_err_syndrome;
 560 }
 561
 562 static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
 563 {
 564         return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4      |
 565                                       MLX4_CQE_STATUS_IPV4F     |
 566                                       MLX4_CQE_STATUS_IPV4OPT   |
 567                                       MLX4_CQE_STATUS_IPV6      |
 568                                       MLX4_CQE_STATUS_IPOK)) ==
 569                 cpu_to_be16(MLX4_CQE_STATUS_IPV4        |
 570                             MLX4_CQE_STATUS_IPOK))              &&
 571                 (status & cpu_to_be16(MLX4_CQE_STATUS_UDP       |
 572                                       MLX4_CQE_STATUS_TCP))     &&
 573                 checksum == cpu_to_be16(0xffff);
 574 }
 575
 576 static int use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc,
 577                            unsigned tail, struct mlx4_cqe *cqe, int is_eth)
 578 {
 579         struct mlx4_ib_proxy_sqp_hdr *hdr;
 580
 581         ib_dma_sync_single_for_cpu(qp->ibqp.device,
 582                                    qp->sqp_proxy_rcv[tail].map,
 583                                    sizeof (struct mlx4_ib_proxy_sqp_hdr),
 584                                    DMA_FROM_DEVICE);
 585         hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr);
 586         wc->pkey_index  = be16_to_cpu(hdr->tun.pkey_index);
 587         wc->src_qp      = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF;
 588         wc->wc_flags   |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0;
 589         wc->dlid_path_bits = 0;
 590
 591         if (is_eth) {
 592                 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid);
 593                 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4);
 594                 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2);
 595                 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
 596         } else {
 597                 wc->slid        = be16_to_cpu(hdr->tun.slid_mac_47_32);
 598                 wc->sl          = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12);
 599         }
 600
 601         return 0;
 602 }
 603
 604 static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries,
 605                                struct ib_wc *wc, int *npolled, int is_send)
 606 {
 607         struct mlx4_ib_wq *wq;
 608         unsigned cur;
 609         int i;
 610
 611         wq = is_send ? &qp->sq : &qp->rq;
 612         cur = wq->head - wq->tail;
 613
 614         if (cur == 0)
 615                 return;
 616
 617         for (i = 0;  i < cur && *npolled < num_entries; i++) {
 618                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 619                 wc->status = IB_WC_WR_FLUSH_ERR;
 620                 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR;
 621                 wq->tail++;
 622                 (*npolled)++;
 623                 wc->qp = &qp->ibqp;
 624                 wc++;
 625         }
 626 }
 627
 628 static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries,
 629                                  struct ib_wc *wc, int *npolled)
 630 {
 631         struct mlx4_ib_qp *qp;
 632
 633         *npolled = 0;
 634         /* Find uncompleted WQEs belonging to that cq and retrun
 635          * simulated FLUSH_ERR completions
 636          */
 637         list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) {
 638                 mlx4_ib_qp_sw_comp(qp, num_entries, wc, npolled, 1);
 639                 if (*npolled >= num_entries)
 640                         goto out;
 641         }
 642
 643         list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) {
 644                 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0);
 645                 if (*npolled >= num_entries)
 646                         goto out;
 647         }
 648
 649 out:
 650         return;
 651 }
 652
 653 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
 654                             struct mlx4_ib_qp **cur_qp,
 655                             struct ib_wc *wc)
 656 {
 657         struct mlx4_cqe *cqe;
 658         struct mlx4_qp *mqp;
 659         struct mlx4_ib_wq *wq;
 660         struct mlx4_ib_srq *srq;
 661         struct mlx4_srq *msrq = NULL;
 662         int is_send;
 663         int is_error;
 664         int is_eth;
 665         u32 g_mlpath_rqpn;
 666         u16 wqe_ctr;
 667         unsigned tail = 0;
 668
 669 repoll:
 670         cqe = next_cqe_sw(cq);
 671         if (!cqe)
 672                 return -EAGAIN;
 673
 674         if (cq->buf.entry_size == 64)
 675                 cqe++;
 676
 677         ++cq->mcq.cons_index;
 678
 679         /*
 680          * Make sure we read CQ entry contents after we've checked the
 681          * ownership bit.
 682          */
 683         rmb();
 684
 685         is_send  = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
 686         is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 687                 MLX4_CQE_OPCODE_ERROR;
 688
 689         if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
 690                      is_send)) {
 691                 pr_warn("Completion for NOP opcode detected!\n");
 692                 return -EINVAL;
 693         }
 694
 695         /* Resize CQ in progress */
 696         if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
 697                 if (cq->resize_buf) {
 698                         struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
 699
 700                         mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
 701                         cq->buf      = cq->resize_buf->buf;
 702                         cq->ibcq.cqe = cq->resize_buf->cqe;
 703
 704                         kfree(cq->resize_buf);
 705                         cq->resize_buf = NULL;
 706                 }
 707
 708                 goto repoll;
 709         }
 710
 711         if (!*cur_qp ||
 712             (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
 713                 /*
 714                  * We do not have to take the QP table lock here,
 715                  * because CQs will be locked while QPs are removed
 716                  * from the table.
 717                  */
 718                 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
 719                                        be32_to_cpu(cqe->vlan_my_qpn));
 720                 if (unlikely(!mqp)) {
 721                         pr_warn("CQ %06x with entry for unknown QPN %06x\n",
 722                                cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
 723                         return -EINVAL;
 724                 }
 725
 726                 *cur_qp = to_mibqp(mqp);
 727         }
 728
 729         wc->qp = &(*cur_qp)->ibqp;
 730
 731         if (wc->qp->qp_type == IB_QPT_XRC_TGT) {
 732                 u32 srq_num;
 733                 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
 734                 srq_num       = g_mlpath_rqpn & 0xffffff;
 735                 /* SRQ is also in the radix tree */
 736                 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev,
 737                                        srq_num);
 738                 if (unlikely(!msrq)) {
 739                         pr_warn("CQ %06x with entry for unknown SRQN %06x\n",
 740                                 cq->mcq.cqn, srq_num);
 741                         return -EINVAL;
 742                 }
 743         }
 744
 745         if (is_send) {
 746                 wq = &(*cur_qp)->sq;
 747                 if (!(*cur_qp)->sq_signal_bits) {
 748                         wqe_ctr = be16_to_cpu(cqe->wqe_index);
 749                         wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
 750                 }
 751                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 752                 ++wq->tail;
 753         } else if ((*cur_qp)->ibqp.srq) {
 754                 srq = to_msrq((*cur_qp)->ibqp.srq);
 755                 wqe_ctr = be16_to_cpu(cqe->wqe_index);
 756                 wc->wr_id = srq->wrid[wqe_ctr];
 757                 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
 758         } else if (msrq) {
 759                 srq = to_mibsrq(msrq);
 760                 wqe_ctr = be16_to_cpu(cqe->wqe_index);
 761                 wc->wr_id = srq->wrid[wqe_ctr];
 762                 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
 763         } else {
 764                 wq        = &(*cur_qp)->rq;
 765                 tail      = wq->tail & (wq->wqe_cnt - 1);
 766                 wc->wr_id = wq->wrid[tail];
 767                 ++wq->tail;
 768         }
 769
 770         if (unlikely(is_error)) {
 771                 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
 772                 return 0;
 773         }
 774
 775         wc->status = IB_WC_SUCCESS;
 776
 777         if (is_send) {
 778                 wc->wc_flags = 0;
 779                 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
 780                 case MLX4_OPCODE_RDMA_WRITE_IMM:
 781                         wc->wc_flags |= IB_WC_WITH_IMM;
 782                 case MLX4_OPCODE_RDMA_WRITE:
 783                         wc->opcode    = IB_WC_RDMA_WRITE;
 784                         break;
 785                 case MLX4_OPCODE_SEND_IMM:
 786                         wc->wc_flags |= IB_WC_WITH_IMM;
 787                 case MLX4_OPCODE_SEND:
 788                 case MLX4_OPCODE_SEND_INVAL:
 789                         wc->opcode    = IB_WC_SEND;
 790                         break;
 791                 case MLX4_OPCODE_RDMA_READ:
 792                         wc->opcode    = IB_WC_RDMA_READ;
 793                         wc->byte_len  = be32_to_cpu(cqe->byte_cnt);
 794                         break;
 795                 case MLX4_OPCODE_ATOMIC_CS:
 796                         wc->opcode    = IB_WC_COMP_SWAP;
 797                         wc->byte_len  = 8;
 798                         break;
 799                 case MLX4_OPCODE_ATOMIC_FA:
 800                         wc->opcode    = IB_WC_FETCH_ADD;
 801                         wc->byte_len  = 8;
 802                         break;
 803                 case MLX4_OPCODE_MASKED_ATOMIC_CS:
 804                         wc->opcode    = IB_WC_MASKED_COMP_SWAP;
 805                         wc->byte_len  = 8;
 806                         break;
 807                 case MLX4_OPCODE_MASKED_ATOMIC_FA:
 808                         wc->opcode    = IB_WC_MASKED_FETCH_ADD;
 809                         wc->byte_len  = 8;
 810                         break;
 811                 case MLX4_OPCODE_BIND_MW:
 812                         wc->opcode    = IB_WC_BIND_MW;
 813                         break;
 814                 case MLX4_OPCODE_LSO:
 815                         wc->opcode    = IB_WC_LSO;
 816                         break;
 817                 case MLX4_OPCODE_FMR:
 818                         wc->opcode    = IB_WC_FAST_REG_MR;
 819                         break;
 820                 case MLX4_OPCODE_LOCAL_INVAL:
 821                         wc->opcode    = IB_WC_LOCAL_INV;
 822                         break;
 823                 }
 824         } else {
 825                 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
 826
 827                 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
 828                 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
 829                         wc->opcode      = IB_WC_RECV_RDMA_WITH_IMM;
 830                         wc->wc_flags    = IB_WC_WITH_IMM;
 831                         wc->ex.imm_data = cqe->immed_rss_invalid;
 832                         break;
 833                 case MLX4_RECV_OPCODE_SEND_INVAL:
 834                         wc->opcode      = IB_WC_RECV;
 835                         wc->wc_flags    = IB_WC_WITH_INVALIDATE;
 836                         wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
 837                         break;
 838                 case MLX4_RECV_OPCODE_SEND:
 839                         wc->opcode   = IB_WC_RECV;
 840                         wc->wc_flags = 0;
 841                         break;
 842                 case MLX4_RECV_OPCODE_SEND_IMM:
 843                         wc->opcode      = IB_WC_RECV;
 844                         wc->wc_flags    = IB_WC_WITH_IMM;
 845                         wc->ex.imm_data = cqe->immed_rss_invalid;
 846                         break;
 847                 }
 848
 849                 is_eth = (rdma_port_get_link_layer(wc->qp->device,
 850                                                   (*cur_qp)->port) ==
 851                           IB_LINK_LAYER_ETHERNET);
 852                 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) {
 853                         if ((*cur_qp)->mlx4_ib_qp_type &
 854                             (MLX4_IB_QPT_PROXY_SMI_OWNER |
 855                              MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
 856                                 return use_tunnel_data(*cur_qp, cq, wc, tail,
 857                                                        cqe, is_eth);
 858                 }
 859
 860                 wc->slid           = be16_to_cpu(cqe->rlid);
 861                 g_mlpath_rqpn      = be32_to_cpu(cqe->g_mlpath_rqpn);
 862                 wc->src_qp         = g_mlpath_rqpn & 0xffffff;
 863                 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
 864                 wc->wc_flags      |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
 865                 wc->pkey_index     = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
 866                 wc->wc_flags      |= mlx4_ib_ipoib_csum_ok(cqe->status,
 867                                         cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
 868                 if (is_eth) {
 869                         wc->sl  = be16_to_cpu(cqe->sl_vid) >> 13;
 870                         if (be32_to_cpu(cqe->vlan_my_qpn) &
 871                                         MLX4_CQE_VLAN_PRESENT_MASK) {
 872                                 wc->vlan_id = be16_to_cpu(cqe->sl_vid) &
 873                                         MLX4_CQE_VID_MASK;
 874                         } else {
 875                                 wc->vlan_id = 0xffff;
 876                         }
 877                         memcpy(wc->smac, cqe->smac, ETH_ALEN);
 878                         wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
 879                 } else {
 880                         wc->sl  = be16_to_cpu(cqe->sl_vid) >> 12;
 881                         wc->vlan_id = 0xffff;
 882                 }
 883         }
 884
 885         return 0;
 886 }
 887
 888 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
 889 {
 890         struct mlx4_ib_cq *cq = to_mcq(ibcq);
 891         struct mlx4_ib_qp *cur_qp = NULL;
 892         unsigned long flags;
 893         int npolled;
 894         int err = 0;
 895         struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device);
 896
 897         spin_lock_irqsave(&cq->lock, flags);
 898         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 899                 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
 900                 goto out;
 901         }
 902
 903         for (npolled = 0; npolled < num_entries; ++npolled) {
 904                 err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
 905                 if (err)
 906                         break;
 907         }
 908
 909         mlx4_cq_set_ci(&cq->mcq);
 910
 911 out:
 912         spin_unlock_irqrestore(&cq->lock, flags);
 913
 914         if (err == 0 || err == -EAGAIN)
 915                 return npolled;
 916         else
 917                 return err;
 918 }
 919
 920 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
 921 {
 922         mlx4_cq_arm(&to_mcq(ibcq)->mcq,
 923                     (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
 924                     MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
 925                     to_mdev(ibcq->device)->uar_map,
 926                     MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
 927
 928         return 0;
 929 }
 930
 931 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
 932 {
 933         u32 prod_index;
 934         int nfreed = 0;
 935         struct mlx4_cqe *cqe, *dest;
 936         u8 owner_bit;
 937         int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0;
 938
 939         /*
 940          * First we need to find the current producer index, so we
 941          * know where to start cleaning from.  It doesn't matter if HW
 942          * adds new entries after this loop -- the QP we're worried
 943          * about is already in RESET, so the new entries won't come
 944          * from our QP and therefore don't need to be checked.
 945          */
 946         for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
 947                 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
 948                         break;
 949
 950         /*
 951          * Now sweep backwards through the CQ, removing CQ entries
 952          * that match our QP by copying older entries on top of them.
 953          */
 954         while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
 955                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
 956                 cqe += cqe_inc;
 957
 958                 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
 959                         if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
 960                                 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
 961                         ++nfreed;
 962                 } else if (nfreed) {
 963                         dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
 964                         dest += cqe_inc;
 965
 966                         owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
 967                         memcpy(dest, cqe, sizeof *cqe);
 968                         dest->owner_sr_opcode = owner_bit |
 969                                 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
 970                 }
 971         }
 972
 973         if (nfreed) {
 974                 cq->mcq.cons_index += nfreed;
 975                 /*
 976                  * Make sure update of buffer contents is done before
 977                  * updating consumer index.
 978                  */
 979                 wmb();
 980                 mlx4_cq_set_ci(&cq->mcq);
 981         }
 982 }
 983
 984 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
 985 {
 986         spin_lock_irq(&cq->lock);
 987         __mlx4_ib_cq_clean(cq, qpn, srq);
 988         spin_unlock_irq(&cq->lock);
 989 }