2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/mlx4/cq.h>
35 #include <linux/mlx4/qp.h>
36 #include <linux/mlx4/srq.h>
37 #include <linux/slab.h>
42 static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
44 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
45 ibcq->comp_handler(ibcq, ibcq->cq_context);
48 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
50 struct ib_event event;
53 if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
54 pr_warn("Unexpected event type %d "
55 "on CQ %06x\n", type, cq->cqn);
59 ibcq = &to_mibcq(cq)->ibcq;
60 if (ibcq->event_handler) {
61 event.device = ibcq->device;
62 event.event = IB_EVENT_CQ_ERR;
63 event.element.cq = ibcq;
64 ibcq->event_handler(&event, ibcq->cq_context);
68 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
70 return mlx4_buf_offset(&buf->buf, n * buf->entry_size);
73 static void *get_cqe(struct mlx4_ib_cq *cq, int n)
75 return get_cqe_from_buf(&cq->buf, n);
78 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
80 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
81 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe);
83 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
84 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
87 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
89 return get_sw_cqe(cq, cq->mcq.cons_index);
92 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
94 struct mlx4_ib_cq *mcq = to_mcq(cq);
95 struct mlx4_ib_dev *dev = to_mdev(cq->device);
97 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
100 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
104 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size,
105 PAGE_SIZE * 2, &buf->buf, GFP_KERNEL);
110 buf->entry_size = dev->dev->caps.cqe_size;
111 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
116 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf, GFP_KERNEL);
123 mlx4_mtt_cleanup(dev->dev, &buf->mtt);
126 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf);
132 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
134 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf);
137 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
138 struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
139 u64 buf_addr, int cqe)
142 int cqe_size = dev->dev->caps.cqe_size;
144 *umem = ib_umem_get(context, buf_addr, cqe * cqe_size,
145 IB_ACCESS_LOCAL_WRITE, 1);
147 return PTR_ERR(*umem);
149 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
150 ilog2((*umem)->page_size), &buf->mtt);
154 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
161 mlx4_mtt_cleanup(dev->dev, &buf->mtt);
164 ib_umem_release(*umem);
169 #define CQ_CREATE_FLAGS_SUPPORTED IB_CQ_FLAGS_TIMESTAMP_COMPLETION
170 struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev,
171 const struct ib_cq_init_attr *attr,
172 struct ib_ucontext *context,
173 struct ib_udata *udata)
175 int entries = attr->cqe;
176 int vector = attr->comp_vector;
177 struct mlx4_ib_dev *dev = to_mdev(ibdev);
178 struct mlx4_ib_cq *cq;
179 struct mlx4_uar *uar;
182 if (entries < 1 || entries > dev->dev->caps.max_cqes)
183 return ERR_PTR(-EINVAL);
185 if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED)
186 return ERR_PTR(-EINVAL);
188 cq = kmalloc(sizeof *cq, GFP_KERNEL);
190 return ERR_PTR(-ENOMEM);
192 entries = roundup_pow_of_two(entries + 1);
193 cq->ibcq.cqe = entries - 1;
194 mutex_init(&cq->resize_mutex);
195 spin_lock_init(&cq->lock);
196 cq->resize_buf = NULL;
197 cq->resize_umem = NULL;
198 cq->create_flags = attr->flags;
199 INIT_LIST_HEAD(&cq->send_qp_list);
200 INIT_LIST_HEAD(&cq->recv_qp_list);
203 struct mlx4_ib_create_cq ucmd;
205 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
210 err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
211 ucmd.buf_addr, entries);
215 err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
220 uar = &to_mucontext(context)->uar;
222 err = mlx4_db_alloc(dev->dev, &cq->db, 1, GFP_KERNEL);
226 cq->mcq.set_ci_db = cq->db.db;
227 cq->mcq.arm_db = cq->db.db + 1;
228 *cq->mcq.set_ci_db = 0;
231 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
235 uar = &dev->priv_uar;
239 vector = dev->eq_table[vector % ibdev->num_comp_vectors];
241 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
242 cq->db.dma, &cq->mcq, vector, 0,
243 !!(cq->create_flags & IB_CQ_FLAGS_TIMESTAMP_COMPLETION));
248 cq->mcq.tasklet_ctx.comp = mlx4_ib_cq_comp;
250 cq->mcq.comp = mlx4_ib_cq_comp;
251 cq->mcq.event = mlx4_ib_cq_event;
254 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
262 mlx4_cq_free(dev->dev, &cq->mcq);
266 mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
269 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
272 ib_umem_release(cq->umem);
274 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
278 mlx4_db_free(dev->dev, &cq->db);
286 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
294 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
298 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
300 kfree(cq->resize_buf);
301 cq->resize_buf = NULL;
305 cq->resize_buf->cqe = entries - 1;
310 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
311 int entries, struct ib_udata *udata)
313 struct mlx4_ib_resize_cq ucmd;
319 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
322 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
326 err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
327 &cq->resize_umem, ucmd.buf_addr, entries);
329 kfree(cq->resize_buf);
330 cq->resize_buf = NULL;
334 cq->resize_buf->cqe = entries - 1;
339 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
343 i = cq->mcq.cons_index;
344 while (get_sw_cqe(cq, i))
347 return i - cq->mcq.cons_index;
350 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
352 struct mlx4_cqe *cqe, *new_cqe;
354 int cqe_size = cq->buf.entry_size;
355 int cqe_inc = cqe_size == 64 ? 1 : 0;
357 i = cq->mcq.cons_index;
358 cqe = get_cqe(cq, i & cq->ibcq.cqe);
361 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
362 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
363 (i + 1) & cq->resize_buf->cqe);
364 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size);
367 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
368 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
369 cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
372 ++cq->mcq.cons_index;
375 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
377 struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
378 struct mlx4_ib_cq *cq = to_mcq(ibcq);
383 mutex_lock(&cq->resize_mutex);
384 if (entries < 1 || entries > dev->dev->caps.max_cqes) {
389 entries = roundup_pow_of_two(entries + 1);
390 if (entries == ibcq->cqe + 1) {
395 if (entries > dev->dev->caps.max_cqes + 1) {
401 err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
405 /* Can't be smaller than the number of outstanding CQEs */
406 outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
407 if (entries < outst_cqe + 1) {
412 err = mlx4_alloc_resize_buf(dev, cq, entries);
419 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
423 mlx4_mtt_cleanup(dev->dev, &mtt);
425 cq->buf = cq->resize_buf->buf;
426 cq->ibcq.cqe = cq->resize_buf->cqe;
427 ib_umem_release(cq->umem);
428 cq->umem = cq->resize_umem;
430 kfree(cq->resize_buf);
431 cq->resize_buf = NULL;
432 cq->resize_umem = NULL;
434 struct mlx4_ib_cq_buf tmp_buf;
437 spin_lock_irq(&cq->lock);
438 if (cq->resize_buf) {
439 mlx4_ib_cq_resize_copy_cqes(cq);
441 tmp_cqe = cq->ibcq.cqe;
442 cq->buf = cq->resize_buf->buf;
443 cq->ibcq.cqe = cq->resize_buf->cqe;
445 kfree(cq->resize_buf);
446 cq->resize_buf = NULL;
448 spin_unlock_irq(&cq->lock);
451 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
457 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
459 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
460 cq->resize_buf->cqe);
462 kfree(cq->resize_buf);
463 cq->resize_buf = NULL;
465 if (cq->resize_umem) {
466 ib_umem_release(cq->resize_umem);
467 cq->resize_umem = NULL;
471 mutex_unlock(&cq->resize_mutex);
476 int mlx4_ib_destroy_cq(struct ib_cq *cq)
478 struct mlx4_ib_dev *dev = to_mdev(cq->device);
479 struct mlx4_ib_cq *mcq = to_mcq(cq);
481 mlx4_cq_free(dev->dev, &mcq->mcq);
482 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
485 mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
486 ib_umem_release(mcq->umem);
488 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
489 mlx4_db_free(dev->dev, &mcq->db);
497 static void dump_cqe(void *cqe)
501 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
502 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
503 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
504 be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
507 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
510 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
511 pr_debug("local QP operation err "
512 "(QPN %06x, WQE index %x, vendor syndrome %02x, "
514 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
515 cqe->vendor_err_syndrome,
516 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
520 switch (cqe->syndrome) {
521 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
522 wc->status = IB_WC_LOC_LEN_ERR;
524 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
525 wc->status = IB_WC_LOC_QP_OP_ERR;
527 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
528 wc->status = IB_WC_LOC_PROT_ERR;
530 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
531 wc->status = IB_WC_WR_FLUSH_ERR;
533 case MLX4_CQE_SYNDROME_MW_BIND_ERR:
534 wc->status = IB_WC_MW_BIND_ERR;
536 case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
537 wc->status = IB_WC_BAD_RESP_ERR;
539 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
540 wc->status = IB_WC_LOC_ACCESS_ERR;
542 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
543 wc->status = IB_WC_REM_INV_REQ_ERR;
545 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
546 wc->status = IB_WC_REM_ACCESS_ERR;
548 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
549 wc->status = IB_WC_REM_OP_ERR;
551 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
552 wc->status = IB_WC_RETRY_EXC_ERR;
554 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
555 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
557 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
558 wc->status = IB_WC_REM_ABORT_ERR;
561 wc->status = IB_WC_GENERAL_ERR;
565 wc->vendor_err = cqe->vendor_err_syndrome;
568 static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
570 return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
571 MLX4_CQE_STATUS_IPV4F |
572 MLX4_CQE_STATUS_IPV4OPT |
573 MLX4_CQE_STATUS_IPV6 |
574 MLX4_CQE_STATUS_IPOK)) ==
575 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
576 MLX4_CQE_STATUS_IPOK)) &&
577 (status & cpu_to_be16(MLX4_CQE_STATUS_UDP |
578 MLX4_CQE_STATUS_TCP)) &&
579 checksum == cpu_to_be16(0xffff);
582 static int use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc,
583 unsigned tail, struct mlx4_cqe *cqe, int is_eth)
585 struct mlx4_ib_proxy_sqp_hdr *hdr;
587 ib_dma_sync_single_for_cpu(qp->ibqp.device,
588 qp->sqp_proxy_rcv[tail].map,
589 sizeof (struct mlx4_ib_proxy_sqp_hdr),
591 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr);
592 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index);
593 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF;
594 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0;
595 wc->dlid_path_bits = 0;
598 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid);
599 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4);
600 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2);
601 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
603 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32);
604 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12);
610 static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries,
611 struct ib_wc *wc, int *npolled, int is_send)
613 struct mlx4_ib_wq *wq;
617 wq = is_send ? &qp->sq : &qp->rq;
618 cur = wq->head - wq->tail;
623 for (i = 0; i < cur && *npolled < num_entries; i++) {
624 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
625 wc->status = IB_WC_WR_FLUSH_ERR;
626 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR;
634 static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries,
635 struct ib_wc *wc, int *npolled)
637 struct mlx4_ib_qp *qp;
640 /* Find uncompleted WQEs belonging to that cq and retrun
641 * simulated FLUSH_ERR completions
643 list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) {
644 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1);
645 if (*npolled >= num_entries)
649 list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) {
650 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0);
651 if (*npolled >= num_entries)
659 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
660 struct mlx4_ib_qp **cur_qp,
663 struct mlx4_cqe *cqe;
665 struct mlx4_ib_wq *wq;
666 struct mlx4_ib_srq *srq;
667 struct mlx4_srq *msrq = NULL;
676 cqe = next_cqe_sw(cq);
680 if (cq->buf.entry_size == 64)
683 ++cq->mcq.cons_index;
686 * Make sure we read CQ entry contents after we've checked the
691 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
692 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
693 MLX4_CQE_OPCODE_ERROR;
695 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
697 pr_warn("Completion for NOP opcode detected!\n");
701 /* Resize CQ in progress */
702 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
703 if (cq->resize_buf) {
704 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
706 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
707 cq->buf = cq->resize_buf->buf;
708 cq->ibcq.cqe = cq->resize_buf->cqe;
710 kfree(cq->resize_buf);
711 cq->resize_buf = NULL;
718 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
720 * We do not have to take the QP table lock here,
721 * because CQs will be locked while QPs are removed
724 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
725 be32_to_cpu(cqe->vlan_my_qpn));
726 if (unlikely(!mqp)) {
727 pr_warn("CQ %06x with entry for unknown QPN %06x\n",
728 cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
732 *cur_qp = to_mibqp(mqp);
735 wc->qp = &(*cur_qp)->ibqp;
737 if (wc->qp->qp_type == IB_QPT_XRC_TGT) {
739 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
740 srq_num = g_mlpath_rqpn & 0xffffff;
741 /* SRQ is also in the radix tree */
742 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev,
744 if (unlikely(!msrq)) {
745 pr_warn("CQ %06x with entry for unknown SRQN %06x\n",
746 cq->mcq.cqn, srq_num);
753 if (!(*cur_qp)->sq_signal_bits) {
754 wqe_ctr = be16_to_cpu(cqe->wqe_index);
755 wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
757 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
759 } else if ((*cur_qp)->ibqp.srq) {
760 srq = to_msrq((*cur_qp)->ibqp.srq);
761 wqe_ctr = be16_to_cpu(cqe->wqe_index);
762 wc->wr_id = srq->wrid[wqe_ctr];
763 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
765 srq = to_mibsrq(msrq);
766 wqe_ctr = be16_to_cpu(cqe->wqe_index);
767 wc->wr_id = srq->wrid[wqe_ctr];
768 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
771 tail = wq->tail & (wq->wqe_cnt - 1);
772 wc->wr_id = wq->wrid[tail];
776 if (unlikely(is_error)) {
777 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
781 wc->status = IB_WC_SUCCESS;
785 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
786 case MLX4_OPCODE_RDMA_WRITE_IMM:
787 wc->wc_flags |= IB_WC_WITH_IMM;
788 case MLX4_OPCODE_RDMA_WRITE:
789 wc->opcode = IB_WC_RDMA_WRITE;
791 case MLX4_OPCODE_SEND_IMM:
792 wc->wc_flags |= IB_WC_WITH_IMM;
793 case MLX4_OPCODE_SEND:
794 case MLX4_OPCODE_SEND_INVAL:
795 wc->opcode = IB_WC_SEND;
797 case MLX4_OPCODE_RDMA_READ:
798 wc->opcode = IB_WC_RDMA_READ;
799 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
801 case MLX4_OPCODE_ATOMIC_CS:
802 wc->opcode = IB_WC_COMP_SWAP;
805 case MLX4_OPCODE_ATOMIC_FA:
806 wc->opcode = IB_WC_FETCH_ADD;
809 case MLX4_OPCODE_MASKED_ATOMIC_CS:
810 wc->opcode = IB_WC_MASKED_COMP_SWAP;
813 case MLX4_OPCODE_MASKED_ATOMIC_FA:
814 wc->opcode = IB_WC_MASKED_FETCH_ADD;
817 case MLX4_OPCODE_BIND_MW:
818 wc->opcode = IB_WC_BIND_MW;
820 case MLX4_OPCODE_LSO:
821 wc->opcode = IB_WC_LSO;
823 case MLX4_OPCODE_FMR:
824 wc->opcode = IB_WC_REG_MR;
826 case MLX4_OPCODE_LOCAL_INVAL:
827 wc->opcode = IB_WC_LOCAL_INV;
831 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
833 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
834 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
835 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
836 wc->wc_flags = IB_WC_WITH_IMM;
837 wc->ex.imm_data = cqe->immed_rss_invalid;
839 case MLX4_RECV_OPCODE_SEND_INVAL:
840 wc->opcode = IB_WC_RECV;
841 wc->wc_flags = IB_WC_WITH_INVALIDATE;
842 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
844 case MLX4_RECV_OPCODE_SEND:
845 wc->opcode = IB_WC_RECV;
848 case MLX4_RECV_OPCODE_SEND_IMM:
849 wc->opcode = IB_WC_RECV;
850 wc->wc_flags = IB_WC_WITH_IMM;
851 wc->ex.imm_data = cqe->immed_rss_invalid;
855 is_eth = (rdma_port_get_link_layer(wc->qp->device,
857 IB_LINK_LAYER_ETHERNET);
858 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) {
859 if ((*cur_qp)->mlx4_ib_qp_type &
860 (MLX4_IB_QPT_PROXY_SMI_OWNER |
861 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
862 return use_tunnel_data(*cur_qp, cq, wc, tail,
866 wc->slid = be16_to_cpu(cqe->rlid);
867 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
868 wc->src_qp = g_mlpath_rqpn & 0xffffff;
869 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
870 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
871 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
872 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status,
873 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
875 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13;
876 if (be32_to_cpu(cqe->vlan_my_qpn) &
877 MLX4_CQE_CVLAN_PRESENT_MASK) {
878 wc->vlan_id = be16_to_cpu(cqe->sl_vid) &
881 wc->vlan_id = 0xffff;
883 memcpy(wc->smac, cqe->smac, ETH_ALEN);
884 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
886 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
887 wc->vlan_id = 0xffff;
894 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
896 struct mlx4_ib_cq *cq = to_mcq(ibcq);
897 struct mlx4_ib_qp *cur_qp = NULL;
901 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device);
903 spin_lock_irqsave(&cq->lock, flags);
904 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
905 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
909 for (npolled = 0; npolled < num_entries; ++npolled) {
910 err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
915 mlx4_cq_set_ci(&cq->mcq);
918 spin_unlock_irqrestore(&cq->lock, flags);
920 if (err == 0 || err == -EAGAIN)
926 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
928 mlx4_cq_arm(&to_mcq(ibcq)->mcq,
929 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
930 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
931 to_mdev(ibcq->device)->uar_map,
932 MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
937 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
941 struct mlx4_cqe *cqe, *dest;
943 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0;
946 * First we need to find the current producer index, so we
947 * know where to start cleaning from. It doesn't matter if HW
948 * adds new entries after this loop -- the QP we're worried
949 * about is already in RESET, so the new entries won't come
950 * from our QP and therefore don't need to be checked.
952 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
953 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
957 * Now sweep backwards through the CQ, removing CQ entries
958 * that match our QP by copying older entries on top of them.
960 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
961 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
964 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
965 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
966 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
969 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
972 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
973 memcpy(dest, cqe, sizeof *cqe);
974 dest->owner_sr_opcode = owner_bit |
975 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
980 cq->mcq.cons_index += nfreed;
982 * Make sure update of buffer contents is done before
983 * updating consumer index.
986 mlx4_cq_set_ci(&cq->mcq);
990 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
992 spin_lock_irq(&cq->lock);
993 __mlx4_ib_cq_clean(cq, qpn, srq);
994 spin_unlock_irq(&cq->lock);