drivers/infiniband/hw/ocrdma/ocrdma_hw.c

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) CNA Adapters.              *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #include <linux/sched.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/log2.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_user_verbs.h>
  35
  36 #include "ocrdma.h"
  37 #include "ocrdma_hw.h"
  38 #include "ocrdma_verbs.h"
  39 #include "ocrdma_ah.h"
  40
  41 enum mbx_status {
  42         OCRDMA_MBX_STATUS_FAILED                = 1,
  43         OCRDMA_MBX_STATUS_ILLEGAL_FIELD         = 3,
  44         OCRDMA_MBX_STATUS_OOR                   = 100,
  45         OCRDMA_MBX_STATUS_INVALID_PD            = 101,
  46         OCRDMA_MBX_STATUS_PD_INUSE              = 102,
  47         OCRDMA_MBX_STATUS_INVALID_CQ            = 103,
  48         OCRDMA_MBX_STATUS_INVALID_QP            = 104,
  49         OCRDMA_MBX_STATUS_INVALID_LKEY          = 105,
  50         OCRDMA_MBX_STATUS_ORD_EXCEEDS           = 106,
  51         OCRDMA_MBX_STATUS_IRD_EXCEEDS           = 107,
  52         OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS     = 108,
  53         OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS     = 109,
  54         OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS      = 110,
  55         OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS     = 111,
  56         OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS      = 112,
  57         OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE  = 113,
  58         OCRDMA_MBX_STATUS_MW_BOUND              = 114,
  59         OCRDMA_MBX_STATUS_INVALID_VA            = 115,
  60         OCRDMA_MBX_STATUS_INVALID_LENGTH        = 116,
  61         OCRDMA_MBX_STATUS_INVALID_FBO           = 117,
  62         OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS    = 118,
  63         OCRDMA_MBX_STATUS_INVALID_PBE_SIZE      = 119,
  64         OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY     = 120,
  65         OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT     = 121,
  66         OCRDMA_MBX_STATUS_INVALID_SRQ_ID        = 129,
  67         OCRDMA_MBX_STATUS_SRQ_ERROR             = 133,
  68         OCRDMA_MBX_STATUS_RQE_EXCEEDS           = 134,
  69         OCRDMA_MBX_STATUS_MTU_EXCEEDS           = 135,
  70         OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS        = 136,
  71         OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS     = 137,
  72         OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS     = 138,
  73         OCRDMA_MBX_STATUS_QP_BOUND              = 130,
  74         OCRDMA_MBX_STATUS_INVALID_CHANGE        = 139,
  75         OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP      = 140,
  76         OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
  77         OCRDMA_MBX_STATUS_MW_STILL_BOUND        = 142,
  78         OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID    = 143,
  79         OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS    = 144
  80 };
  81
  82 enum additional_status {
  83         OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
  84 };
  85
  86 enum cqe_status {
  87         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES  = 1,
  88         OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER         = 2,
  89         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES    = 3,
  90         OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING            = 4,
  91         OCRDMA_MBX_CQE_STATUS_DMA_FAILED                = 5
  92 };
  93
  94 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
  95 {
  96         return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
  97 }
  98
  99 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
 100 {
 101         eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
 102 }
 103
 104 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
 105 {
 106         struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
 107             (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
 108
 109         if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
 110                 return NULL;
 111         return cqe;
 112 }
 113
 114 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
 115 {
 116         dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
 117 }
 118
 119 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
 120 {
 121         return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
 122 }
 123
 124 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
 125 {
 126         dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
 127 }
 128
 129 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
 130 {
 131         return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
 132 }
 133
 134 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
 135 {
 136         switch (qps) {
 137         case OCRDMA_QPS_RST:
 138                 return IB_QPS_RESET;
 139         case OCRDMA_QPS_INIT:
 140                 return IB_QPS_INIT;
 141         case OCRDMA_QPS_RTR:
 142                 return IB_QPS_RTR;
 143         case OCRDMA_QPS_RTS:
 144                 return IB_QPS_RTS;
 145         case OCRDMA_QPS_SQD:
 146         case OCRDMA_QPS_SQ_DRAINING:
 147                 return IB_QPS_SQD;
 148         case OCRDMA_QPS_SQE:
 149                 return IB_QPS_SQE;
 150         case OCRDMA_QPS_ERR:
 151                 return IB_QPS_ERR;
 152         }
 153         return IB_QPS_ERR;
 154 }
 155
 156 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
 157 {
 158         switch (qps) {
 159         case IB_QPS_RESET:
 160                 return OCRDMA_QPS_RST;
 161         case IB_QPS_INIT:
 162                 return OCRDMA_QPS_INIT;
 163         case IB_QPS_RTR:
 164                 return OCRDMA_QPS_RTR;
 165         case IB_QPS_RTS:
 166                 return OCRDMA_QPS_RTS;
 167         case IB_QPS_SQD:
 168                 return OCRDMA_QPS_SQD;
 169         case IB_QPS_SQE:
 170                 return OCRDMA_QPS_SQE;
 171         case IB_QPS_ERR:
 172                 return OCRDMA_QPS_ERR;
 173         }
 174         return OCRDMA_QPS_ERR;
 175 }
 176
 177 static int ocrdma_get_mbx_errno(u32 status)
 178 {
 179         int err_num;
 180         u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
 181                                         OCRDMA_MBX_RSP_STATUS_SHIFT;
 182         u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
 183                                         OCRDMA_MBX_RSP_ASTATUS_SHIFT;
 184
 185         switch (mbox_status) {
 186         case OCRDMA_MBX_STATUS_OOR:
 187         case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
 188                 err_num = -EAGAIN;
 189                 break;
 190
 191         case OCRDMA_MBX_STATUS_INVALID_PD:
 192         case OCRDMA_MBX_STATUS_INVALID_CQ:
 193         case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
 194         case OCRDMA_MBX_STATUS_INVALID_QP:
 195         case OCRDMA_MBX_STATUS_INVALID_CHANGE:
 196         case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
 197         case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
 198         case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
 199         case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
 200         case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
 201         case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
 202         case OCRDMA_MBX_STATUS_INVALID_LKEY:
 203         case OCRDMA_MBX_STATUS_INVALID_VA:
 204         case OCRDMA_MBX_STATUS_INVALID_LENGTH:
 205         case OCRDMA_MBX_STATUS_INVALID_FBO:
 206         case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
 207         case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
 208         case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
 209         case OCRDMA_MBX_STATUS_SRQ_ERROR:
 210         case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
 211                 err_num = -EINVAL;
 212                 break;
 213
 214         case OCRDMA_MBX_STATUS_PD_INUSE:
 215         case OCRDMA_MBX_STATUS_QP_BOUND:
 216         case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
 217         case OCRDMA_MBX_STATUS_MW_BOUND:
 218                 err_num = -EBUSY;
 219                 break;
 220
 221         case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
 222         case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
 223         case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
 224         case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
 225         case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
 226         case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
 227         case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
 228         case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
 229         case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
 230                 err_num = -ENOBUFS;
 231                 break;
 232
 233         case OCRDMA_MBX_STATUS_FAILED:
 234                 switch (add_status) {
 235                 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
 236                         err_num = -EAGAIN;
 237                         break;
 238                 }
 239         default:
 240                 err_num = -EFAULT;
 241         }
 242         return err_num;
 243 }
 244
 245 char *port_speed_string(struct ocrdma_dev *dev)
 246 {
 247         char *str = "";
 248         u16 speeds_supported;
 249
 250         speeds_supported = dev->phy.fixed_speeds_supported |
 251                                 dev->phy.auto_speeds_supported;
 252         if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
 253                 str = "40Gbps ";
 254         else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
 255                 str = "10Gbps ";
 256         else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
 257                 str = "1Gbps ";
 258
 259         return str;
 260 }
 261
 262 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
 263 {
 264         int err_num = -EINVAL;
 265
 266         switch (cqe_status) {
 267         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
 268                 err_num = -EPERM;
 269                 break;
 270         case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
 271                 err_num = -EINVAL;
 272                 break;
 273         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
 274         case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
 275                 err_num = -EINVAL;
 276                 break;
 277         case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
 278         default:
 279                 err_num = -EINVAL;
 280                 break;
 281         }
 282         return err_num;
 283 }
 284
 285 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
 286                        bool solicited, u16 cqe_popped)
 287 {
 288         u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
 289
 290         val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
 291              OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
 292
 293         if (armed)
 294                 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
 295         if (solicited)
 296                 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
 297         val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
 298         iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
 299 }
 300
 301 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
 302 {
 303         u32 val = 0;
 304
 305         val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
 306         val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
 307         iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
 308 }
 309
 310 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
 311                               bool arm, bool clear_int, u16 num_eqe)
 312 {
 313         u32 val = 0;
 314
 315         val |= eq_id & OCRDMA_EQ_ID_MASK;
 316         val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
 317         if (arm)
 318                 val |= (1 << OCRDMA_REARM_SHIFT);
 319         if (clear_int)
 320                 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
 321         val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
 322         val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
 323         iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
 324 }
 325
 326 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
 327                             u8 opcode, u8 subsys, u32 cmd_len)
 328 {
 329         cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
 330         cmd_hdr->timeout = 20; /* seconds */
 331         cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
 332 }
 333
 334 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
 335 {
 336         struct ocrdma_mqe *mqe;
 337
 338         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
 339         if (!mqe)
 340                 return NULL;
 341         mqe->hdr.spcl_sge_cnt_emb |=
 342                 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
 343                                         OCRDMA_MQE_HDR_EMB_MASK;
 344         mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
 345
 346         ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
 347                         mqe->hdr.pyld_len);
 348         return mqe;
 349 }
 350
 351 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
 352 {
 353         dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
 354 }
 355
 356 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
 357                           struct ocrdma_queue_info *q, u16 len, u16 entry_size)
 358 {
 359         memset(q, 0, sizeof(*q));
 360         q->len = len;
 361         q->entry_size = entry_size;
 362         q->size = len * entry_size;
 363         q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
 364                                    &q->dma, GFP_KERNEL);
 365         if (!q->va)
 366                 return -ENOMEM;
 367         memset(q->va, 0, q->size);
 368         return 0;
 369 }
 370
 371 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
 372                                         dma_addr_t host_pa, int hw_page_size)
 373 {
 374         int i;
 375
 376         for (i = 0; i < cnt; i++) {
 377                 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
 378                 q_pa[i].hi = (u32) upper_32_bits(host_pa);
 379                 host_pa += hw_page_size;
 380         }
 381 }
 382
 383 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
 384                                struct ocrdma_queue_info *q, int queue_type)
 385 {
 386         u8 opcode = 0;
 387         int status;
 388         struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
 389
 390         switch (queue_type) {
 391         case QTYPE_MCCQ:
 392                 opcode = OCRDMA_CMD_DELETE_MQ;
 393                 break;
 394         case QTYPE_CQ:
 395                 opcode = OCRDMA_CMD_DELETE_CQ;
 396                 break;
 397         case QTYPE_EQ:
 398                 opcode = OCRDMA_CMD_DELETE_EQ;
 399                 break;
 400         default:
 401                 BUG();
 402         }
 403         memset(cmd, 0, sizeof(*cmd));
 404         ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 405         cmd->id = q->id;
 406
 407         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 408                                  cmd, sizeof(*cmd), NULL, NULL);
 409         if (!status)
 410                 q->created = false;
 411         return status;
 412 }
 413
 414 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 415 {
 416         int status;
 417         struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
 418         struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
 419
 420         memset(cmd, 0, sizeof(*cmd));
 421         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
 422                         sizeof(*cmd));
 423
 424         cmd->req.rsvd_version = 2;
 425         cmd->num_pages = 4;
 426         cmd->valid = OCRDMA_CREATE_EQ_VALID;
 427         cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
 428
 429         ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
 430                              PAGE_SIZE_4K);
 431         status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
 432                                  NULL);
 433         if (!status) {
 434                 eq->q.id = rsp->vector_eqid & 0xffff;
 435                 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
 436                 eq->q.created = true;
 437         }
 438         return status;
 439 }
 440
 441 static int ocrdma_create_eq(struct ocrdma_dev *dev,
 442                             struct ocrdma_eq *eq, u16 q_len)
 443 {
 444         int status;
 445
 446         status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
 447                                 sizeof(struct ocrdma_eqe));
 448         if (status)
 449                 return status;
 450
 451         status = ocrdma_mbx_create_eq(dev, eq);
 452         if (status)
 453                 goto mbx_err;
 454         eq->dev = dev;
 455         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 456
 457         return 0;
 458 mbx_err:
 459         ocrdma_free_q(dev, &eq->q);
 460         return status;
 461 }
 462
 463 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 464 {
 465         int irq;
 466
 467         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
 468                 irq = dev->nic_info.pdev->irq;
 469         else
 470                 irq = dev->nic_info.msix.vector_list[eq->vector];
 471         return irq;
 472 }
 473
 474 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 475 {
 476         if (eq->q.created) {
 477                 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
 478                 ocrdma_free_q(dev, &eq->q);
 479         }
 480 }
 481
 482 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 483 {
 484         int irq;
 485
 486         /* disarm EQ so that interrupts are not generated
 487          * during freeing and EQ delete is in progress.
 488          */
 489         ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
 490
 491         irq = ocrdma_get_irq(dev, eq);
 492         free_irq(irq, eq);
 493         _ocrdma_destroy_eq(dev, eq);
 494 }
 495
 496 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
 497 {
 498         int i;
 499
 500         for (i = 0; i < dev->eq_cnt; i++)
 501                 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
 502 }
 503
 504 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
 505                                    struct ocrdma_queue_info *cq,
 506                                    struct ocrdma_queue_info *eq)
 507 {
 508         struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
 509         struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
 510         int status;
 511
 512         memset(cmd, 0, sizeof(*cmd));
 513         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
 514                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 515
 516         cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
 517         cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
 518                 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
 519         cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
 520
 521         cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
 522         cmd->eqn = eq->id;
 523         cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
 524
 525         ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
 526                              cq->dma, PAGE_SIZE_4K);
 527         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 528                                  cmd, sizeof(*cmd), NULL, NULL);
 529         if (!status) {
 530                 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
 531                 cq->created = true;
 532         }
 533         return status;
 534 }
 535
 536 static u32 ocrdma_encoded_q_len(int q_len)
 537 {
 538         u32 len_encoded = fls(q_len);   /* log2(len) + 1 */
 539
 540         if (len_encoded == 16)
 541                 len_encoded = 0;
 542         return len_encoded;
 543 }
 544
 545 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
 546                                 struct ocrdma_queue_info *mq,
 547                                 struct ocrdma_queue_info *cq)
 548 {
 549         int num_pages, status;
 550         struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
 551         struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
 552         struct ocrdma_pa *pa;
 553
 554         memset(cmd, 0, sizeof(*cmd));
 555         num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
 556
 557         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
 558                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 559         cmd->req.rsvd_version = 1;
 560         cmd->cqid_pages = num_pages;
 561         cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
 562         cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
 563
 564         cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
 565         cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
 566
 567         cmd->async_cqid_ringsize = cq->id;
 568         cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
 569                                 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
 570         cmd->valid = OCRDMA_CREATE_MQ_VALID;
 571         pa = &cmd->pa[0];
 572
 573         ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
 574         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 575                                  cmd, sizeof(*cmd), NULL, NULL);
 576         if (!status) {
 577                 mq->id = rsp->id;
 578                 mq->created = true;
 579         }
 580         return status;
 581 }
 582
 583 static int ocrdma_create_mq(struct ocrdma_dev *dev)
 584 {
 585         int status;
 586
 587         /* Alloc completion queue for Mailbox queue */
 588         status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
 589                                 sizeof(struct ocrdma_mcqe));
 590         if (status)
 591                 goto alloc_err;
 592
 593         dev->eq_tbl[0].cq_cnt++;
 594         status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
 595         if (status)
 596                 goto mbx_cq_free;
 597
 598         memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
 599         init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
 600         mutex_init(&dev->mqe_ctx.lock);
 601
 602         /* Alloc Mailbox queue */
 603         status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
 604                                 sizeof(struct ocrdma_mqe));
 605         if (status)
 606                 goto mbx_cq_destroy;
 607         status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
 608         if (status)
 609                 goto mbx_q_free;
 610         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
 611         return 0;
 612
 613 mbx_q_free:
 614         ocrdma_free_q(dev, &dev->mq.sq);
 615 mbx_cq_destroy:
 616         ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
 617 mbx_cq_free:
 618         ocrdma_free_q(dev, &dev->mq.cq);
 619 alloc_err:
 620         return status;
 621 }
 622
 623 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
 624 {
 625         struct ocrdma_queue_info *mbxq, *cq;
 626
 627         /* mqe_ctx lock synchronizes with any other pending cmds. */
 628         mutex_lock(&dev->mqe_ctx.lock);
 629         mbxq = &dev->mq.sq;
 630         if (mbxq->created) {
 631                 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
 632                 ocrdma_free_q(dev, mbxq);
 633         }
 634         mutex_unlock(&dev->mqe_ctx.lock);
 635
 636         cq = &dev->mq.cq;
 637         if (cq->created) {
 638                 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
 639                 ocrdma_free_q(dev, cq);
 640         }
 641 }
 642
 643 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
 644                                        struct ocrdma_qp *qp)
 645 {
 646         enum ib_qp_state new_ib_qps = IB_QPS_ERR;
 647         enum ib_qp_state old_ib_qps;
 648
 649         if (qp == NULL)
 650                 BUG();
 651         ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
 652 }
 653
 654 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
 655                                     struct ocrdma_ae_mcqe *cqe)
 656 {
 657         struct ocrdma_qp *qp = NULL;
 658         struct ocrdma_cq *cq = NULL;
 659         struct ib_event ib_evt;
 660         int cq_event = 0;
 661         int qp_event = 1;
 662         int srq_event = 0;
 663         int dev_event = 0;
 664         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 665             OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 666
 667         if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
 668                 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
 669         if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
 670                 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
 671
 672         memset(&ib_evt, 0, sizeof(ib_evt));
 673
 674         ib_evt.device = &dev->ibdev;
 675
 676         switch (type) {
 677         case OCRDMA_CQ_ERROR:
 678                 ib_evt.element.cq = &cq->ibcq;
 679                 ib_evt.event = IB_EVENT_CQ_ERR;
 680                 cq_event = 1;
 681                 qp_event = 0;
 682                 break;
 683         case OCRDMA_CQ_OVERRUN_ERROR:
 684                 ib_evt.element.cq = &cq->ibcq;
 685                 ib_evt.event = IB_EVENT_CQ_ERR;
 686                 cq_event = 1;
 687                 qp_event = 0;
 688                 break;
 689         case OCRDMA_CQ_QPCAT_ERROR:
 690                 ib_evt.element.qp = &qp->ibqp;
 691                 ib_evt.event = IB_EVENT_QP_FATAL;
 692                 ocrdma_process_qpcat_error(dev, qp);
 693                 break;
 694         case OCRDMA_QP_ACCESS_ERROR:
 695                 ib_evt.element.qp = &qp->ibqp;
 696                 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
 697                 break;
 698         case OCRDMA_QP_COMM_EST_EVENT:
 699                 ib_evt.element.qp = &qp->ibqp;
 700                 ib_evt.event = IB_EVENT_COMM_EST;
 701                 break;
 702         case OCRDMA_SQ_DRAINED_EVENT:
 703                 ib_evt.element.qp = &qp->ibqp;
 704                 ib_evt.event = IB_EVENT_SQ_DRAINED;
 705                 break;
 706         case OCRDMA_DEVICE_FATAL_EVENT:
 707                 ib_evt.element.port_num = 1;
 708                 ib_evt.event = IB_EVENT_DEVICE_FATAL;
 709                 qp_event = 0;
 710                 dev_event = 1;
 711                 break;
 712         case OCRDMA_SRQCAT_ERROR:
 713                 ib_evt.element.srq = &qp->srq->ibsrq;
 714                 ib_evt.event = IB_EVENT_SRQ_ERR;
 715                 srq_event = 1;
 716                 qp_event = 0;
 717                 break;
 718         case OCRDMA_SRQ_LIMIT_EVENT:
 719                 ib_evt.element.srq = &qp->srq->ibsrq;
 720                 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
 721                 srq_event = 1;
 722                 qp_event = 0;
 723                 break;
 724         case OCRDMA_QP_LAST_WQE_EVENT:
 725                 ib_evt.element.qp = &qp->ibqp;
 726                 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
 727                 break;
 728         default:
 729                 cq_event = 0;
 730                 qp_event = 0;
 731                 srq_event = 0;
 732                 dev_event = 0;
 733                 pr_err("%s() unknown type=0x%x\n", __func__, type);
 734                 break;
 735         }
 736
 737         if (type < OCRDMA_MAX_ASYNC_ERRORS)
 738                 atomic_inc(&dev->async_err_stats[type]);
 739
 740         if (qp_event) {
 741                 if (qp->ibqp.event_handler)
 742                         qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
 743         } else if (cq_event) {
 744                 if (cq->ibcq.event_handler)
 745                         cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
 746         } else if (srq_event) {
 747                 if (qp->srq->ibsrq.event_handler)
 748                         qp->srq->ibsrq.event_handler(&ib_evt,
 749                                                      qp->srq->ibsrq.
 750                                                      srq_context);
 751         } else if (dev_event) {
 752                 pr_err("%s: Fatal event received\n", dev->ibdev.name);
 753                 ib_dispatch_event(&ib_evt);
 754         }
 755
 756 }
 757
 758 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
 759                                         struct ocrdma_ae_mcqe *cqe)
 760 {
 761         struct ocrdma_ae_pvid_mcqe *evt;
 762         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 763                         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 764
 765         switch (type) {
 766         case OCRDMA_ASYNC_EVENT_PVID_STATE:
 767                 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
 768                 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
 769                         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
 770                         dev->pvid = ((evt->tag_enabled &
 771                                         OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
 772                                         OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
 773                 break;
 774
 775         case OCRDMA_ASYNC_EVENT_COS_VALUE:
 776                 atomic_set(&dev->update_sl, 1);
 777                 break;
 778         default:
 779                 /* Not interested evts. */
 780                 break;
 781         }
 782 }
 783
 784 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
 785 {
 786         /* async CQE processing */
 787         struct ocrdma_ae_mcqe *cqe = ae_cqe;
 788         u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
 789                         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
 790
 791         if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
 792                 ocrdma_dispatch_ibevent(dev, cqe);
 793         else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
 794                 ocrdma_process_grp5_aync(dev, cqe);
 795         else
 796                 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
 797                        dev->id, evt_code);
 798 }
 799
 800 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
 801 {
 802         if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
 803                 dev->mqe_ctx.cqe_status = (cqe->status &
 804                      OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
 805                 dev->mqe_ctx.ext_status =
 806                     (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
 807                     >> OCRDMA_MCQE_ESTATUS_SHIFT;
 808                 dev->mqe_ctx.cmd_done = true;
 809                 wake_up(&dev->mqe_ctx.cmd_wait);
 810         } else
 811                 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
 812                        __func__, cqe->tag_lo, dev->mqe_ctx.tag);
 813 }
 814
 815 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 816 {
 817         u16 cqe_popped = 0;
 818         struct ocrdma_mcqe *cqe;
 819
 820         while (1) {
 821                 cqe = ocrdma_get_mcqe(dev);
 822                 if (cqe == NULL)
 823                         break;
 824                 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
 825                 cqe_popped += 1;
 826                 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
 827                         ocrdma_process_acqe(dev, cqe);
 828                 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
 829                         ocrdma_process_mcqe(dev, cqe);
 830                 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
 831                 ocrdma_mcq_inc_tail(dev);
 832         }
 833         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
 834         return 0;
 835 }
 836
 837 static struct ocrdma_cq *_ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
 838                                 struct ocrdma_cq *cq, bool sq)
 839 {
 840         struct ocrdma_qp *qp;
 841         struct list_head *cur;
 842         struct ocrdma_cq *bcq = NULL;
 843         struct list_head *head = sq?(&cq->sq_head):(&cq->rq_head);
 844
 845         list_for_each(cur, head) {
 846                 if (sq)
 847                         qp = list_entry(cur, struct ocrdma_qp, sq_entry);
 848                 else
 849                         qp = list_entry(cur, struct ocrdma_qp, rq_entry);
 850
 851                 if (qp->srq)
 852                         continue;
 853                 /* if wq and rq share the same cq, than comp_handler
 854                  * is already invoked.
 855                  */
 856                 if (qp->sq_cq == qp->rq_cq)
 857                         continue;
 858                 /* if completion came on sq, rq's cq is buddy cq.
 859                  * if completion came on rq, sq's cq is buddy cq.
 860                  */
 861                 if (qp->sq_cq == cq)
 862                         bcq = qp->rq_cq;
 863                 else
 864                         bcq = qp->sq_cq;
 865                 return bcq;
 866         }
 867         return NULL;
 868 }
 869
 870 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
 871                                        struct ocrdma_cq *cq)
 872 {
 873         unsigned long flags;
 874         struct ocrdma_cq *bcq = NULL;
 875
 876         /* Go through list of QPs in error state which are using this CQ
 877          * and invoke its callback handler to trigger CQE processing for
 878          * error/flushed CQE. It is rare to find more than few entries in
 879          * this list as most consumers stops after getting error CQE.
 880          * List is traversed only once when a matching buddy cq found for a QP.
 881          */
 882         spin_lock_irqsave(&dev->flush_q_lock, flags);
 883         /* Check if buddy CQ is present.
 884          * true - Check for  SQ CQ
 885          * false - Check for RQ CQ
 886          */
 887         bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, true);
 888         if (bcq == NULL)
 889                 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, false);
 890         spin_unlock_irqrestore(&dev->flush_q_lock, flags);
 891
 892         /* if there is valid buddy cq, look for its completion handler */
 893         if (bcq && bcq->ibcq.comp_handler) {
 894                 spin_lock_irqsave(&bcq->comp_handler_lock, flags);
 895                 (*bcq->ibcq.comp_handler) (&bcq->ibcq, bcq->ibcq.cq_context);
 896                 spin_unlock_irqrestore(&bcq->comp_handler_lock, flags);
 897         }
 898 }
 899
 900 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
 901 {
 902         unsigned long flags;
 903         struct ocrdma_cq *cq;
 904
 905         if (cq_idx >= OCRDMA_MAX_CQ)
 906                 BUG();
 907
 908         cq = dev->cq_tbl[cq_idx];
 909         if (cq == NULL)
 910                 return;
 911
 912         if (cq->ibcq.comp_handler) {
 913                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 914                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 915                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 916         }
 917         ocrdma_qp_buddy_cq_handler(dev, cq);
 918 }
 919
 920 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 921 {
 922         /* process the MQ-CQE. */
 923         if (cq_id == dev->mq.cq.id)
 924                 ocrdma_mq_cq_handler(dev, cq_id);
 925         else
 926                 ocrdma_qp_cq_handler(dev, cq_id);
 927 }
 928
 929 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
 930 {
 931         struct ocrdma_eq *eq = handle;
 932         struct ocrdma_dev *dev = eq->dev;
 933         struct ocrdma_eqe eqe;
 934         struct ocrdma_eqe *ptr;
 935         u16 cq_id;
 936         int budget = eq->cq_cnt;
 937
 938         do {
 939                 ptr = ocrdma_get_eqe(eq);
 940                 eqe = *ptr;
 941                 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
 942                 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
 943                         break;
 944
 945                 ptr->id_valid = 0;
 946                 /* ring eq doorbell as soon as its consumed. */
 947                 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
 948                 /* check whether its CQE or not. */
 949                 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
 950                         cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
 951                         ocrdma_cq_handler(dev, cq_id);
 952                 }
 953                 ocrdma_eq_inc_tail(eq);
 954
 955                 /* There can be a stale EQE after the last bound CQ is
 956                  * destroyed. EQE valid and budget == 0 implies this.
 957                  */
 958                 if (budget)
 959                         budget--;
 960
 961         } while (budget);
 962
 963         eq->aic_obj.eq_intr_cnt++;
 964         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 965         return IRQ_HANDLED;
 966 }
 967
 968 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
 969 {
 970         struct ocrdma_mqe *mqe;
 971
 972         dev->mqe_ctx.tag = dev->mq.sq.head;
 973         dev->mqe_ctx.cmd_done = false;
 974         mqe = ocrdma_get_mqe(dev);
 975         cmd->hdr.tag_lo = dev->mq.sq.head;
 976         ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
 977         /* make sure descriptor is written before ringing doorbell */
 978         wmb();
 979         ocrdma_mq_inc_head(dev);
 980         ocrdma_ring_mq_db(dev);
 981 }
 982
 983 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
 984 {
 985         long status;
 986         /* 30 sec timeout */
 987         status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
 988                                     (dev->mqe_ctx.cmd_done != false),
 989                                     msecs_to_jiffies(30000));
 990         if (status)
 991                 return 0;
 992         else {
 993                 dev->mqe_ctx.fw_error_state = true;
 994                 pr_err("%s(%d) mailbox timeout: fw not responding\n",
 995                        __func__, dev->id);
 996                 return -1;
 997         }
 998 }
 999
1000 /* issue a mailbox command on the MQ */
1001 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
1002 {
1003         int status = 0;
1004         u16 cqe_status, ext_status;
1005         struct ocrdma_mqe *rsp_mqe;
1006         struct ocrdma_mbx_rsp *rsp = NULL;
1007
1008         mutex_lock(&dev->mqe_ctx.lock);
1009         if (dev->mqe_ctx.fw_error_state)
1010                 goto mbx_err;
1011         ocrdma_post_mqe(dev, mqe);
1012         status = ocrdma_wait_mqe_cmpl(dev);
1013         if (status)
1014                 goto mbx_err;
1015         cqe_status = dev->mqe_ctx.cqe_status;
1016         ext_status = dev->mqe_ctx.ext_status;
1017         rsp_mqe = ocrdma_get_mqe_rsp(dev);
1018         ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
1019         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1020                                 OCRDMA_MQE_HDR_EMB_SHIFT)
1021                 rsp = &mqe->u.rsp;
1022
1023         if (cqe_status || ext_status) {
1024                 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
1025                        __func__, cqe_status, ext_status);
1026                 if (rsp) {
1027                         /* This is for embedded cmds. */
1028                         pr_err("opcode=0x%x, subsystem=0x%x\n",
1029                                (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1030                                 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1031                                 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1032                                 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1033                 }
1034                 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1035                 goto mbx_err;
1036         }
1037         /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1038         if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1039                 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1040 mbx_err:
1041         mutex_unlock(&dev->mqe_ctx.lock);
1042         return status;
1043 }
1044
1045 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1046                                  void *payload_va)
1047 {
1048         int status = 0;
1049         struct ocrdma_mbx_rsp *rsp = payload_va;
1050
1051         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1052                                 OCRDMA_MQE_HDR_EMB_SHIFT)
1053                 BUG();
1054
1055         status = ocrdma_mbx_cmd(dev, mqe);
1056         if (!status)
1057                 /* For non embedded, only CQE failures are handled in
1058                  * ocrdma_mbx_cmd. We need to check for RSP errors.
1059                  */
1060                 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1061                         status = ocrdma_get_mbx_errno(rsp->status);
1062
1063         if (status)
1064                 pr_err("opcode=0x%x, subsystem=0x%x\n",
1065                        (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1066                         OCRDMA_MBX_RSP_OPCODE_SHIFT,
1067                         (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1068                         OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1069         return status;
1070 }
1071
1072 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1073                               struct ocrdma_dev_attr *attr,
1074                               struct ocrdma_mbx_query_config *rsp)
1075 {
1076         attr->max_pd =
1077             (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1078             OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1079         attr->max_dpp_pds =
1080            (rsp->max_dpp_pds_credits & OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK) >>
1081             OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET;
1082         attr->max_qp =
1083             (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1084             OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1085         attr->max_srq =
1086                 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1087                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1088         attr->max_send_sge = ((rsp->max_write_send_sge &
1089                                OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1090                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1091         attr->max_recv_sge = (rsp->max_write_send_sge &
1092                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1093             OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
1094         attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1095                               OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1096             OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1097         attr->max_rdma_sge = (rsp->max_write_send_sge &
1098                               OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1099             OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1100         attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1101                                 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1102             OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1103         attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1104                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1105             OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1106         attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1107                                     OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1108             OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1109         attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1110                                OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1111             OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1112         attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1113                                     OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1114             OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1115         attr->max_mw = rsp->max_mw;
1116         attr->max_mr = rsp->max_mr;
1117         attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1118                               rsp->max_mr_size_lo;
1119         attr->max_fmr = 0;
1120         attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1121         attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1122         attr->max_cqe = rsp->max_cq_cqes_per_cq &
1123                         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1124         attr->max_cq = (rsp->max_cq_cqes_per_cq &
1125                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1126                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1127         attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1128                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1129                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1130                 OCRDMA_WQE_STRIDE;
1131         attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1132                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1133                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1134                 OCRDMA_WQE_STRIDE;
1135         attr->max_inline_data =
1136             attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1137                               sizeof(struct ocrdma_sge));
1138         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1139                 attr->ird = 1;
1140                 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1141                 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1142         }
1143         dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1144                  OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1145         dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1146                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1147 }
1148
1149 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1150                                    struct ocrdma_fw_conf_rsp *conf)
1151 {
1152         u32 fn_mode;
1153
1154         fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1155         if (fn_mode != OCRDMA_FN_MODE_RDMA)
1156                 return -EINVAL;
1157         dev->base_eqid = conf->base_eqid;
1158         dev->max_eq = conf->max_eq;
1159         return 0;
1160 }
1161
1162 /* can be issued only during init time. */
1163 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1164 {
1165         int status = -ENOMEM;
1166         struct ocrdma_mqe *cmd;
1167         struct ocrdma_fw_ver_rsp *rsp;
1168
1169         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1170         if (!cmd)
1171                 return -ENOMEM;
1172         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1173                         OCRDMA_CMD_GET_FW_VER,
1174                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1175
1176         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1177         if (status)
1178                 goto mbx_err;
1179         rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1180         memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1181         memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1182                sizeof(rsp->running_ver));
1183         ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1184 mbx_err:
1185         kfree(cmd);
1186         return status;
1187 }
1188
1189 /* can be issued only during init time. */
1190 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1191 {
1192         int status = -ENOMEM;
1193         struct ocrdma_mqe *cmd;
1194         struct ocrdma_fw_conf_rsp *rsp;
1195
1196         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1197         if (!cmd)
1198                 return -ENOMEM;
1199         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1200                         OCRDMA_CMD_GET_FW_CONFIG,
1201                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1202         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1203         if (status)
1204                 goto mbx_err;
1205         rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1206         status = ocrdma_check_fw_config(dev, rsp);
1207 mbx_err:
1208         kfree(cmd);
1209         return status;
1210 }
1211
1212 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1213 {
1214         struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1215         struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1216         struct ocrdma_rdma_stats_resp *old_stats;
1217         int status;
1218
1219         old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL);
1220         if (old_stats == NULL)
1221                 return -ENOMEM;
1222
1223         memset(mqe, 0, sizeof(*mqe));
1224         mqe->hdr.pyld_len = dev->stats_mem.size;
1225         mqe->hdr.spcl_sge_cnt_emb |=
1226                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1227                                 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1228         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1229         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1230         mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1231
1232         /* Cache the old stats */
1233         memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1234         memset(req, 0, dev->stats_mem.size);
1235
1236         ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1237                         OCRDMA_CMD_GET_RDMA_STATS,
1238                         OCRDMA_SUBSYS_ROCE,
1239                         dev->stats_mem.size);
1240         if (reset)
1241                 req->reset_stats = reset;
1242
1243         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1244         if (status)
1245                 /* Copy from cache, if mbox fails */
1246                 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1247         else
1248                 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1249
1250         kfree(old_stats);
1251         return status;
1252 }
1253
1254 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1255 {
1256         int status = -ENOMEM;
1257         struct ocrdma_dma_mem dma;
1258         struct ocrdma_mqe *mqe;
1259         struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1260         struct mgmt_hba_attribs *hba_attribs;
1261
1262         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
1263         if (!mqe)
1264                 return status;
1265
1266         dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1267         dma.va   = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1268                                         dma.size, &dma.pa, GFP_KERNEL);
1269         if (!dma.va)
1270                 goto free_mqe;
1271
1272         mqe->hdr.pyld_len = dma.size;
1273         mqe->hdr.spcl_sge_cnt_emb |=
1274                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1275                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
1276         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1277         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1278         mqe->u.nonemb_req.sge[0].len = dma.size;
1279
1280         memset(dma.va, 0, dma.size);
1281         ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1282                         OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1283                         OCRDMA_SUBSYS_COMMON,
1284                         dma.size);
1285
1286         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1287         if (!status) {
1288                 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1289                 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1290
1291                 dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1292                                         OCRDMA_HBA_ATTRB_PTNUM_MASK)
1293                                         >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
1294                 strncpy(dev->model_number,
1295                         hba_attribs->controller_model_number, 31);
1296         }
1297         dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1298 free_mqe:
1299         kfree(mqe);
1300         return status;
1301 }
1302
1303 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1304 {
1305         int status = -ENOMEM;
1306         struct ocrdma_mbx_query_config *rsp;
1307         struct ocrdma_mqe *cmd;
1308
1309         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1310         if (!cmd)
1311                 return status;
1312         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1313         if (status)
1314                 goto mbx_err;
1315         rsp = (struct ocrdma_mbx_query_config *)cmd;
1316         ocrdma_get_attr(dev, &dev->attr, rsp);
1317 mbx_err:
1318         kfree(cmd);
1319         return status;
1320 }
1321
1322 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1323 {
1324         int status = -ENOMEM;
1325         struct ocrdma_get_link_speed_rsp *rsp;
1326         struct ocrdma_mqe *cmd;
1327
1328         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1329                                   sizeof(*cmd));
1330         if (!cmd)
1331                 return status;
1332         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1333                         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1334                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1335
1336         ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1337
1338         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1339         if (status)
1340                 goto mbx_err;
1341
1342         rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1343         *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1344                         >> OCRDMA_PHY_PS_SHIFT;
1345
1346 mbx_err:
1347         kfree(cmd);
1348         return status;
1349 }
1350
1351 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1352 {
1353         int status = -ENOMEM;
1354         struct ocrdma_mqe *cmd;
1355         struct ocrdma_get_phy_info_rsp *rsp;
1356
1357         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1358         if (!cmd)
1359                 return status;
1360
1361         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1362                         OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1363                         sizeof(*cmd));
1364
1365         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1366         if (status)
1367                 goto mbx_err;
1368
1369         rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1370         dev->phy.phy_type =
1371                         (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1372         dev->phy.interface_type =
1373                         (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1374                                 >> OCRDMA_IF_TYPE_SHIFT;
1375         dev->phy.auto_speeds_supported  =
1376                         (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
1377         dev->phy.fixed_speeds_supported =
1378                         (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1379                                 >> OCRDMA_FSPEED_SUPP_SHIFT;
1380 mbx_err:
1381         kfree(cmd);
1382         return status;
1383 }
1384
1385 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1386 {
1387         int status = -ENOMEM;
1388         struct ocrdma_alloc_pd *cmd;
1389         struct ocrdma_alloc_pd_rsp *rsp;
1390
1391         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1392         if (!cmd)
1393                 return status;
1394         if (pd->dpp_enabled)
1395                 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1396         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1397         if (status)
1398                 goto mbx_err;
1399         rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1400         pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1401         if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1402                 pd->dpp_enabled = true;
1403                 pd->dpp_page = rsp->dpp_page_pdid >>
1404                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1405         } else {
1406                 pd->dpp_enabled = false;
1407                 pd->num_dpp_qp = 0;
1408         }
1409 mbx_err:
1410         kfree(cmd);
1411         return status;
1412 }
1413
1414 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1415 {
1416         int status = -ENOMEM;
1417         struct ocrdma_dealloc_pd *cmd;
1418
1419         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1420         if (!cmd)
1421                 return status;
1422         cmd->id = pd->id;
1423         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1424         kfree(cmd);
1425         return status;
1426 }
1427
1428
1429 static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev *dev)
1430 {
1431         int status = -ENOMEM;
1432         size_t pd_bitmap_size;
1433         struct ocrdma_alloc_pd_range *cmd;
1434         struct ocrdma_alloc_pd_range_rsp *rsp;
1435
1436         /* Pre allocate the DPP PDs */
1437         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1438         if (!cmd)
1439                 return -ENOMEM;
1440         cmd->pd_count = dev->attr.max_dpp_pds;
1441         cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1442         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1443         if (status)
1444                 goto mbx_err;
1445         rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1446
1447         if ((rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) && rsp->pd_count) {
1448                 dev->pd_mgr->dpp_page_index = rsp->dpp_page_pdid >>
1449                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1450                 dev->pd_mgr->pd_dpp_start = rsp->dpp_page_pdid &
1451                                 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1452                 dev->pd_mgr->max_dpp_pd = rsp->pd_count;
1453                 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1454                 dev->pd_mgr->pd_dpp_bitmap = kzalloc(pd_bitmap_size,
1455                                                      GFP_KERNEL);
1456         }
1457         kfree(cmd);
1458
1459         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1460         if (!cmd)
1461                 return -ENOMEM;
1462
1463         cmd->pd_count = dev->attr.max_pd - dev->attr.max_dpp_pds;
1464         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1465         if (status)
1466                 goto mbx_err;
1467         rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1468         if (rsp->pd_count) {
1469                 dev->pd_mgr->pd_norm_start = rsp->dpp_page_pdid &
1470                                         OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1471                 dev->pd_mgr->max_normal_pd = rsp->pd_count;
1472                 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1473                 dev->pd_mgr->pd_norm_bitmap = kzalloc(pd_bitmap_size,
1474                                                       GFP_KERNEL);
1475         }
1476
1477         if (dev->pd_mgr->pd_norm_bitmap || dev->pd_mgr->pd_dpp_bitmap) {
1478                 /* Enable PD resource manager */
1479                 dev->pd_mgr->pd_prealloc_valid = true;
1480         } else {
1481                 return -ENOMEM;
1482         }
1483 mbx_err:
1484         kfree(cmd);
1485         return status;
1486 }
1487
1488 static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev *dev)
1489 {
1490         struct ocrdma_dealloc_pd_range *cmd;
1491
1492         /* return normal PDs to firmware */
1493         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, sizeof(*cmd));
1494         if (!cmd)
1495                 goto mbx_err;
1496
1497         if (dev->pd_mgr->max_normal_pd) {
1498                 cmd->start_pd_id = dev->pd_mgr->pd_norm_start;
1499                 cmd->pd_count = dev->pd_mgr->max_normal_pd;
1500                 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1501         }
1502
1503         if (dev->pd_mgr->max_dpp_pd) {
1504                 kfree(cmd);
1505                 /* return DPP PDs to firmware */
1506                 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE,
1507                                           sizeof(*cmd));
1508                 if (!cmd)
1509                         goto mbx_err;
1510
1511                 cmd->start_pd_id = dev->pd_mgr->pd_dpp_start;
1512                 cmd->pd_count = dev->pd_mgr->max_dpp_pd;
1513                 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1514         }
1515 mbx_err:
1516         kfree(cmd);
1517 }
1518
1519 void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev)
1520 {
1521         int status;
1522
1523         dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr),
1524                               GFP_KERNEL);
1525         if (!dev->pd_mgr) {
1526                 pr_err("%s(%d)Memory allocation failure.\n", __func__, dev->id);
1527                 return;
1528         }
1529         status = ocrdma_mbx_alloc_pd_range(dev);
1530         if (status) {
1531                 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
1532                          __func__, dev->id);
1533         }
1534 }
1535
1536 static void ocrdma_free_pd_pool(struct ocrdma_dev *dev)
1537 {
1538         ocrdma_mbx_dealloc_pd_range(dev);
1539         kfree(dev->pd_mgr->pd_norm_bitmap);
1540         kfree(dev->pd_mgr->pd_dpp_bitmap);
1541         kfree(dev->pd_mgr);
1542 }
1543
1544 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1545                                int *num_pages, int *page_size)
1546 {
1547         int i;
1548         int mem_size;
1549
1550         *num_entries = roundup_pow_of_two(*num_entries);
1551         mem_size = *num_entries * entry_size;
1552         /* find the possible lowest possible multiplier */
1553         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1554                 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1555                         break;
1556         }
1557         if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1558                 return -EINVAL;
1559         mem_size = roundup(mem_size,
1560                        ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1561         *num_pages =
1562             mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1563         *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1564         *num_entries = mem_size / entry_size;
1565         return 0;
1566 }
1567
1568 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1569 {
1570         int i;
1571         int status = 0;
1572         int max_ah;
1573         struct ocrdma_create_ah_tbl *cmd;
1574         struct ocrdma_create_ah_tbl_rsp *rsp;
1575         struct pci_dev *pdev = dev->nic_info.pdev;
1576         dma_addr_t pa;
1577         struct ocrdma_pbe *pbes;
1578
1579         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1580         if (!cmd)
1581                 return status;
1582
1583         max_ah = OCRDMA_MAX_AH;
1584         dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1585
1586         /* number of PBEs in PBL */
1587         cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1588                                 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1589                                 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1590
1591         /* page size */
1592         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1593                 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1594                         break;
1595         }
1596         cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1597                                 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1598
1599         /* ah_entry size */
1600         cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1601                                 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1602                                 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1603
1604         dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1605                                                 &dev->av_tbl.pbl.pa,
1606                                                 GFP_KERNEL);
1607         if (dev->av_tbl.pbl.va == NULL)
1608                 goto mem_err;
1609
1610         dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1611                                             &pa, GFP_KERNEL);
1612         if (dev->av_tbl.va == NULL)
1613                 goto mem_err_ah;
1614         dev->av_tbl.pa = pa;
1615         dev->av_tbl.num_ah = max_ah;
1616         memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1617
1618         pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1619         for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1620                 pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1621                 pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
1622                 pa += PAGE_SIZE;
1623         }
1624         cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1625         cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1626         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1627         if (status)
1628                 goto mbx_err;
1629         rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1630         dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1631         kfree(cmd);
1632         return 0;
1633
1634 mbx_err:
1635         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1636                           dev->av_tbl.pa);
1637         dev->av_tbl.va = NULL;
1638 mem_err_ah:
1639         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1640                           dev->av_tbl.pbl.pa);
1641         dev->av_tbl.pbl.va = NULL;
1642         dev->av_tbl.size = 0;
1643 mem_err:
1644         kfree(cmd);
1645         return status;
1646 }
1647
1648 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1649 {
1650         struct ocrdma_delete_ah_tbl *cmd;
1651         struct pci_dev *pdev = dev->nic_info.pdev;
1652
1653         if (dev->av_tbl.va == NULL)
1654                 return;
1655
1656         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1657         if (!cmd)
1658                 return;
1659         cmd->ahid = dev->av_tbl.ahid;
1660
1661         ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1662         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1663                           dev->av_tbl.pa);
1664         dev->av_tbl.va = NULL;
1665         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1666                           dev->av_tbl.pbl.pa);
1667         kfree(cmd);
1668 }
1669
1670 /* Multiple CQs uses the EQ. This routine returns least used
1671  * EQ to associate with CQ. This will distributes the interrupt
1672  * processing and CPU load to associated EQ, vector and so to that CPU.
1673  */
1674 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1675 {
1676         int i, selected_eq = 0, cq_cnt = 0;
1677         u16 eq_id;
1678
1679         mutex_lock(&dev->dev_lock);
1680         cq_cnt = dev->eq_tbl[0].cq_cnt;
1681         eq_id = dev->eq_tbl[0].q.id;
1682         /* find the EQ which is has the least number of
1683          * CQs associated with it.
1684          */
1685         for (i = 0; i < dev->eq_cnt; i++) {
1686                 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1687                         cq_cnt = dev->eq_tbl[i].cq_cnt;
1688                         eq_id = dev->eq_tbl[i].q.id;
1689                         selected_eq = i;
1690                 }
1691         }
1692         dev->eq_tbl[selected_eq].cq_cnt += 1;
1693         mutex_unlock(&dev->dev_lock);
1694         return eq_id;
1695 }
1696
1697 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1698 {
1699         int i;
1700
1701         mutex_lock(&dev->dev_lock);
1702         i = ocrdma_get_eq_table_index(dev, eq_id);
1703         if (i == -EINVAL)
1704                 BUG();
1705         dev->eq_tbl[i].cq_cnt -= 1;
1706         mutex_unlock(&dev->dev_lock);
1707 }
1708
1709 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1710                          int entries, int dpp_cq, u16 pd_id)
1711 {
1712         int status = -ENOMEM; int max_hw_cqe;
1713         struct pci_dev *pdev = dev->nic_info.pdev;
1714         struct ocrdma_create_cq *cmd;
1715         struct ocrdma_create_cq_rsp *rsp;
1716         u32 hw_pages, cqe_size, page_size, cqe_count;
1717
1718         if (entries > dev->attr.max_cqe) {
1719                 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1720                        __func__, dev->id, dev->attr.max_cqe, entries);
1721                 return -EINVAL;
1722         }
1723         if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1724                 return -EINVAL;
1725
1726         if (dpp_cq) {
1727                 cq->max_hw_cqe = 1;
1728                 max_hw_cqe = 1;
1729                 cqe_size = OCRDMA_DPP_CQE_SIZE;
1730                 hw_pages = 1;
1731         } else {
1732                 cq->max_hw_cqe = dev->attr.max_cqe;
1733                 max_hw_cqe = dev->attr.max_cqe;
1734                 cqe_size = sizeof(struct ocrdma_cqe);
1735                 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1736         }
1737
1738         cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1739
1740         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1741         if (!cmd)
1742                 return -ENOMEM;
1743         ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1744                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1745         cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1746         if (!cq->va) {
1747                 status = -ENOMEM;
1748                 goto mem_err;
1749         }
1750         memset(cq->va, 0, cq->len);
1751         page_size = cq->len / hw_pages;
1752         cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1753                                         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1754         cmd->cmd.pgsz_pgcnt |= hw_pages;
1755         cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1756
1757         cq->eqn = ocrdma_bind_eq(dev);
1758         cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1759         cqe_count = cq->len / cqe_size;
1760         cq->cqe_cnt = cqe_count;
1761         if (cqe_count > 1024) {
1762                 /* Set cnt to 3 to indicate more than 1024 cq entries */
1763                 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1764         } else {
1765                 u8 count = 0;
1766                 switch (cqe_count) {
1767                 case 256:
1768                         count = 0;
1769                         break;
1770                 case 512:
1771                         count = 1;
1772                         break;
1773                 case 1024:
1774                         count = 2;
1775                         break;
1776                 default:
1777                         goto mbx_err;
1778                 }
1779                 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1780         }
1781         /* shared eq between all the consumer cqs. */
1782         cmd->cmd.eqn = cq->eqn;
1783         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1784                 if (dpp_cq)
1785                         cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1786                                 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1787                 cq->phase_change = false;
1788                 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
1789         } else {
1790                 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
1791                 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1792                 cq->phase_change = true;
1793         }
1794
1795         /* pd_id valid only for v3 */
1796         cmd->cmd.pdid_cqecnt |= (pd_id <<
1797                 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
1798         ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1799         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1800         if (status)
1801                 goto mbx_err;
1802
1803         rsp = (struct ocrdma_create_cq_rsp *)cmd;
1804         cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1805         kfree(cmd);
1806         return 0;
1807 mbx_err:
1808         ocrdma_unbind_eq(dev, cq->eqn);
1809         dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1810 mem_err:
1811         kfree(cmd);
1812         return status;
1813 }
1814
1815 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1816 {
1817         int status = -ENOMEM;
1818         struct ocrdma_destroy_cq *cmd;
1819
1820         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1821         if (!cmd)
1822                 return status;
1823         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1824                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1825
1826         cmd->bypass_flush_qid |=
1827             (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1828             OCRDMA_DESTROY_CQ_QID_MASK;
1829
1830         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1831         ocrdma_unbind_eq(dev, cq->eqn);
1832         dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1833         kfree(cmd);
1834         return status;
1835 }
1836
1837 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1838                           u32 pdid, int addr_check)
1839 {
1840         int status = -ENOMEM;
1841         struct ocrdma_alloc_lkey *cmd;
1842         struct ocrdma_alloc_lkey_rsp *rsp;
1843
1844         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1845         if (!cmd)
1846                 return status;
1847         cmd->pdid = pdid;
1848         cmd->pbl_sz_flags |= addr_check;
1849         cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1850         cmd->pbl_sz_flags |=
1851             (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1852         cmd->pbl_sz_flags |=
1853             (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1854         cmd->pbl_sz_flags |=
1855             (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1856         cmd->pbl_sz_flags |=
1857             (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1858         cmd->pbl_sz_flags |=
1859             (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1860
1861         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1862         if (status)
1863                 goto mbx_err;
1864         rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1865         hwmr->lkey = rsp->lrkey;
1866 mbx_err:
1867         kfree(cmd);
1868         return status;
1869 }
1870
1871 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1872 {
1873         int status = -ENOMEM;
1874         struct ocrdma_dealloc_lkey *cmd;
1875
1876         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1877         if (!cmd)
1878                 return -ENOMEM;
1879         cmd->lkey = lkey;
1880         cmd->rsvd_frmr = fr_mr ? 1 : 0;
1881         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1882         if (status)
1883                 goto mbx_err;
1884 mbx_err:
1885         kfree(cmd);
1886         return status;
1887 }
1888
1889 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1890                              u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1891 {
1892         int status = -ENOMEM;
1893         int i;
1894         struct ocrdma_reg_nsmr *cmd;
1895         struct ocrdma_reg_nsmr_rsp *rsp;
1896
1897         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1898         if (!cmd)
1899                 return -ENOMEM;
1900         cmd->num_pbl_pdid =
1901             pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1902         cmd->fr_mr = hwmr->fr_mr;
1903
1904         cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1905                                     OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1906         cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1907                                     OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1908         cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1909                                     OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1910         cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1911                                     OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1912         cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1913                                     OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1914         cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1915
1916         cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1917         cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1918                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1919         cmd->totlen_low = hwmr->len;
1920         cmd->totlen_high = upper_32_bits(hwmr->len);
1921         cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1922         cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1923         cmd->va_loaddr = (u32) hwmr->va;
1924         cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1925
1926         for (i = 0; i < pbl_cnt; i++) {
1927                 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1928                 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1929         }
1930         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1931         if (status)
1932                 goto mbx_err;
1933         rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1934         hwmr->lkey = rsp->lrkey;
1935 mbx_err:
1936         kfree(cmd);
1937         return status;
1938 }
1939
1940 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1941                                   struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1942                                   u32 pbl_offset, u32 last)
1943 {
1944         int status = -ENOMEM;
1945         int i;
1946         struct ocrdma_reg_nsmr_cont *cmd;
1947
1948         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1949         if (!cmd)
1950                 return -ENOMEM;
1951         cmd->lrkey = hwmr->lkey;
1952         cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1953             (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1954         cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1955
1956         for (i = 0; i < pbl_cnt; i++) {
1957                 cmd->pbl[i].lo =
1958                     (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1959                 cmd->pbl[i].hi =
1960                     upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1961         }
1962         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1963         if (status)
1964                 goto mbx_err;
1965 mbx_err:
1966         kfree(cmd);
1967         return status;
1968 }
1969
1970 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1971                   struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1972 {
1973         int status;
1974         u32 last = 0;
1975         u32 cur_pbl_cnt, pbl_offset;
1976         u32 pending_pbl_cnt = hwmr->num_pbls;
1977
1978         pbl_offset = 0;
1979         cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1980         if (cur_pbl_cnt == pending_pbl_cnt)
1981                 last = 1;
1982
1983         status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1984                                    cur_pbl_cnt, hwmr->pbe_size, last);
1985         if (status) {
1986                 pr_err("%s() status=%d\n", __func__, status);
1987                 return status;
1988         }
1989         /* if there is no more pbls to register then exit. */
1990         if (last)
1991                 return 0;
1992
1993         while (!last) {
1994                 pbl_offset += cur_pbl_cnt;
1995                 pending_pbl_cnt -= cur_pbl_cnt;
1996                 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1997                 /* if we reach the end of the pbls, then need to set the last
1998                  * bit, indicating no more pbls to register for this memory key.
1999                  */
2000                 if (cur_pbl_cnt == pending_pbl_cnt)
2001                         last = 1;
2002
2003                 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
2004                                                 pbl_offset, last);
2005                 if (status)
2006                         break;
2007         }
2008         if (status)
2009                 pr_err("%s() err. status=%d\n", __func__, status);
2010
2011         return status;
2012 }
2013
2014 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2015 {
2016         struct ocrdma_qp *tmp;
2017         bool found = false;
2018         list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
2019                 if (qp == tmp) {
2020                         found = true;
2021                         break;
2022                 }
2023         }
2024         return found;
2025 }
2026
2027 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2028 {
2029         struct ocrdma_qp *tmp;
2030         bool found = false;
2031         list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
2032                 if (qp == tmp) {
2033                         found = true;
2034                         break;
2035                 }
2036         }
2037         return found;
2038 }
2039
2040 void ocrdma_flush_qp(struct ocrdma_qp *qp)
2041 {
2042         bool found;
2043         unsigned long flags;
2044         struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2045
2046         spin_lock_irqsave(&dev->flush_q_lock, flags);
2047         found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
2048         if (!found)
2049                 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
2050         if (!qp->srq) {
2051                 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
2052                 if (!found)
2053                         list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
2054         }
2055         spin_unlock_irqrestore(&dev->flush_q_lock, flags);
2056 }
2057
2058 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
2059 {
2060         qp->sq.head = 0;
2061         qp->sq.tail = 0;
2062         qp->rq.head = 0;
2063         qp->rq.tail = 0;
2064 }
2065
2066 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
2067                            enum ib_qp_state *old_ib_state)
2068 {
2069         unsigned long flags;
2070         int status = 0;
2071         enum ocrdma_qp_state new_state;
2072         new_state = get_ocrdma_qp_state(new_ib_state);
2073
2074         /* sync with wqe and rqe posting */
2075         spin_lock_irqsave(&qp->q_lock, flags);
2076
2077         if (old_ib_state)
2078                 *old_ib_state = get_ibqp_state(qp->state);
2079         if (new_state == qp->state) {
2080                 spin_unlock_irqrestore(&qp->q_lock, flags);
2081                 return 1;
2082         }
2083
2084
2085         if (new_state == OCRDMA_QPS_INIT) {
2086                 ocrdma_init_hwq_ptr(qp);
2087                 ocrdma_del_flush_qp(qp);
2088         } else if (new_state == OCRDMA_QPS_ERR) {
2089                 ocrdma_flush_qp(qp);
2090         }
2091
2092         qp->state = new_state;
2093
2094         spin_unlock_irqrestore(&qp->q_lock, flags);
2095         return status;
2096 }
2097
2098 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
2099 {
2100         u32 flags = 0;
2101         if (qp->cap_flags & OCRDMA_QP_INB_RD)
2102                 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
2103         if (qp->cap_flags & OCRDMA_QP_INB_WR)
2104                 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
2105         if (qp->cap_flags & OCRDMA_QP_MW_BIND)
2106                 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
2107         if (qp->cap_flags & OCRDMA_QP_LKEY0)
2108                 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
2109         if (qp->cap_flags & OCRDMA_QP_FAST_REG)
2110                 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
2111         return flags;
2112 }
2113
2114 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
2115                                         struct ib_qp_init_attr *attrs,
2116                                         struct ocrdma_qp *qp)
2117 {
2118         int status;
2119         u32 len, hw_pages, hw_page_size;
2120         dma_addr_t pa;
2121         struct ocrdma_pd *pd = qp->pd;
2122         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2123         struct pci_dev *pdev = dev->nic_info.pdev;
2124         u32 max_wqe_allocated;
2125         u32 max_sges = attrs->cap.max_send_sge;
2126
2127         /* QP1 may exceed 127 */
2128         max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
2129                                 dev->attr.max_wqe);
2130
2131         status = ocrdma_build_q_conf(&max_wqe_allocated,
2132                 dev->attr.wqe_size, &hw_pages, &hw_page_size);
2133         if (status) {
2134                 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
2135                        max_wqe_allocated);
2136                 return -EINVAL;
2137         }
2138         qp->sq.max_cnt = max_wqe_allocated;
2139         len = (hw_pages * hw_page_size);
2140
2141         qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2142         if (!qp->sq.va)
2143                 return -EINVAL;
2144         memset(qp->sq.va, 0, len);
2145         qp->sq.len = len;
2146         qp->sq.pa = pa;
2147         qp->sq.entry_size = dev->attr.wqe_size;
2148         ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2149
2150         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2151                                 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2152         cmd->num_wq_rq_pages |= (hw_pages <<
2153                                  OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2154             OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2155         cmd->max_sge_send_write |= (max_sges <<
2156                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2157             OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2158         cmd->max_sge_send_write |= (max_sges <<
2159                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2160                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2161         cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2162                              OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2163                                 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2164         cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2165                               OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2166                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2167         return 0;
2168 }
2169
2170 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2171                                         struct ib_qp_init_attr *attrs,
2172                                         struct ocrdma_qp *qp)
2173 {
2174         int status;
2175         u32 len, hw_pages, hw_page_size;
2176         dma_addr_t pa = 0;
2177         struct ocrdma_pd *pd = qp->pd;
2178         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2179         struct pci_dev *pdev = dev->nic_info.pdev;
2180         u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2181
2182         status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2183                                      &hw_pages, &hw_page_size);
2184         if (status) {
2185                 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2186                        attrs->cap.max_recv_wr + 1);
2187                 return status;
2188         }
2189         qp->rq.max_cnt = max_rqe_allocated;
2190         len = (hw_pages * hw_page_size);
2191
2192         qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2193         if (!qp->rq.va)
2194                 return -ENOMEM;
2195         memset(qp->rq.va, 0, len);
2196         qp->rq.pa = pa;
2197         qp->rq.len = len;
2198         qp->rq.entry_size = dev->attr.rqe_size;
2199
2200         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2201         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2202                 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2203         cmd->num_wq_rq_pages |=
2204             (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2205             OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2206         cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2207                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2208                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2209         cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2210                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2211                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2212         cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2213                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2214                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2215         return 0;
2216 }
2217
2218 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2219                                          struct ocrdma_pd *pd,
2220                                          struct ocrdma_qp *qp,
2221                                          u8 enable_dpp_cq, u16 dpp_cq_id)
2222 {
2223         pd->num_dpp_qp--;
2224         qp->dpp_enabled = true;
2225         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2226         if (!enable_dpp_cq)
2227                 return;
2228         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2229         cmd->dpp_credits_cqid = dpp_cq_id;
2230         cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2231                                         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2232 }
2233
2234 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2235                                         struct ocrdma_qp *qp)
2236 {
2237         struct ocrdma_pd *pd = qp->pd;
2238         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2239         struct pci_dev *pdev = dev->nic_info.pdev;
2240         dma_addr_t pa = 0;
2241         int ird_page_size = dev->attr.ird_page_size;
2242         int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2243         struct ocrdma_hdr_wqe *rqe;
2244         int i  = 0;
2245
2246         if (dev->attr.ird == 0)
2247                 return 0;
2248
2249         qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2250                                         &pa, GFP_KERNEL);
2251         if (!qp->ird_q_va)
2252                 return -ENOMEM;
2253         memset(qp->ird_q_va, 0, ird_q_len);
2254         ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2255                              pa, ird_page_size);
2256         for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2257                 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2258                         (i * dev->attr.rqe_size));
2259                 rqe->cw = 0;
2260                 rqe->cw |= 2;
2261                 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2262                 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2263                 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2264         }
2265         return 0;
2266 }
2267
2268 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2269                                      struct ocrdma_qp *qp,
2270                                      struct ib_qp_init_attr *attrs,
2271                                      u16 *dpp_offset, u16 *dpp_credit_lmt)
2272 {
2273         u32 max_wqe_allocated, max_rqe_allocated;
2274         qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2275         qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2276         qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2277         qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2278         qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2279         qp->dpp_enabled = false;
2280         if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2281                 qp->dpp_enabled = true;
2282                 *dpp_credit_lmt = (rsp->dpp_response &
2283                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2284                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2285                 *dpp_offset = (rsp->dpp_response &
2286                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2287                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2288         }
2289         max_wqe_allocated =
2290                 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2291         max_wqe_allocated = 1 << max_wqe_allocated;
2292         max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2293
2294         qp->sq.max_cnt = max_wqe_allocated;
2295         qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2296
2297         if (!attrs->srq) {
2298                 qp->rq.max_cnt = max_rqe_allocated;
2299                 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2300         }
2301 }
2302
2303 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2304                          u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2305                          u16 *dpp_credit_lmt)
2306 {
2307         int status = -ENOMEM;
2308         u32 flags = 0;
2309         struct ocrdma_pd *pd = qp->pd;
2310         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2311         struct pci_dev *pdev = dev->nic_info.pdev;
2312         struct ocrdma_cq *cq;
2313         struct ocrdma_create_qp_req *cmd;
2314         struct ocrdma_create_qp_rsp *rsp;
2315         int qptype;
2316
2317         switch (attrs->qp_type) {
2318         case IB_QPT_GSI:
2319                 qptype = OCRDMA_QPT_GSI;
2320                 break;
2321         case IB_QPT_RC:
2322                 qptype = OCRDMA_QPT_RC;
2323                 break;
2324         case IB_QPT_UD:
2325                 qptype = OCRDMA_QPT_UD;
2326                 break;
2327         default:
2328                 return -EINVAL;
2329         }
2330
2331         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2332         if (!cmd)
2333                 return status;
2334         cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2335                                                 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2336         status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2337         if (status)
2338                 goto sq_err;
2339
2340         if (attrs->srq) {
2341                 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2342                 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2343                 cmd->rq_addr[0].lo = srq->id;
2344                 qp->srq = srq;
2345         } else {
2346                 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2347                 if (status)
2348                         goto rq_err;
2349         }
2350
2351         status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2352         if (status)
2353                 goto mbx_err;
2354
2355         cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2356                                 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2357
2358         flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2359
2360         cmd->max_sge_recv_flags |= flags;
2361         cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2362                              OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2363                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2364         cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2365                              OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2366                                 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2367         cq = get_ocrdma_cq(attrs->send_cq);
2368         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2369                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2370         qp->sq_cq = cq;
2371         cq = get_ocrdma_cq(attrs->recv_cq);
2372         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2373                                 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2374         qp->rq_cq = cq;
2375
2376         if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2377             (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2378                 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2379                                              dpp_cq_id);
2380         }
2381
2382         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2383         if (status)
2384                 goto mbx_err;
2385         rsp = (struct ocrdma_create_qp_rsp *)cmd;
2386         ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2387         qp->state = OCRDMA_QPS_RST;
2388         kfree(cmd);
2389         return 0;
2390 mbx_err:
2391         if (qp->rq.va)
2392                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2393 rq_err:
2394         pr_err("%s(%d) rq_err\n", __func__, dev->id);
2395         dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2396 sq_err:
2397         pr_err("%s(%d) sq_err\n", __func__, dev->id);
2398         kfree(cmd);
2399         return status;
2400 }
2401
2402 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2403                         struct ocrdma_qp_params *param)
2404 {
2405         int status = -ENOMEM;
2406         struct ocrdma_query_qp *cmd;
2407         struct ocrdma_query_qp_rsp *rsp;
2408
2409         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2410         if (!cmd)
2411                 return status;
2412         cmd->qp_id = qp->id;
2413         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2414         if (status)
2415                 goto mbx_err;
2416         rsp = (struct ocrdma_query_qp_rsp *)cmd;
2417         memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2418 mbx_err:
2419         kfree(cmd);
2420         return status;
2421 }
2422
2423 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2424                                 struct ocrdma_modify_qp *cmd,
2425                                 struct ib_qp_attr *attrs,
2426                                 int attr_mask)
2427 {
2428         int status;
2429         struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2430         union ib_gid sgid, zgid;
2431         u32 vlan_id;
2432         u8 mac_addr[6];
2433         struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2434
2435         if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2436                 return -EINVAL;
2437         if (atomic_cmpxchg(&dev->update_sl, 1, 0))
2438                 ocrdma_init_service_level(dev);
2439         cmd->params.tclass_sq_psn |=
2440             (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2441         cmd->params.rnt_rc_sl_fl |=
2442             (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2443         cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2444         cmd->params.hop_lmt_rq_psn |=
2445             (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2446         cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2447         memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2448                sizeof(cmd->params.dgid));
2449         status = ocrdma_query_gid(&dev->ibdev, 1,
2450                         ah_attr->grh.sgid_index, &sgid);
2451         if (status)
2452                 return status;
2453
2454         memset(&zgid, 0, sizeof(zgid));
2455         if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2456                 return -EINVAL;
2457
2458         qp->sgid_idx = ah_attr->grh.sgid_index;
2459         memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2460         status = ocrdma_resolve_dmac(dev, ah_attr, &mac_addr[0]);
2461         if (status)
2462                 return status;
2463         cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2464                                 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2465         /* convert them to LE format. */
2466         ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2467         ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2468         cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2469         if (attr_mask & IB_QP_VID) {
2470                 vlan_id = attrs->vlan_id;
2471                 cmd->params.vlan_dmac_b4_to_b5 |=
2472                     vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2473                 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2474                 cmd->params.rnt_rc_sl_fl |=
2475                         (dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
2476         }
2477         return 0;
2478 }
2479
2480 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2481                                 struct ocrdma_modify_qp *cmd,
2482                                 struct ib_qp_attr *attrs, int attr_mask)
2483 {
2484         int status = 0;
2485         struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2486
2487         if (attr_mask & IB_QP_PKEY_INDEX) {
2488                 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2489                                             OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2490                 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2491         }
2492         if (attr_mask & IB_QP_QKEY) {
2493                 qp->qkey = attrs->qkey;
2494                 cmd->params.qkey = attrs->qkey;
2495                 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2496         }
2497         if (attr_mask & IB_QP_AV) {
2498                 status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
2499                 if (status)
2500                         return status;
2501         } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2502                 /* set the default mac address for UD, GSI QPs */
2503                 cmd->params.dmac_b0_to_b3 = dev->nic_info.mac_addr[0] |
2504                         (dev->nic_info.mac_addr[1] << 8) |
2505                         (dev->nic_info.mac_addr[2] << 16) |
2506                         (dev->nic_info.mac_addr[3] << 24);
2507                 cmd->params.vlan_dmac_b4_to_b5 = dev->nic_info.mac_addr[4] |
2508                                         (dev->nic_info.mac_addr[5] << 8);
2509         }
2510         if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2511             attrs->en_sqd_async_notify) {
2512                 cmd->params.max_sge_recv_flags |=
2513                         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2514                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2515         }
2516         if (attr_mask & IB_QP_DEST_QPN) {
2517                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2518                                 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2519                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2520         }
2521         if (attr_mask & IB_QP_PATH_MTU) {
2522                 if (attrs->path_mtu < IB_MTU_256 ||
2523                     attrs->path_mtu > IB_MTU_4096) {
2524                         status = -EINVAL;
2525                         goto pmtu_err;
2526                 }
2527                 cmd->params.path_mtu_pkey_indx |=
2528                     (ib_mtu_enum_to_int(attrs->path_mtu) <<
2529                      OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2530                     OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2531                 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2532         }
2533         if (attr_mask & IB_QP_TIMEOUT) {
2534                 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2535                     OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2536                 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2537         }
2538         if (attr_mask & IB_QP_RETRY_CNT) {
2539                 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2540                                       OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2541                     OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2542                 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2543         }
2544         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2545                 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2546                                       OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2547                     OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2548                 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2549         }
2550         if (attr_mask & IB_QP_RNR_RETRY) {
2551                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2552                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2553                         & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2554                 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2555         }
2556         if (attr_mask & IB_QP_SQ_PSN) {
2557                 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2558                 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2559         }
2560         if (attr_mask & IB_QP_RQ_PSN) {
2561                 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2562                 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2563         }
2564         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2565                 if (attrs->max_rd_atomic > dev->attr.max_ord_per_qp) {
2566                         status = -EINVAL;
2567                         goto pmtu_err;
2568                 }
2569                 qp->max_ord = attrs->max_rd_atomic;
2570                 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2571         }
2572         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2573                 if (attrs->max_dest_rd_atomic > dev->attr.max_ird_per_qp) {
2574                         status = -EINVAL;
2575                         goto pmtu_err;
2576                 }
2577                 qp->max_ird = attrs->max_dest_rd_atomic;
2578                 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2579         }
2580         cmd->params.max_ord_ird = (qp->max_ord <<
2581                                 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2582                                 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2583 pmtu_err:
2584         return status;
2585 }
2586
2587 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2588                          struct ib_qp_attr *attrs, int attr_mask)
2589 {
2590         int status = -ENOMEM;
2591         struct ocrdma_modify_qp *cmd;
2592
2593         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2594         if (!cmd)
2595                 return status;
2596
2597         cmd->params.id = qp->id;
2598         cmd->flags = 0;
2599         if (attr_mask & IB_QP_STATE) {
2600                 cmd->params.max_sge_recv_flags |=
2601                     (get_ocrdma_qp_state(attrs->qp_state) <<
2602                      OCRDMA_QP_PARAMS_STATE_SHIFT) &
2603                     OCRDMA_QP_PARAMS_STATE_MASK;
2604                 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2605         } else {
2606                 cmd->params.max_sge_recv_flags |=
2607                     (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2608                     OCRDMA_QP_PARAMS_STATE_MASK;
2609         }
2610
2611         status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2612         if (status)
2613                 goto mbx_err;
2614         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2615         if (status)
2616                 goto mbx_err;
2617
2618 mbx_err:
2619         kfree(cmd);
2620         return status;
2621 }
2622
2623 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2624 {
2625         int status = -ENOMEM;
2626         struct ocrdma_destroy_qp *cmd;
2627         struct pci_dev *pdev = dev->nic_info.pdev;
2628
2629         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2630         if (!cmd)
2631                 return status;
2632         cmd->qp_id = qp->id;
2633         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2634         if (status)
2635                 goto mbx_err;
2636
2637 mbx_err:
2638         kfree(cmd);
2639         if (qp->sq.va)
2640                 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2641         if (!qp->srq && qp->rq.va)
2642                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2643         if (qp->dpp_enabled)
2644                 qp->pd->num_dpp_qp++;
2645         return status;
2646 }
2647
2648 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2649                           struct ib_srq_init_attr *srq_attr,
2650                           struct ocrdma_pd *pd)
2651 {
2652         int status = -ENOMEM;
2653         int hw_pages, hw_page_size;
2654         int len;
2655         struct ocrdma_create_srq_rsp *rsp;
2656         struct ocrdma_create_srq *cmd;
2657         dma_addr_t pa;
2658         struct pci_dev *pdev = dev->nic_info.pdev;
2659         u32 max_rqe_allocated;
2660
2661         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2662         if (!cmd)
2663                 return status;
2664
2665         cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2666         max_rqe_allocated = srq_attr->attr.max_wr + 1;
2667         status = ocrdma_build_q_conf(&max_rqe_allocated,
2668                                 dev->attr.rqe_size,
2669                                 &hw_pages, &hw_page_size);
2670         if (status) {
2671                 pr_err("%s() req. max_wr=0x%x\n", __func__,
2672                        srq_attr->attr.max_wr);
2673                 status = -EINVAL;
2674                 goto ret;
2675         }
2676         len = hw_pages * hw_page_size;
2677         srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2678         if (!srq->rq.va) {
2679                 status = -ENOMEM;
2680                 goto ret;
2681         }
2682         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2683
2684         srq->rq.entry_size = dev->attr.rqe_size;
2685         srq->rq.pa = pa;
2686         srq->rq.len = len;
2687         srq->rq.max_cnt = max_rqe_allocated;
2688
2689         cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2690         cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2691                                 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2692
2693         cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2694                 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2695         cmd->pages_rqe_sz |= (dev->attr.rqe_size
2696                 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2697                 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2698         cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2699
2700         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2701         if (status)
2702                 goto mbx_err;
2703         rsp = (struct ocrdma_create_srq_rsp *)cmd;
2704         srq->id = rsp->id;
2705         srq->rq.dbid = rsp->id;
2706         max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2707                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2708                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2709         max_rqe_allocated = (1 << max_rqe_allocated);
2710         srq->rq.max_cnt = max_rqe_allocated;
2711         srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2712         srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2713                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2714                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2715         goto ret;
2716 mbx_err:
2717         dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2718 ret:
2719         kfree(cmd);
2720         return status;
2721 }
2722
2723 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2724 {
2725         int status = -ENOMEM;
2726         struct ocrdma_modify_srq *cmd;
2727         struct ocrdma_pd *pd = srq->pd;
2728         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2729
2730         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2731         if (!cmd)
2732                 return status;
2733         cmd->id = srq->id;
2734         cmd->limit_max_rqe |= srq_attr->srq_limit <<
2735             OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2736         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2737         kfree(cmd);
2738         return status;
2739 }
2740
2741 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2742 {
2743         int status = -ENOMEM;
2744         struct ocrdma_query_srq *cmd;
2745         struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2746
2747         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2748         if (!cmd)
2749                 return status;
2750         cmd->id = srq->rq.dbid;
2751         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2752         if (status == 0) {
2753                 struct ocrdma_query_srq_rsp *rsp =
2754                     (struct ocrdma_query_srq_rsp *)cmd;
2755                 srq_attr->max_sge =
2756                     rsp->srq_lmt_max_sge &
2757                     OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2758                 srq_attr->max_wr =
2759                     rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2760                 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2761                     OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2762         }
2763         kfree(cmd);
2764         return status;
2765 }
2766
2767 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2768 {
2769         int status = -ENOMEM;
2770         struct ocrdma_destroy_srq *cmd;
2771         struct pci_dev *pdev = dev->nic_info.pdev;
2772         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2773         if (!cmd)
2774                 return status;
2775         cmd->id = srq->id;
2776         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2777         if (srq->rq.va)
2778                 dma_free_coherent(&pdev->dev, srq->rq.len,
2779                                   srq->rq.va, srq->rq.pa);
2780         kfree(cmd);
2781         return status;
2782 }
2783
2784 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2785                                       struct ocrdma_dcbx_cfg *dcbxcfg)
2786 {
2787         int status = 0;
2788         dma_addr_t pa;
2789         struct ocrdma_mqe cmd;
2790
2791         struct ocrdma_get_dcbx_cfg_req *req = NULL;
2792         struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2793         struct pci_dev *pdev = dev->nic_info.pdev;
2794         struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2795
2796         memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2797         cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2798                                         sizeof(struct ocrdma_get_dcbx_cfg_req));
2799         req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2800         if (!req) {
2801                 status = -ENOMEM;
2802                 goto mem_err;
2803         }
2804
2805         cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2806                                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
2807         mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2808         mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2809         mqe_sge->len = cmd.hdr.pyld_len;
2810
2811         memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2812         ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2813                         OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2814         req->param_type = ptype;
2815
2816         status = ocrdma_mbx_cmd(dev, &cmd);
2817         if (status)
2818                 goto mbx_err;
2819
2820         rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2821         ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2822         memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2823
2824 mbx_err:
2825         dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2826 mem_err:
2827         return status;
2828 }
2829
2830 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX  0x08
2831 #define OCRDMA_DEFAULT_SERVICE_LEVEL    0x05
2832
2833 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2834                                     struct ocrdma_dcbx_cfg *dcbxcfg,
2835                                     u8 *srvc_lvl)
2836 {
2837         int status = -EINVAL, indx, slindx;
2838         int ventry_cnt;
2839         struct ocrdma_app_parameter *app_param;
2840         u8 valid, proto_sel;
2841         u8 app_prio, pfc_prio;
2842         u16 proto;
2843
2844         if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2845                 pr_info("%s ocrdma%d DCBX is disabled\n",
2846                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2847                 goto out;
2848         }
2849
2850         if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2851                 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2852                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2853                         (ptype > 0 ? "operational" : "admin"),
2854                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2855                         "enabled" : "disabled",
2856                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2857                         "" : ", not sync'ed");
2858                 goto out;
2859         } else {
2860                 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2861                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2862         }
2863
2864         ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2865                                 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2866                                 & OCRDMA_DCBX_STATE_MASK;
2867
2868         for (indx = 0; indx < ventry_cnt; indx++) {
2869                 app_param = &dcbxcfg->app_param[indx];
2870                 valid = (app_param->valid_proto_app >>
2871                                 OCRDMA_APP_PARAM_VALID_SHIFT)
2872                                 & OCRDMA_APP_PARAM_VALID_MASK;
2873                 proto_sel = (app_param->valid_proto_app
2874                                 >>  OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2875                                 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2876                 proto = app_param->valid_proto_app &
2877                                 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2878
2879                 if (
2880                         valid && proto == OCRDMA_APP_PROTO_ROCE &&
2881                         proto_sel == OCRDMA_PROTO_SELECT_L2) {
2882                         for (slindx = 0; slindx <
2883                                 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2884                                 app_prio = ocrdma_get_app_prio(
2885                                                 (u8 *)app_param->app_prio,
2886                                                 slindx);
2887                                 pfc_prio = ocrdma_get_pfc_prio(
2888                                                 (u8 *)dcbxcfg->pfc_prio,
2889                                                 slindx);
2890
2891                                 if (app_prio && pfc_prio) {
2892                                         *srvc_lvl = slindx;
2893                                         status = 0;
2894                                         goto out;
2895                                 }
2896                         }
2897                         if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2898                                 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2899                                         dev_name(&dev->nic_info.pdev->dev),
2900                                         dev->id, proto);
2901                         }
2902                 }
2903         }
2904
2905 out:
2906         return status;
2907 }
2908
2909 void ocrdma_init_service_level(struct ocrdma_dev *dev)
2910 {
2911         int status = 0, indx;
2912         struct ocrdma_dcbx_cfg dcbxcfg;
2913         u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
2914         int ptype = OCRDMA_PARAMETER_TYPE_OPER;
2915
2916         for (indx = 0; indx < 2; indx++) {
2917                 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
2918                 if (status) {
2919                         pr_err("%s(): status=%d\n", __func__, status);
2920                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2921                         continue;
2922                 }
2923
2924                 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
2925                                                   &dcbxcfg, &srvc_lvl);
2926                 if (status) {
2927                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2928                         continue;
2929                 }
2930
2931                 break;
2932         }
2933
2934         if (status)
2935                 pr_info("%s ocrdma%d service level default\n",
2936                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2937         else
2938                 pr_info("%s ocrdma%d service level %d\n",
2939                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2940                         srvc_lvl);
2941
2942         dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
2943         dev->sl = srvc_lvl;
2944 }
2945
2946 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2947 {
2948         int i;
2949         int status = -EINVAL;
2950         struct ocrdma_av *av;
2951         unsigned long flags;
2952
2953         av = dev->av_tbl.va;
2954         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2955         for (i = 0; i < dev->av_tbl.num_ah; i++) {
2956                 if (av->valid == 0) {
2957                         av->valid = OCRDMA_AV_VALID;
2958                         ah->av = av;
2959                         ah->id = i;
2960                         status = 0;
2961                         break;
2962                 }
2963                 av++;
2964         }
2965         if (i == dev->av_tbl.num_ah)
2966                 status = -EAGAIN;
2967         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2968         return status;
2969 }
2970
2971 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2972 {
2973         unsigned long flags;
2974         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2975         ah->av->valid = 0;
2976         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2977         return 0;
2978 }
2979
2980 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
2981 {
2982         int num_eq, i, status = 0;
2983         int irq;
2984         unsigned long flags = 0;
2985
2986         num_eq = dev->nic_info.msix.num_vectors -
2987                         dev->nic_info.msix.start_vector;
2988         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2989                 num_eq = 1;
2990                 flags = IRQF_SHARED;
2991         } else {
2992                 num_eq = min_t(u32, num_eq, num_online_cpus());
2993         }
2994
2995         if (!num_eq)
2996                 return -EINVAL;
2997
2998         dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2999         if (!dev->eq_tbl)
3000                 return -ENOMEM;
3001
3002         for (i = 0; i < num_eq; i++) {
3003                 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
3004                                         OCRDMA_EQ_LEN);
3005                 if (status) {
3006                         status = -EINVAL;
3007                         break;
3008                 }
3009                 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
3010                         dev->id, i);
3011                 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
3012                 status = request_irq(irq, ocrdma_irq_handler, flags,
3013                                      dev->eq_tbl[i].irq_name,
3014                                      &dev->eq_tbl[i]);
3015                 if (status)
3016                         goto done;
3017                 dev->eq_cnt += 1;
3018         }
3019         /* one eq is sufficient for data path to work */
3020         return 0;
3021 done:
3022         ocrdma_destroy_eqs(dev);
3023         return status;
3024 }
3025
3026 static int ocrdma_mbx_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3027                                  int num)
3028 {
3029         int i, status = -ENOMEM;
3030         struct ocrdma_modify_eqd_req *cmd;
3031
3032         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_EQ_DELAY, sizeof(*cmd));
3033         if (!cmd)
3034                 return status;
3035
3036         ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_MODIFY_EQ_DELAY,
3037                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
3038
3039         cmd->cmd.num_eq = num;
3040         for (i = 0; i < num; i++) {
3041                 cmd->cmd.set_eqd[i].eq_id = eq[i].q.id;
3042                 cmd->cmd.set_eqd[i].phase = 0;
3043                 cmd->cmd.set_eqd[i].delay_multiplier =
3044                                 (eq[i].aic_obj.prev_eqd * 65)/100;
3045         }
3046         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
3047         if (status)
3048                 goto mbx_err;
3049 mbx_err:
3050         kfree(cmd);
3051         return status;
3052 }
3053
3054 static int ocrdma_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3055                              int num)
3056 {
3057         int num_eqs, i = 0;
3058         if (num > 8) {
3059                 while (num) {
3060                         num_eqs = min(num, 8);
3061                         ocrdma_mbx_modify_eqd(dev, &eq[i], num_eqs);
3062                         i += num_eqs;
3063                         num -= num_eqs;
3064                 }
3065         } else {
3066                 ocrdma_mbx_modify_eqd(dev, eq, num);
3067         }
3068         return 0;
3069 }
3070
3071 void ocrdma_eqd_set_task(struct work_struct *work)
3072 {
3073         struct ocrdma_dev *dev =
3074                 container_of(work, struct ocrdma_dev, eqd_work.work);
3075         struct ocrdma_eq *eq = 0;
3076         int i, num = 0, status = -EINVAL;
3077         u64 eq_intr;
3078
3079         for (i = 0; i < dev->eq_cnt; i++) {
3080                 eq = &dev->eq_tbl[i];
3081                 if (eq->aic_obj.eq_intr_cnt > eq->aic_obj.prev_eq_intr_cnt) {
3082                         eq_intr = eq->aic_obj.eq_intr_cnt -
3083                                   eq->aic_obj.prev_eq_intr_cnt;
3084                         if ((eq_intr > EQ_INTR_PER_SEC_THRSH_HI) &&
3085                             (eq->aic_obj.prev_eqd == EQ_AIC_MIN_EQD)) {
3086                                 eq->aic_obj.prev_eqd = EQ_AIC_MAX_EQD;
3087                                 num++;
3088                         } else if ((eq_intr < EQ_INTR_PER_SEC_THRSH_LOW) &&
3089                                    (eq->aic_obj.prev_eqd == EQ_AIC_MAX_EQD)) {
3090                                 eq->aic_obj.prev_eqd = EQ_AIC_MIN_EQD;
3091                                 num++;
3092                         }
3093                 }
3094                 eq->aic_obj.prev_eq_intr_cnt = eq->aic_obj.eq_intr_cnt;
3095         }
3096
3097         if (num)
3098                 status = ocrdma_modify_eqd(dev, &dev->eq_tbl[0], num);
3099         schedule_delayed_work(&dev->eqd_work, msecs_to_jiffies(1000));
3100 }
3101
3102 int ocrdma_init_hw(struct ocrdma_dev *dev)
3103 {
3104         int status;
3105
3106         /* create the eqs  */
3107         status = ocrdma_create_eqs(dev);
3108         if (status)
3109                 goto qpeq_err;
3110         status = ocrdma_create_mq(dev);
3111         if (status)
3112                 goto mq_err;
3113         status = ocrdma_mbx_query_fw_config(dev);
3114         if (status)
3115                 goto conf_err;
3116         status = ocrdma_mbx_query_dev(dev);
3117         if (status)
3118                 goto conf_err;
3119         status = ocrdma_mbx_query_fw_ver(dev);
3120         if (status)
3121                 goto conf_err;
3122         status = ocrdma_mbx_create_ah_tbl(dev);
3123         if (status)
3124                 goto conf_err;
3125         status = ocrdma_mbx_get_phy_info(dev);
3126         if (status)
3127                 goto info_attrb_err;
3128         status = ocrdma_mbx_get_ctrl_attribs(dev);
3129         if (status)
3130                 goto info_attrb_err;
3131
3132         return 0;
3133
3134 info_attrb_err:
3135         ocrdma_mbx_delete_ah_tbl(dev);
3136 conf_err:
3137         ocrdma_destroy_mq(dev);
3138 mq_err:
3139         ocrdma_destroy_eqs(dev);
3140 qpeq_err:
3141         pr_err("%s() status=%d\n", __func__, status);
3142         return status;
3143 }
3144
3145 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
3146 {
3147         ocrdma_free_pd_pool(dev);
3148         ocrdma_mbx_delete_ah_tbl(dev);
3149
3150         /* cleanup the eqs */
3151         ocrdma_destroy_eqs(dev);
3152
3153         /* cleanup the control path */
3154         ocrdma_destroy_mq(dev);
3155 }