2 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * This file contains all of the code that is specific to the
36 * QLogic_IB 7220 chip (except that specific to the SerDes)
39 #include <linux/interrupt.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/module.h>
44 #include <rdma/ib_verbs.h>
49 static void qib_setup_7220_setextled(struct qib_pportdata *, u32);
50 static void qib_7220_handle_hwerrors(struct qib_devdata *, char *, size_t);
51 static void sendctrl_7220_mod(struct qib_pportdata *ppd, u32 op);
52 static u32 qib_7220_iblink_state(u64);
53 static u8 qib_7220_phys_portstate(u64);
54 static void qib_sdma_update_7220_tail(struct qib_pportdata *, u16);
55 static void qib_set_ib_7220_lstate(struct qib_pportdata *, u16, u16);
58 * This file contains almost all the chip-specific register information and
59 * access functions for the QLogic QLogic_IB 7220 PCI-Express chip, with the
60 * exception of SerDes support, which in in qib_sd7220.c.
63 /* Below uses machine-generated qib_chipnum_regs.h file */
64 #define KREG_IDX(regname) (QIB_7220_##regname##_OFFS / sizeof(u64))
66 /* Use defines to tie machine-generated names to lower-case names */
67 #define kr_control KREG_IDX(Control)
68 #define kr_counterregbase KREG_IDX(CntrRegBase)
69 #define kr_errclear KREG_IDX(ErrClear)
70 #define kr_errmask KREG_IDX(ErrMask)
71 #define kr_errstatus KREG_IDX(ErrStatus)
72 #define kr_extctrl KREG_IDX(EXTCtrl)
73 #define kr_extstatus KREG_IDX(EXTStatus)
74 #define kr_gpio_clear KREG_IDX(GPIOClear)
75 #define kr_gpio_mask KREG_IDX(GPIOMask)
76 #define kr_gpio_out KREG_IDX(GPIOOut)
77 #define kr_gpio_status KREG_IDX(GPIOStatus)
78 #define kr_hrtbt_guid KREG_IDX(HRTBT_GUID)
79 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
80 #define kr_hwerrclear KREG_IDX(HwErrClear)
81 #define kr_hwerrmask KREG_IDX(HwErrMask)
82 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
83 #define kr_ibcctrl KREG_IDX(IBCCtrl)
84 #define kr_ibcddrctrl KREG_IDX(IBCDDRCtrl)
85 #define kr_ibcddrstatus KREG_IDX(IBCDDRStatus)
86 #define kr_ibcstatus KREG_IDX(IBCStatus)
87 #define kr_ibserdesctrl KREG_IDX(IBSerDesCtrl)
88 #define kr_intclear KREG_IDX(IntClear)
89 #define kr_intmask KREG_IDX(IntMask)
90 #define kr_intstatus KREG_IDX(IntStatus)
91 #define kr_ncmodectrl KREG_IDX(IBNCModeCtrl)
92 #define kr_palign KREG_IDX(PageAlign)
93 #define kr_partitionkey KREG_IDX(RcvPartitionKey)
94 #define kr_portcnt KREG_IDX(PortCnt)
95 #define kr_rcvbthqp KREG_IDX(RcvBTHQP)
96 #define kr_rcvctrl KREG_IDX(RcvCtrl)
97 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
98 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
99 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
100 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
101 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
102 #define kr_rcvpktledcnt KREG_IDX(RcvPktLEDCnt)
103 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
104 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
105 #define kr_revision KREG_IDX(Revision)
106 #define kr_scratch KREG_IDX(Scratch)
107 #define kr_sendbuffererror KREG_IDX(SendBufErr0)
108 #define kr_sendctrl KREG_IDX(SendCtrl)
109 #define kr_senddmabase KREG_IDX(SendDmaBase)
110 #define kr_senddmabufmask0 KREG_IDX(SendDmaBufMask0)
111 #define kr_senddmabufmask1 (KREG_IDX(SendDmaBufMask0) + 1)
112 #define kr_senddmabufmask2 (KREG_IDX(SendDmaBufMask0) + 2)
113 #define kr_senddmahead KREG_IDX(SendDmaHead)
114 #define kr_senddmaheadaddr KREG_IDX(SendDmaHeadAddr)
115 #define kr_senddmalengen KREG_IDX(SendDmaLenGen)
116 #define kr_senddmastatus KREG_IDX(SendDmaStatus)
117 #define kr_senddmatail KREG_IDX(SendDmaTail)
118 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
119 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
120 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
121 #define kr_sendpiosize KREG_IDX(SendBufSize)
122 #define kr_sendregbase KREG_IDX(SendRegBase)
123 #define kr_userregbase KREG_IDX(UserRegBase)
124 #define kr_xgxs_cfg KREG_IDX(XGXSCfg)
126 /* These must only be written via qib_write_kreg_ctxt() */
127 #define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0)
128 #define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
131 #define CREG_IDX(regname) ((QIB_7220_##regname##_OFFS - \
132 QIB_7220_LBIntCnt_OFFS) / sizeof(u64))
134 #define cr_badformat CREG_IDX(RxVersionErrCnt)
135 #define cr_erricrc CREG_IDX(RxICRCErrCnt)
136 #define cr_errlink CREG_IDX(RxLinkMalformCnt)
137 #define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt)
138 #define cr_errpkey CREG_IDX(RxPKeyMismatchCnt)
139 #define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlViolCnt)
140 #define cr_err_rlen CREG_IDX(RxLenErrCnt)
141 #define cr_errslen CREG_IDX(TxLenErrCnt)
142 #define cr_errtidfull CREG_IDX(RxTIDFullErrCnt)
143 #define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt)
144 #define cr_errvcrc CREG_IDX(RxVCRCErrCnt)
145 #define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt)
146 #define cr_lbint CREG_IDX(LBIntCnt)
147 #define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
148 #define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt)
149 #define cr_lbflowstall CREG_IDX(LBFlowStallCnt)
150 #define cr_pktrcv CREG_IDX(RxDataPktCnt)
151 #define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
152 #define cr_pktsend CREG_IDX(TxDataPktCnt)
153 #define cr_pktsendflow CREG_IDX(TxFlowPktCnt)
154 #define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt)
155 #define cr_rcvebp CREG_IDX(RxEBPCnt)
156 #define cr_rcvovfl CREG_IDX(RxBufOvflCnt)
157 #define cr_senddropped CREG_IDX(TxDroppedPktCnt)
158 #define cr_sendstall CREG_IDX(TxFlowStallCnt)
159 #define cr_sendunderrun CREG_IDX(TxUnderrunCnt)
160 #define cr_wordrcv CREG_IDX(RxDwordCnt)
161 #define cr_wordsend CREG_IDX(TxDwordCnt)
162 #define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
163 #define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt)
164 #define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
165 #define cr_iblinkdown CREG_IDX(IBLinkDownedCnt)
166 #define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
167 #define cr_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
168 #define cr_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
169 #define cr_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
170 #define cr_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
171 #define cr_rxvlerr CREG_IDX(RxVlErrCnt)
172 #define cr_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
173 #define cr_psstat CREG_IDX(PSStat)
174 #define cr_psstart CREG_IDX(PSStart)
175 #define cr_psinterval CREG_IDX(PSInterval)
176 #define cr_psrcvdatacount CREG_IDX(PSRcvDataCount)
177 #define cr_psrcvpktscount CREG_IDX(PSRcvPktsCount)
178 #define cr_psxmitdatacount CREG_IDX(PSXmitDataCount)
179 #define cr_psxmitpktscount CREG_IDX(PSXmitPktsCount)
180 #define cr_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
181 #define cr_txsdmadesc CREG_IDX(TxSDmaDescCnt)
182 #define cr_pcieretrydiag CREG_IDX(PcieRetryBufDiagQwordCnt)
184 #define SYM_RMASK(regname, fldname) ((u64) \
185 QIB_7220_##regname##_##fldname##_RMASK)
186 #define SYM_MASK(regname, fldname) ((u64) \
187 QIB_7220_##regname##_##fldname##_RMASK << \
188 QIB_7220_##regname##_##fldname##_LSB)
189 #define SYM_LSB(regname, fldname) (QIB_7220_##regname##_##fldname##_LSB)
190 #define SYM_FIELD(value, regname, fldname) ((u64) \
191 (((value) >> SYM_LSB(regname, fldname)) & \
192 SYM_RMASK(regname, fldname)))
193 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
194 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
197 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
198 /* cycle through TS1/TS2 till OK */
199 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
200 /* wait for TS1, then go on */
201 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
202 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
204 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
205 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
206 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
208 #define BLOB_7220_IBCHG 0x81
211 * We could have a single register get/put routine, that takes a group type,
212 * but this is somewhat clearer and cleaner. It also gives us some error
213 * checking. 64 bit register reads should always work, but are inefficient
214 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
215 * so we use kreg32 wherever possible. User register and counter register
216 * reads are always 32 bit reads, so only one form of those routines.
220 * qib_read_ureg32 - read 32-bit virtualized per-context register
222 * @regno: register number
223 * @ctxt: context number
225 * Return the contents of a register that is virtualized to be per context.
226 * Returns -1 on errors (not distinguishable from valid contents at
227 * runtime; we may add a separate error variable at some point).
229 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
230 enum qib_ureg regno, int ctxt)
232 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
236 return readl(regno + (u64 __iomem *)
237 ((char __iomem *)dd->userbase +
238 dd->ureg_align * ctxt));
240 return readl(regno + (u64 __iomem *)
242 (char __iomem *)dd->kregbase +
243 dd->ureg_align * ctxt));
247 * qib_write_ureg - write 32-bit virtualized per-context register
249 * @regno: register number
253 * Write the contents of a register that is virtualized to be per context.
255 static inline void qib_write_ureg(const struct qib_devdata *dd,
256 enum qib_ureg regno, u64 value, int ctxt)
261 ubase = (u64 __iomem *)
262 ((char __iomem *) dd->userbase +
263 dd->ureg_align * ctxt);
265 ubase = (u64 __iomem *)
267 (char __iomem *) dd->kregbase +
268 dd->ureg_align * ctxt);
270 if (dd->kregbase && (dd->flags & QIB_PRESENT))
271 writeq(value, &ubase[regno]);
275 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
276 * @dd: the qlogic_ib device
277 * @regno: the register number to write
278 * @ctxt: the context containing the register
279 * @value: the value to write
281 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
282 const u16 regno, unsigned ctxt,
285 qib_write_kreg(dd, regno + ctxt, value);
288 static inline void write_7220_creg(const struct qib_devdata *dd,
289 u16 regno, u64 value)
291 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
292 writeq(value, &dd->cspec->cregbase[regno]);
295 static inline u64 read_7220_creg(const struct qib_devdata *dd, u16 regno)
297 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
299 return readq(&dd->cspec->cregbase[regno]);
302 static inline u32 read_7220_creg32(const struct qib_devdata *dd, u16 regno)
304 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
306 return readl(&dd->cspec->cregbase[regno]);
309 /* kr_revision bits */
310 #define QLOGIC_IB_R_EMULATORREV_MASK ((1ULL << 22) - 1)
311 #define QLOGIC_IB_R_EMULATORREV_SHIFT 40
313 /* kr_control bits */
314 #define QLOGIC_IB_C_RESET (1U << 7)
316 /* kr_intstatus, kr_intclear, kr_intmask bits */
317 #define QLOGIC_IB_I_RCVURG_MASK ((1ULL << 17) - 1)
318 #define QLOGIC_IB_I_RCVURG_SHIFT 32
319 #define QLOGIC_IB_I_RCVAVAIL_MASK ((1ULL << 17) - 1)
320 #define QLOGIC_IB_I_RCVAVAIL_SHIFT 0
321 #define QLOGIC_IB_I_SERDESTRIMDONE (1ULL << 27)
323 #define QLOGIC_IB_C_FREEZEMODE 0x00000002
324 #define QLOGIC_IB_C_LINKENABLE 0x00000004
326 #define QLOGIC_IB_I_SDMAINT 0x8000000000000000ULL
327 #define QLOGIC_IB_I_SDMADISABLED 0x4000000000000000ULL
328 #define QLOGIC_IB_I_ERROR 0x0000000080000000ULL
329 #define QLOGIC_IB_I_SPIOSENT 0x0000000040000000ULL
330 #define QLOGIC_IB_I_SPIOBUFAVAIL 0x0000000020000000ULL
331 #define QLOGIC_IB_I_GPIO 0x0000000010000000ULL
333 /* variables for sanity checking interrupt and errors */
334 #define QLOGIC_IB_I_BITSEXTANT \
335 (QLOGIC_IB_I_SDMAINT | QLOGIC_IB_I_SDMADISABLED | \
336 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \
337 (QLOGIC_IB_I_RCVAVAIL_MASK << \
338 QLOGIC_IB_I_RCVAVAIL_SHIFT) | \
339 QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \
340 QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO | \
341 QLOGIC_IB_I_SERDESTRIMDONE)
343 #define IB_HWE_BITSEXTANT \
344 (HWE_MASK(RXEMemParityErr) | \
345 HWE_MASK(TXEMemParityErr) | \
346 (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK << \
347 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) | \
348 QLOGIC_IB_HWE_PCIE1PLLFAILED | \
349 QLOGIC_IB_HWE_PCIE0PLLFAILED | \
350 QLOGIC_IB_HWE_PCIEPOISONEDTLP | \
351 QLOGIC_IB_HWE_PCIECPLTIMEOUT | \
352 QLOGIC_IB_HWE_PCIEBUSPARITYXTLH | \
353 QLOGIC_IB_HWE_PCIEBUSPARITYXADM | \
354 QLOGIC_IB_HWE_PCIEBUSPARITYRADM | \
355 HWE_MASK(PowerOnBISTFailed) | \
356 QLOGIC_IB_HWE_COREPLL_FBSLIP | \
357 QLOGIC_IB_HWE_COREPLL_RFSLIP | \
358 QLOGIC_IB_HWE_SERDESPLLFAILED | \
359 HWE_MASK(IBCBusToSPCParityErr) | \
360 HWE_MASK(IBCBusFromSPCParityErr) | \
361 QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR | \
362 QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR | \
363 QLOGIC_IB_HWE_SDMAMEMREADERR | \
364 QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED | \
365 QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT | \
366 QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT | \
367 QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT | \
368 QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT | \
369 QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR | \
370 QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR | \
371 QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR | \
372 QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR)
374 #define IB_E_BITSEXTANT \
375 (ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) | \
376 ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) | \
377 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) | \
378 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \
379 ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) | \
380 ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) | \
381 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) | \
382 ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) | \
383 ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) | \
384 ERR_MASK(SendSpecialTriggerErr) | \
385 ERR_MASK(SDmaDisabledErr) | ERR_MASK(SendMinPktLenErr) | \
386 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnderRunErr) | \
387 ERR_MASK(SendPktLenErr) | ERR_MASK(SendDroppedSmpPktErr) | \
388 ERR_MASK(SendDroppedDataPktErr) | \
389 ERR_MASK(SendPioArmLaunchErr) | \
390 ERR_MASK(SendUnexpectedPktNumErr) | \
391 ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(SendBufMisuseErr) | \
392 ERR_MASK(SDmaGenMismatchErr) | ERR_MASK(SDmaOutOfBoundErr) | \
393 ERR_MASK(SDmaTailOutOfBoundErr) | ERR_MASK(SDmaBaseErr) | \
394 ERR_MASK(SDma1stDescErr) | ERR_MASK(SDmaRpyTagErr) | \
395 ERR_MASK(SDmaDwEnErr) | ERR_MASK(SDmaMissingDwErr) | \
396 ERR_MASK(SDmaUnexpDataErr) | \
397 ERR_MASK(IBStatusChanged) | ERR_MASK(InvalidAddrErr) | \
398 ERR_MASK(ResetNegated) | ERR_MASK(HardwareErr) | \
399 ERR_MASK(SDmaDescAddrMisalignErr) | \
400 ERR_MASK(InvalidEEPCmd))
402 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
403 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK 0x00000000000000ffULL
404 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0
405 #define QLOGIC_IB_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
406 #define QLOGIC_IB_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
407 #define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
408 #define QLOGIC_IB_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
409 #define QLOGIC_IB_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
410 #define QLOGIC_IB_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
411 #define QLOGIC_IB_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
412 #define QLOGIC_IB_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
413 #define QLOGIC_IB_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
414 #define QLOGIC_IB_HWE_SERDESPLLFAILED 0x1000000000000000ULL
415 /* specific to this chip */
416 #define QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR 0x0000000000000040ULL
417 #define QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR 0x0000000000000080ULL
418 #define QLOGIC_IB_HWE_SDMAMEMREADERR 0x0000000010000000ULL
419 #define QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED 0x2000000000000000ULL
420 #define QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT 0x0100000000000000ULL
421 #define QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT 0x0200000000000000ULL
422 #define QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT 0x0400000000000000ULL
423 #define QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT 0x0800000000000000ULL
424 #define QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR 0x0000008000000000ULL
425 #define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL
426 #define QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR 0x0000001000000000ULL
427 #define QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR 0x0000002000000000ULL
429 #define IBA7220_IBCC_LINKCMD_SHIFT 19
431 /* kr_ibcddrctrl bits */
432 #define IBA7220_IBC_DLIDLMC_MASK 0xFFFFFFFFUL
433 #define IBA7220_IBC_DLIDLMC_SHIFT 32
435 #define IBA7220_IBC_HRTBT_MASK (SYM_RMASK(IBCDDRCtrl, HRTBT_AUTO) | \
436 SYM_RMASK(IBCDDRCtrl, HRTBT_ENB))
437 #define IBA7220_IBC_HRTBT_SHIFT SYM_LSB(IBCDDRCtrl, HRTBT_ENB)
439 #define IBA7220_IBC_LANE_REV_SUPPORTED (1<<8)
440 #define IBA7220_IBC_LREV_MASK 1
441 #define IBA7220_IBC_LREV_SHIFT 8
442 #define IBA7220_IBC_RXPOL_MASK 1
443 #define IBA7220_IBC_RXPOL_SHIFT 7
444 #define IBA7220_IBC_WIDTH_SHIFT 5
445 #define IBA7220_IBC_WIDTH_MASK 0x3
446 #define IBA7220_IBC_WIDTH_1X_ONLY (0 << IBA7220_IBC_WIDTH_SHIFT)
447 #define IBA7220_IBC_WIDTH_4X_ONLY (1 << IBA7220_IBC_WIDTH_SHIFT)
448 #define IBA7220_IBC_WIDTH_AUTONEG (2 << IBA7220_IBC_WIDTH_SHIFT)
449 #define IBA7220_IBC_SPEED_AUTONEG (1 << 1)
450 #define IBA7220_IBC_SPEED_SDR (1 << 2)
451 #define IBA7220_IBC_SPEED_DDR (1 << 3)
452 #define IBA7220_IBC_SPEED_AUTONEG_MASK (0x7 << 1)
453 #define IBA7220_IBC_IBTA_1_2_MASK (1)
455 /* kr_ibcddrstatus */
456 /* link latency shift is 0, don't bother defining */
457 #define IBA7220_DDRSTAT_LINKLAT_MASK 0x3ffffff
459 /* kr_extstatus bits */
460 #define QLOGIC_IB_EXTS_FREQSEL 0x2
461 #define QLOGIC_IB_EXTS_SERDESSEL 0x4
462 #define QLOGIC_IB_EXTS_MEMBIST_ENDTEST 0x0000000000004000
463 #define QLOGIC_IB_EXTS_MEMBIST_DISABLED 0x0000000000008000
465 /* kr_xgxsconfig bits */
466 #define QLOGIC_IB_XGXS_RESET 0x5ULL
467 #define QLOGIC_IB_XGXS_FC_SAFE (1ULL << 63)
469 /* kr_rcvpktledcnt */
470 #define IBA7220_LEDBLINK_ON_SHIFT 32 /* 4ns period on after packet */
471 #define IBA7220_LEDBLINK_OFF_SHIFT 0 /* 4ns period off before next on */
473 #define _QIB_GPIO_SDA_NUM 1
474 #define _QIB_GPIO_SCL_NUM 0
475 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7220 cards. */
476 #define QIB_TWSI_TEMP_DEV 0x98
478 /* HW counter clock is at 4nsec */
479 #define QIB_7220_PSXMITWAIT_CHECK_RATE 4000
481 #define IBA7220_R_INTRAVAIL_SHIFT 17
482 #define IBA7220_R_PKEY_DIS_SHIFT 34
483 #define IBA7220_R_TAILUPD_SHIFT 35
484 #define IBA7220_R_CTXTCFG_SHIFT 36
486 #define IBA7220_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
489 * the size bits give us 2^N, in KB units. 0 marks as invalid,
490 * and 7 is reserved. We currently use only 2KB and 4KB
492 #define IBA7220_TID_SZ_SHIFT 37 /* shift to 3bit size selector */
493 #define IBA7220_TID_SZ_2K (1UL << IBA7220_TID_SZ_SHIFT) /* 2KB */
494 #define IBA7220_TID_SZ_4K (2UL << IBA7220_TID_SZ_SHIFT) /* 4KB */
495 #define IBA7220_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
496 #define PBC_7220_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
497 #define PBC_7220_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
499 #define AUTONEG_TRIES 5 /* sequential retries to negotiate DDR */
501 /* packet rate matching delay multiplier */
502 static u8 rate_to_delay[2][2] = {
508 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
509 [IB_RATE_2_5_GBPS] = 8,
510 [IB_RATE_5_GBPS] = 4,
511 [IB_RATE_10_GBPS] = 2,
512 [IB_RATE_20_GBPS] = 1
515 #define IBA7220_LINKSPEED_SHIFT SYM_LSB(IBCStatus, LinkSpeedActive)
516 #define IBA7220_LINKWIDTH_SHIFT SYM_LSB(IBCStatus, LinkWidthActive)
518 /* link training states, from IBC */
519 #define IB_7220_LT_STATE_DISABLED 0x00
520 #define IB_7220_LT_STATE_LINKUP 0x01
521 #define IB_7220_LT_STATE_POLLACTIVE 0x02
522 #define IB_7220_LT_STATE_POLLQUIET 0x03
523 #define IB_7220_LT_STATE_SLEEPDELAY 0x04
524 #define IB_7220_LT_STATE_SLEEPQUIET 0x05
525 #define IB_7220_LT_STATE_CFGDEBOUNCE 0x08
526 #define IB_7220_LT_STATE_CFGRCVFCFG 0x09
527 #define IB_7220_LT_STATE_CFGWAITRMT 0x0a
528 #define IB_7220_LT_STATE_CFGIDLE 0x0b
529 #define IB_7220_LT_STATE_RECOVERRETRAIN 0x0c
530 #define IB_7220_LT_STATE_RECOVERWAITRMT 0x0e
531 #define IB_7220_LT_STATE_RECOVERIDLE 0x0f
533 /* link state machine states from IBC */
534 #define IB_7220_L_STATE_DOWN 0x0
535 #define IB_7220_L_STATE_INIT 0x1
536 #define IB_7220_L_STATE_ARM 0x2
537 #define IB_7220_L_STATE_ACTIVE 0x3
538 #define IB_7220_L_STATE_ACT_DEFER 0x4
540 static const u8 qib_7220_physportstate[0x20] = {
541 [IB_7220_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
542 [IB_7220_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
543 [IB_7220_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
544 [IB_7220_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
545 [IB_7220_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
546 [IB_7220_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
547 [IB_7220_LT_STATE_CFGDEBOUNCE] =
548 IB_PHYSPORTSTATE_CFG_TRAIN,
549 [IB_7220_LT_STATE_CFGRCVFCFG] =
550 IB_PHYSPORTSTATE_CFG_TRAIN,
551 [IB_7220_LT_STATE_CFGWAITRMT] =
552 IB_PHYSPORTSTATE_CFG_TRAIN,
553 [IB_7220_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_TRAIN,
554 [IB_7220_LT_STATE_RECOVERRETRAIN] =
555 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
556 [IB_7220_LT_STATE_RECOVERWAITRMT] =
557 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
558 [IB_7220_LT_STATE_RECOVERIDLE] =
559 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
560 [0x10] = IB_PHYSPORTSTATE_CFG_TRAIN,
561 [0x11] = IB_PHYSPORTSTATE_CFG_TRAIN,
562 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
563 [0x13] = IB_PHYSPORTSTATE_CFG_TRAIN,
564 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
565 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
566 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
567 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
570 int qib_special_trigger;
571 module_param_named(special_trigger, qib_special_trigger, int, S_IRUGO);
572 MODULE_PARM_DESC(special_trigger, "Enable SpecialTrigger arm/launch");
574 #define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr)
575 #define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr)
577 #define SYM_MASK_BIT(regname, fldname, bit) ((u64) \
578 (1ULL << (SYM_LSB(regname, fldname) + (bit))))
580 #define TXEMEMPARITYERR_PIOBUF \
581 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0)
582 #define TXEMEMPARITYERR_PIOPBC \
583 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1)
584 #define TXEMEMPARITYERR_PIOLAUNCHFIFO \
585 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2)
587 #define RXEMEMPARITYERR_RCVBUF \
588 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0)
589 #define RXEMEMPARITYERR_LOOKUPQ \
590 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1)
591 #define RXEMEMPARITYERR_EXPTID \
592 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2)
593 #define RXEMEMPARITYERR_EAGERTID \
594 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3)
595 #define RXEMEMPARITYERR_FLAGBUF \
596 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4)
597 #define RXEMEMPARITYERR_DATAINFO \
598 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5)
599 #define RXEMEMPARITYERR_HDRINFO \
600 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6)
602 /* 7220 specific hardware errors... */
603 static const struct qib_hwerror_msgs qib_7220_hwerror_msgs[] = {
604 /* generic hardware errors */
605 QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR, "QIB2IB Parity"),
606 QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2QIB Parity"),
608 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF,
609 "TXE PIOBUF Memory Parity"),
610 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC,
611 "TXE PIOPBC Memory Parity"),
612 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO,
613 "TXE PIOLAUNCHFIFO Memory Parity"),
615 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF,
616 "RXE RCVBUF Memory Parity"),
617 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ,
618 "RXE LOOKUPQ Memory Parity"),
619 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID,
620 "RXE EAGERTID Memory Parity"),
621 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID,
622 "RXE EXPTID Memory Parity"),
623 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF,
624 "RXE FLAGBUF Memory Parity"),
625 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO,
626 "RXE DATAINFO Memory Parity"),
627 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO,
628 "RXE HDRINFO Memory Parity"),
630 /* chip-specific hardware errors */
631 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP,
632 "PCIe Poisoned TLP"),
633 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,
634 "PCIe completion timeout"),
636 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
637 * parity or memory parity error failures, because most likely we
638 * won't be able to talk to the core of the chip. Nonetheless, we
639 * might see them, if they are in parts of the PCIe core that aren't
642 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED,
644 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED,
646 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH,
647 "PCIe XTLH core parity"),
648 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM,
649 "PCIe ADM TX core parity"),
650 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM,
651 "PCIe ADM RX core parity"),
652 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED,
654 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR,
655 "PCIe cpl header queue"),
656 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR,
657 "PCIe cpl data queue"),
658 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SDMAMEMREADERR,
659 "Send DMA memory read"),
660 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED,
661 "uC PLL clock not locked"),
662 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT,
663 "PCIe serdes Q0 no clock"),
664 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT,
665 "PCIe serdes Q1 no clock"),
666 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT,
667 "PCIe serdes Q2 no clock"),
668 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT,
669 "PCIe serdes Q3 no clock"),
670 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR,
671 "DDS RXEQ memory parity"),
672 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR,
673 "IB uC memory parity"),
674 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR,
675 "PCIe uC oct0 memory parity"),
676 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR,
677 "PCIe uC oct1 memory parity"),
680 #define RXE_PARITY (RXEMEMPARITYERR_EAGERTID|RXEMEMPARITYERR_EXPTID)
682 #define QLOGIC_IB_E_PKTERRS (\
683 ERR_MASK(SendPktLenErr) | \
684 ERR_MASK(SendDroppedDataPktErr) | \
685 ERR_MASK(RcvVCRCErr) | \
686 ERR_MASK(RcvICRCErr) | \
687 ERR_MASK(RcvShortPktLenErr) | \
690 /* Convenience for decoding Send DMA errors */
691 #define QLOGIC_IB_E_SDMAERRS ( \
692 ERR_MASK(SDmaGenMismatchErr) | \
693 ERR_MASK(SDmaOutOfBoundErr) | \
694 ERR_MASK(SDmaTailOutOfBoundErr) | ERR_MASK(SDmaBaseErr) | \
695 ERR_MASK(SDma1stDescErr) | ERR_MASK(SDmaRpyTagErr) | \
696 ERR_MASK(SDmaDwEnErr) | ERR_MASK(SDmaMissingDwErr) | \
697 ERR_MASK(SDmaUnexpDataErr) | \
698 ERR_MASK(SDmaDescAddrMisalignErr) | \
699 ERR_MASK(SDmaDisabledErr) | \
700 ERR_MASK(SendBufMisuseErr))
702 /* These are all rcv-related errors which we want to count for stats */
703 #define E_SUM_PKTERRS \
704 (ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) | \
705 ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) | \
706 ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) | \
707 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
708 ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) | \
709 ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr))
711 /* These are all send-related errors which we want to count for stats */
713 (ERR_MASK(SendPioArmLaunchErr) | ERR_MASK(SendUnexpectedPktNumErr) | \
714 ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
715 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) | \
716 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
717 ERR_MASK(InvalidAddrErr))
720 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
721 * errors not related to freeze and cancelling buffers. Can't ignore
722 * armlaunch because could get more while still cleaning up, and need
723 * to cancel those as they happen.
725 #define E_SPKT_ERRS_IGNORE \
726 (ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
727 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) | \
728 ERR_MASK(SendPktLenErr))
731 * these are errors that can occur when the link changes state while
732 * a packet is being sent or received. This doesn't cover things
733 * like EBP or VCRC that can be the result of a sending having the
734 * link change state, so we receive a "known bad" packet.
736 #define E_SUM_LINK_PKTERRS \
737 (ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
738 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
739 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
740 ERR_MASK(RcvUnexpectedCharErr))
742 static void autoneg_7220_work(struct work_struct *);
743 static u32 __iomem *qib_7220_getsendbuf(struct qib_pportdata *, u64, u32 *);
746 * Called when we might have an error that is specific to a particular
747 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
748 * because we don't need to force the update of pioavail.
750 static void qib_disarm_7220_senderrbufs(struct qib_pportdata *ppd)
752 unsigned long sbuf[3];
753 struct qib_devdata *dd = ppd->dd;
756 * It's possible that sendbuffererror could have bits set; might
757 * have already done this as a result of hardware error handling.
759 /* read these before writing errorclear */
760 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
761 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
762 sbuf[2] = qib_read_kreg64(dd, kr_sendbuffererror + 2);
764 if (sbuf[0] || sbuf[1] || sbuf[2])
765 qib_disarm_piobufs_set(dd, sbuf,
766 dd->piobcnt2k + dd->piobcnt4k);
769 static void qib_7220_txe_recover(struct qib_devdata *dd)
771 qib_devinfo(dd->pcidev, "Recovering from TXE PIO parity error\n");
772 qib_disarm_7220_senderrbufs(dd->pport);
776 * This is called with interrupts disabled and sdma_lock held.
778 static void qib_7220_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
780 struct qib_devdata *dd = ppd->dd;
781 u64 set_sendctrl = 0;
782 u64 clr_sendctrl = 0;
784 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
785 set_sendctrl |= SYM_MASK(SendCtrl, SDmaEnable);
787 clr_sendctrl |= SYM_MASK(SendCtrl, SDmaEnable);
789 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
790 set_sendctrl |= SYM_MASK(SendCtrl, SDmaIntEnable);
792 clr_sendctrl |= SYM_MASK(SendCtrl, SDmaIntEnable);
794 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
795 set_sendctrl |= SYM_MASK(SendCtrl, SDmaHalt);
797 clr_sendctrl |= SYM_MASK(SendCtrl, SDmaHalt);
799 spin_lock(&dd->sendctrl_lock);
801 dd->sendctrl |= set_sendctrl;
802 dd->sendctrl &= ~clr_sendctrl;
804 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
805 qib_write_kreg(dd, kr_scratch, 0);
807 spin_unlock(&dd->sendctrl_lock);
810 static void qib_decode_7220_sdma_errs(struct qib_pportdata *ppd,
811 u64 err, char *buf, size_t blen)
813 static const struct {
817 { ERR_MASK(SDmaGenMismatchErr),
819 { ERR_MASK(SDmaOutOfBoundErr),
821 { ERR_MASK(SDmaTailOutOfBoundErr),
822 "SDmaTailOutOfBound" },
823 { ERR_MASK(SDmaBaseErr),
825 { ERR_MASK(SDma1stDescErr),
827 { ERR_MASK(SDmaRpyTagErr),
829 { ERR_MASK(SDmaDwEnErr),
831 { ERR_MASK(SDmaMissingDwErr),
833 { ERR_MASK(SDmaUnexpDataErr),
835 { ERR_MASK(SDmaDescAddrMisalignErr),
836 "SDmaDescAddrMisalign" },
837 { ERR_MASK(SendBufMisuseErr),
839 { ERR_MASK(SDmaDisabledErr),
845 for (i = 0; i < ARRAY_SIZE(errs); i++) {
846 if (err & errs[i].err)
847 bidx += scnprintf(buf + bidx, blen - bidx,
853 * This is called as part of link down clean up so disarm and flush
854 * all send buffers so that SMP packets can be sent.
856 static void qib_7220_sdma_hw_clean_up(struct qib_pportdata *ppd)
858 /* This will trigger the Abort interrupt */
859 sendctrl_7220_mod(ppd, QIB_SENDCTRL_DISARM_ALL | QIB_SENDCTRL_FLUSH |
860 QIB_SENDCTRL_AVAIL_BLIP);
861 ppd->dd->upd_pio_shadow = 1; /* update our idea of what's busy */
864 static void qib_sdma_7220_setlengen(struct qib_pportdata *ppd)
867 * Set SendDmaLenGen and clear and set
868 * the MSB of the generation count to enable generation checking
869 * and load the internal generation counter.
871 qib_write_kreg(ppd->dd, kr_senddmalengen, ppd->sdma_descq_cnt);
872 qib_write_kreg(ppd->dd, kr_senddmalengen,
873 ppd->sdma_descq_cnt |
874 (1ULL << QIB_7220_SendDmaLenGen_Generation_MSB));
877 static void qib_7220_sdma_hw_start_up(struct qib_pportdata *ppd)
879 qib_sdma_7220_setlengen(ppd);
880 qib_sdma_update_7220_tail(ppd, 0); /* Set SendDmaTail */
881 ppd->sdma_head_dma[0] = 0;
884 #define DISABLES_SDMA ( \
885 ERR_MASK(SDmaDisabledErr) | \
886 ERR_MASK(SDmaBaseErr) | \
887 ERR_MASK(SDmaTailOutOfBoundErr) | \
888 ERR_MASK(SDmaOutOfBoundErr) | \
889 ERR_MASK(SDma1stDescErr) | \
890 ERR_MASK(SDmaRpyTagErr) | \
891 ERR_MASK(SDmaGenMismatchErr) | \
892 ERR_MASK(SDmaDescAddrMisalignErr) | \
893 ERR_MASK(SDmaMissingDwErr) | \
894 ERR_MASK(SDmaDwEnErr))
896 static void sdma_7220_errors(struct qib_pportdata *ppd, u64 errs)
899 struct qib_devdata *dd = ppd->dd;
902 errs &= QLOGIC_IB_E_SDMAERRS;
904 msg = dd->cspec->sdmamsgbuf;
905 qib_decode_7220_sdma_errs(ppd, errs, msg, sizeof dd->cspec->sdmamsgbuf);
906 spin_lock_irqsave(&ppd->sdma_lock, flags);
908 if (errs & ERR_MASK(SendBufMisuseErr)) {
909 unsigned long sbuf[3];
911 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
912 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
913 sbuf[2] = qib_read_kreg64(dd, kr_sendbuffererror + 2);
916 "IB%u:%u SendBufMisuse: %04lx %016lx %016lx\n",
917 ppd->dd->unit, ppd->port, sbuf[2], sbuf[1],
921 if (errs & ERR_MASK(SDmaUnexpDataErr))
922 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", ppd->dd->unit,
925 switch (ppd->sdma_state.current_state) {
926 case qib_sdma_state_s00_hw_down:
927 /* not expecting any interrupts */
930 case qib_sdma_state_s10_hw_start_up_wait:
931 /* handled in intr path */
934 case qib_sdma_state_s20_idle:
935 /* not expecting any interrupts */
938 case qib_sdma_state_s30_sw_clean_up_wait:
939 /* not expecting any interrupts */
942 case qib_sdma_state_s40_hw_clean_up_wait:
943 if (errs & ERR_MASK(SDmaDisabledErr))
944 __qib_sdma_process_event(ppd,
945 qib_sdma_event_e50_hw_cleaned);
948 case qib_sdma_state_s50_hw_halt_wait:
949 /* handled in intr path */
952 case qib_sdma_state_s99_running:
953 if (errs & DISABLES_SDMA)
954 __qib_sdma_process_event(ppd,
955 qib_sdma_event_e7220_err_halted);
959 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
963 * Decode the error status into strings, deciding whether to always
964 * print * it or not depending on "normal packet errors" vs everything
965 * else. Return 1 if "real" errors, otherwise 0 if only packet
966 * errors, so caller can decide what to print with the string.
968 static int qib_decode_7220_err(struct qib_devdata *dd, char *buf, size_t blen,
974 if (err & QLOGIC_IB_E_PKTERRS) {
975 if (!(err & ~QLOGIC_IB_E_PKTERRS))
977 if ((err & ERR_MASK(RcvICRCErr)) &&
978 !(err & (ERR_MASK(RcvVCRCErr) | ERR_MASK(RcvEBPErr))))
979 strlcat(buf, "CRC ", blen);
983 if (err & ERR_MASK(RcvHdrLenErr))
984 strlcat(buf, "rhdrlen ", blen);
985 if (err & ERR_MASK(RcvBadTidErr))
986 strlcat(buf, "rbadtid ", blen);
987 if (err & ERR_MASK(RcvBadVersionErr))
988 strlcat(buf, "rbadversion ", blen);
989 if (err & ERR_MASK(RcvHdrErr))
990 strlcat(buf, "rhdr ", blen);
991 if (err & ERR_MASK(SendSpecialTriggerErr))
992 strlcat(buf, "sendspecialtrigger ", blen);
993 if (err & ERR_MASK(RcvLongPktLenErr))
994 strlcat(buf, "rlongpktlen ", blen);
995 if (err & ERR_MASK(RcvMaxPktLenErr))
996 strlcat(buf, "rmaxpktlen ", blen);
997 if (err & ERR_MASK(RcvMinPktLenErr))
998 strlcat(buf, "rminpktlen ", blen);
999 if (err & ERR_MASK(SendMinPktLenErr))
1000 strlcat(buf, "sminpktlen ", blen);
1001 if (err & ERR_MASK(RcvFormatErr))
1002 strlcat(buf, "rformaterr ", blen);
1003 if (err & ERR_MASK(RcvUnsupportedVLErr))
1004 strlcat(buf, "runsupvl ", blen);
1005 if (err & ERR_MASK(RcvUnexpectedCharErr))
1006 strlcat(buf, "runexpchar ", blen);
1007 if (err & ERR_MASK(RcvIBFlowErr))
1008 strlcat(buf, "ribflow ", blen);
1009 if (err & ERR_MASK(SendUnderRunErr))
1010 strlcat(buf, "sunderrun ", blen);
1011 if (err & ERR_MASK(SendPioArmLaunchErr))
1012 strlcat(buf, "spioarmlaunch ", blen);
1013 if (err & ERR_MASK(SendUnexpectedPktNumErr))
1014 strlcat(buf, "sunexperrpktnum ", blen);
1015 if (err & ERR_MASK(SendDroppedSmpPktErr))
1016 strlcat(buf, "sdroppedsmppkt ", blen);
1017 if (err & ERR_MASK(SendMaxPktLenErr))
1018 strlcat(buf, "smaxpktlen ", blen);
1019 if (err & ERR_MASK(SendUnsupportedVLErr))
1020 strlcat(buf, "sunsupVL ", blen);
1021 if (err & ERR_MASK(InvalidAddrErr))
1022 strlcat(buf, "invalidaddr ", blen);
1023 if (err & ERR_MASK(RcvEgrFullErr))
1024 strlcat(buf, "rcvegrfull ", blen);
1025 if (err & ERR_MASK(RcvHdrFullErr))
1026 strlcat(buf, "rcvhdrfull ", blen);
1027 if (err & ERR_MASK(IBStatusChanged))
1028 strlcat(buf, "ibcstatuschg ", blen);
1029 if (err & ERR_MASK(RcvIBLostLinkErr))
1030 strlcat(buf, "riblostlink ", blen);
1031 if (err & ERR_MASK(HardwareErr))
1032 strlcat(buf, "hardware ", blen);
1033 if (err & ERR_MASK(ResetNegated))
1034 strlcat(buf, "reset ", blen);
1035 if (err & QLOGIC_IB_E_SDMAERRS)
1036 qib_decode_7220_sdma_errs(dd->pport, err, buf, blen);
1037 if (err & ERR_MASK(InvalidEEPCmd))
1038 strlcat(buf, "invalideepromcmd ", blen);
1043 static void reenable_7220_chase(unsigned long opaque)
1045 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1046 ppd->cpspec->chase_timer.expires = 0;
1047 qib_set_ib_7220_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1048 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1051 static void handle_7220_chase(struct qib_pportdata *ppd, u64 ibcst)
1056 ibclt = (u8)SYM_FIELD(ibcst, IBCStatus, LinkTrainingState);
1059 * Detect and handle the state chase issue, where we can
1060 * get stuck if we are unlucky on timing on both sides of
1061 * the link. If we are, we disable, set a timer, and
1065 case IB_7220_LT_STATE_CFGRCVFCFG:
1066 case IB_7220_LT_STATE_CFGWAITRMT:
1067 case IB_7220_LT_STATE_TXREVLANES:
1068 case IB_7220_LT_STATE_CFGENH:
1070 if (ppd->cpspec->chase_end &&
1071 time_after(tnow, ppd->cpspec->chase_end)) {
1072 ppd->cpspec->chase_end = 0;
1073 qib_set_ib_7220_lstate(ppd,
1074 QLOGIC_IB_IBCC_LINKCMD_DOWN,
1075 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1076 ppd->cpspec->chase_timer.expires = jiffies +
1078 add_timer(&ppd->cpspec->chase_timer);
1079 } else if (!ppd->cpspec->chase_end)
1080 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1084 ppd->cpspec->chase_end = 0;
1089 static void handle_7220_errors(struct qib_devdata *dd, u64 errs)
1092 u64 ignore_this_time = 0;
1095 struct qib_pportdata *ppd = dd->pport;
1098 /* don't report errors that are masked */
1099 errs &= dd->cspec->errormask;
1100 msg = dd->cspec->emsgbuf;
1102 /* do these first, they are most important */
1103 if (errs & ERR_MASK(HardwareErr))
1104 qib_7220_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1106 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1107 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1108 qib_inc_eeprom_err(dd, log_idx, 1);
1110 if (errs & QLOGIC_IB_E_SDMAERRS)
1111 sdma_7220_errors(ppd, errs);
1113 if (errs & ~IB_E_BITSEXTANT)
1114 qib_dev_err(dd, "error interrupt with unknown errors "
1115 "%llx set\n", (unsigned long long)
1116 (errs & ~IB_E_BITSEXTANT));
1118 if (errs & E_SUM_ERRS) {
1119 qib_disarm_7220_senderrbufs(ppd);
1120 if ((errs & E_SUM_LINK_PKTERRS) &&
1121 !(ppd->lflags & QIBL_LINKACTIVE)) {
1123 * This can happen when trying to bring the link
1124 * up, but the IB link changes state at the "wrong"
1125 * time. The IB logic then complains that the packet
1126 * isn't valid. We don't want to confuse people, so
1127 * we just don't print them, except at debug
1129 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1131 } else if ((errs & E_SUM_LINK_PKTERRS) &&
1132 !(ppd->lflags & QIBL_LINKACTIVE)) {
1134 * This can happen when SMA is trying to bring the link
1135 * up, but the IB link changes state at the "wrong" time.
1136 * The IB logic then complains that the packet isn't
1137 * valid. We don't want to confuse people, so we just
1138 * don't print them, except at debug
1140 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1143 qib_write_kreg(dd, kr_errclear, errs);
1145 errs &= ~ignore_this_time;
1150 * The ones we mask off are handled specially below
1151 * or above. Also mask SDMADISABLED by default as it
1154 mask = ERR_MASK(IBStatusChanged) |
1155 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) |
1156 ERR_MASK(HardwareErr) | ERR_MASK(SDmaDisabledErr);
1158 qib_decode_7220_err(dd, msg, sizeof dd->cspec->emsgbuf, errs & ~mask);
1160 if (errs & E_SUM_PKTERRS)
1161 qib_stats.sps_rcverrs++;
1162 if (errs & E_SUM_ERRS)
1163 qib_stats.sps_txerrs++;
1164 iserr = errs & ~(E_SUM_PKTERRS | QLOGIC_IB_E_PKTERRS |
1165 ERR_MASK(SDmaDisabledErr));
1167 if (errs & ERR_MASK(IBStatusChanged)) {
1170 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1171 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1172 handle_7220_chase(ppd, ibcs);
1174 /* Update our picture of width and speed from chip */
1175 ppd->link_width_active =
1176 ((ibcs >> IBA7220_LINKWIDTH_SHIFT) & 1) ?
1177 IB_WIDTH_4X : IB_WIDTH_1X;
1178 ppd->link_speed_active =
1179 ((ibcs >> IBA7220_LINKSPEED_SHIFT) & 1) ?
1180 QIB_IB_DDR : QIB_IB_SDR;
1183 * Since going into a recovery state causes the link state
1184 * to go down and since recovery is transitory, it is better
1185 * if we "miss" ever seeing the link training state go into
1186 * recovery (i.e., ignore this transition for link state
1187 * special handling purposes) without updating lastibcstat.
1189 if (qib_7220_phys_portstate(ibcs) !=
1190 IB_PHYSPORTSTATE_LINK_ERR_RECOVER)
1191 qib_handle_e_ibstatuschanged(ppd, ibcs);
1194 if (errs & ERR_MASK(ResetNegated)) {
1195 qib_dev_err(dd, "Got reset, requires re-init "
1196 "(unload and reload driver)\n");
1197 dd->flags &= ~QIB_INITTED; /* needs re-init */
1198 /* mark as having had error */
1199 *dd->devstatusp |= QIB_STATUS_HWERROR;
1200 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF;
1204 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1206 if (ppd->state_wanted & ppd->lflags)
1207 wake_up_interruptible(&ppd->state_wait);
1210 * If there were hdrq or egrfull errors, wake up any processes
1211 * waiting in poll. We used to try to check which contexts had
1212 * the overflow, but given the cost of that and the chip reads
1213 * to support it, it's better to just wake everybody up if we
1214 * get an overflow; waiters can poll again if it's not them.
1216 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1217 qib_handle_urcv(dd, ~0U);
1218 if (errs & ERR_MASK(RcvEgrFullErr))
1219 qib_stats.sps_buffull++;
1221 qib_stats.sps_hdrfull++;
1227 /* enable/disable chip from delivering interrupts */
1228 static void qib_7220_set_intr_state(struct qib_devdata *dd, u32 enable)
1231 if (dd->flags & QIB_BADINTR)
1233 qib_write_kreg(dd, kr_intmask, ~0ULL);
1234 /* force re-interrupt of any pending interrupts. */
1235 qib_write_kreg(dd, kr_intclear, 0ULL);
1237 qib_write_kreg(dd, kr_intmask, 0ULL);
1241 * Try to cleanup as much as possible for anything that might have gone
1242 * wrong while in freeze mode, such as pio buffers being written by user
1243 * processes (causing armlaunch), send errors due to going into freeze mode,
1244 * etc., and try to avoid causing extra interrupts while doing so.
1245 * Forcibly update the in-memory pioavail register copies after cleanup
1246 * because the chip won't do it while in freeze mode (the register values
1247 * themselves are kept correct).
1248 * Make sure that we don't lose any important interrupts by using the chip
1249 * feature that says that writing 0 to a bit in *clear that is set in
1250 * *status will cause an interrupt to be generated again (if allowed by
1252 * This is in chip-specific code because of all of the register accesses,
1253 * even though the details are similar on most chips.
1255 static void qib_7220_clear_freeze(struct qib_devdata *dd)
1257 /* disable error interrupts, to avoid confusion */
1258 qib_write_kreg(dd, kr_errmask, 0ULL);
1260 /* also disable interrupts; errormask is sometimes overwriten */
1261 qib_7220_set_intr_state(dd, 0);
1263 qib_cancel_sends(dd->pport);
1265 /* clear the freeze, and be sure chip saw it */
1266 qib_write_kreg(dd, kr_control, dd->control);
1267 qib_read_kreg32(dd, kr_scratch);
1269 /* force in-memory update now we are out of freeze */
1270 qib_force_pio_avail_update(dd);
1273 * force new interrupt if any hwerr, error or interrupt bits are
1274 * still set, and clear "safe" send packet errors related to freeze
1275 * and cancelling sends. Re-enable error interrupts before possible
1276 * force of re-interrupt on pending interrupts.
1278 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1279 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1280 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1281 qib_7220_set_intr_state(dd, 1);
1285 * qib_7220_handle_hwerrors - display hardware errors.
1286 * @dd: the qlogic_ib device
1287 * @msg: the output buffer
1288 * @msgl: the size of the output buffer
1290 * Use same msg buffer as regular errors to avoid excessive stack
1291 * use. Most hardware errors are catastrophic, but for right now,
1292 * we'll print them and continue. We reuse the same message buffer as
1293 * handle_7220_errors() to avoid excessive stack usage.
1295 static void qib_7220_handle_hwerrors(struct qib_devdata *dd, char *msg,
1304 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
1307 if (hwerrs == ~0ULL) {
1308 qib_dev_err(dd, "Read of hardware error status failed "
1309 "(all bits set); ignoring\n");
1312 qib_stats.sps_hwerrs++;
1315 * Always clear the error status register, except MEMBISTFAIL,
1316 * regardless of whether we continue or stop using the chip.
1317 * We want that set so we know it failed, even across driver reload.
1318 * We'll still ignore it in the hwerrmask. We do this partly for
1319 * diagnostics, but also for support.
1321 qib_write_kreg(dd, kr_hwerrclear,
1322 hwerrs & ~HWE_MASK(PowerOnBISTFailed));
1324 hwerrs &= dd->cspec->hwerrmask;
1326 /* We log some errors to EEPROM, check if we have any of those. */
1327 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1328 if (hwerrs & dd->eep_st_masks[log_idx].hwerrs_to_log)
1329 qib_inc_eeprom_err(dd, log_idx, 1);
1330 if (hwerrs & ~(TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC |
1332 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
1333 "(cleared)\n", (unsigned long long) hwerrs);
1335 if (hwerrs & ~IB_HWE_BITSEXTANT)
1336 qib_dev_err(dd, "hwerror interrupt with unknown errors "
1337 "%llx set\n", (unsigned long long)
1338 (hwerrs & ~IB_HWE_BITSEXTANT));
1340 if (hwerrs & QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR)
1341 qib_sd7220_clr_ibpar(dd);
1343 ctrl = qib_read_kreg32(dd, kr_control);
1344 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) {
1346 * Parity errors in send memory are recoverable by h/w
1347 * just do housekeeping, exit freeze mode and continue.
1349 if (hwerrs & (TXEMEMPARITYERR_PIOBUF |
1350 TXEMEMPARITYERR_PIOPBC)) {
1351 qib_7220_txe_recover(dd);
1352 hwerrs &= ~(TXEMEMPARITYERR_PIOBUF |
1353 TXEMEMPARITYERR_PIOPBC);
1358 qib_7220_clear_freeze(dd);
1363 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
1365 strlcat(msg, "[Memory BIST test failed, "
1366 "InfiniPath hardware unusable]", msgl);
1367 /* ignore from now on, so disable until driver reloaded */
1368 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
1369 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1372 qib_format_hwerrors(hwerrs, qib_7220_hwerror_msgs,
1373 ARRAY_SIZE(qib_7220_hwerror_msgs), msg, msgl);
1375 bitsmsg = dd->cspec->bitsmsgbuf;
1376 if (hwerrs & (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<
1377 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT)) {
1378 bits = (u32) ((hwerrs >>
1379 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) &
1380 QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK);
1381 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
1382 "[PCIe Mem Parity Errs %x] ", bits);
1383 strlcat(msg, bitsmsg, msgl);
1386 #define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP | \
1387 QLOGIC_IB_HWE_COREPLL_RFSLIP)
1389 if (hwerrs & _QIB_PLL_FAIL) {
1391 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
1392 "[PLL failed (%llx), InfiniPath hardware unusable]",
1393 (unsigned long long) hwerrs & _QIB_PLL_FAIL);
1394 strlcat(msg, bitsmsg, msgl);
1395 /* ignore from now on, so disable until driver reloaded */
1396 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
1397 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1400 if (hwerrs & QLOGIC_IB_HWE_SERDESPLLFAILED) {
1402 * If it occurs, it is left masked since the eternal
1403 * interface is unused.
1405 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
1406 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1409 qib_dev_err(dd, "%s hardware error\n", msg);
1411 if (isfatal && !dd->diag_client) {
1412 qib_dev_err(dd, "Fatal Hardware Error, no longer"
1413 " usable, SN %.16s\n", dd->serial);
1415 * For /sys status file and user programs to print; if no
1416 * trailing brace is copied, we'll know it was truncated.
1419 snprintf(dd->freezemsg, dd->freezelen,
1421 qib_disable_after_error(dd);
1427 * qib_7220_init_hwerrors - enable hardware errors
1428 * @dd: the qlogic_ib device
1430 * now that we have finished initializing everything that might reasonably
1431 * cause a hardware error, and cleared those errors bits as they occur,
1432 * we can enable hardware errors in the mask (potentially enabling
1433 * freeze mode), and enable hardware errors as errors (along with
1434 * everything else) in errormask
1436 static void qib_7220_init_hwerrors(struct qib_devdata *dd)
1441 extsval = qib_read_kreg64(dd, kr_extstatus);
1443 if (!(extsval & (QLOGIC_IB_EXTS_MEMBIST_ENDTEST |
1444 QLOGIC_IB_EXTS_MEMBIST_DISABLED)))
1445 qib_dev_err(dd, "MemBIST did not complete!\n");
1446 if (extsval & QLOGIC_IB_EXTS_MEMBIST_DISABLED)
1447 qib_devinfo(dd->pcidev, "MemBIST is disabled.\n");
1449 val = ~0ULL; /* default to all hwerrors become interrupts, */
1451 val &= ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR;
1452 dd->cspec->hwerrmask = val;
1454 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
1455 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1458 qib_write_kreg(dd, kr_errclear, ~0ULL);
1459 /* enable errors that are masked, at least this first time. */
1460 qib_write_kreg(dd, kr_errmask, ~0ULL);
1461 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1462 /* clear any interrupts up to this point (ints still not enabled) */
1463 qib_write_kreg(dd, kr_intclear, ~0ULL);
1467 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
1468 * on chips that are count-based, rather than trigger-based. There is no
1469 * reference counting, but that's also fine, given the intended use.
1470 * Only chip-specific because it's all register accesses
1472 static void qib_set_7220_armlaunch(struct qib_devdata *dd, u32 enable)
1475 qib_write_kreg(dd, kr_errclear, ERR_MASK(SendPioArmLaunchErr));
1476 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1478 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1479 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1483 * Formerly took parameter <which> in pre-shifted,
1484 * pre-merged form with LinkCmd and LinkInitCmd
1485 * together, and assuming the zero was NOP.
1487 static void qib_set_ib_7220_lstate(struct qib_pportdata *ppd, u16 linkcmd,
1491 struct qib_devdata *dd = ppd->dd;
1492 unsigned long flags;
1494 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
1496 * If we are told to disable, note that so link-recovery
1497 * code does not attempt to bring us back up.
1499 spin_lock_irqsave(&ppd->lflags_lock, flags);
1500 ppd->lflags |= QIBL_IB_LINK_DISABLED;
1501 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1502 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
1504 * Any other linkinitcmd will lead to LINKDOWN and then
1505 * to INIT (if all is well), so clear flag to let
1506 * link-recovery code attempt to bring us back up.
1508 spin_lock_irqsave(&ppd->lflags_lock, flags);
1509 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
1510 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1513 mod_wd = (linkcmd << IBA7220_IBCC_LINKCMD_SHIFT) |
1514 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1516 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl | mod_wd);
1517 /* write to chip to prevent back-to-back writes of ibc reg */
1518 qib_write_kreg(dd, kr_scratch, 0);
1522 * All detailed interaction with the SerDes has been moved to qib_sd7220.c
1524 * The portion of IBA7220-specific bringup_serdes() that actually deals with
1525 * registers and memory within the SerDes itself is qib_sd7220_init().
1529 * qib_7220_bringup_serdes - bring up the serdes
1530 * @ppd: physical port on the qlogic_ib device
1532 static int qib_7220_bringup_serdes(struct qib_pportdata *ppd)
1534 struct qib_devdata *dd = ppd->dd;
1535 u64 val, prev_val, guid, ibc;
1538 /* Put IBC in reset, sends disabled */
1539 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1540 qib_write_kreg(dd, kr_control, 0ULL);
1542 if (qib_compat_ddr_negotiate) {
1543 ppd->cpspec->ibdeltainprog = 1;
1544 ppd->cpspec->ibsymsnap = read_7220_creg32(dd, cr_ibsymbolerr);
1545 ppd->cpspec->iblnkerrsnap =
1546 read_7220_creg32(dd, cr_iblinkerrrecov);
1549 /* flowcontrolwatermark is in units of KBytes */
1550 ibc = 0x5ULL << SYM_LSB(IBCCtrl, FlowCtrlWaterMark);
1552 * How often flowctrl sent. More or less in usecs; balance against
1553 * watermark value, so that in theory senders always get a flow
1554 * control update in time to not let the IB link go idle.
1556 ibc |= 0x3ULL << SYM_LSB(IBCCtrl, FlowCtrlPeriod);
1557 /* max error tolerance */
1558 ibc |= 0xfULL << SYM_LSB(IBCCtrl, PhyerrThreshold);
1559 /* use "real" buffer space for */
1560 ibc |= 4ULL << SYM_LSB(IBCCtrl, CreditScale);
1561 /* IB credit flow control. */
1562 ibc |= 0xfULL << SYM_LSB(IBCCtrl, OverrunThreshold);
1564 * set initial max size pkt IBC will send, including ICRC; it's the
1565 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
1567 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen);
1568 ppd->cpspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */
1570 /* initially come up waiting for TS1, without sending anything. */
1571 val = ppd->cpspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
1572 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1573 qib_write_kreg(dd, kr_ibcctrl, val);
1575 if (!ppd->cpspec->ibcddrctrl) {
1576 /* not on re-init after reset */
1577 ppd->cpspec->ibcddrctrl = qib_read_kreg64(dd, kr_ibcddrctrl);
1579 if (ppd->link_speed_enabled == (QIB_IB_SDR | QIB_IB_DDR))
1580 ppd->cpspec->ibcddrctrl |=
1581 IBA7220_IBC_SPEED_AUTONEG_MASK |
1582 IBA7220_IBC_IBTA_1_2_MASK;
1584 ppd->cpspec->ibcddrctrl |=
1585 ppd->link_speed_enabled == QIB_IB_DDR ?
1586 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
1587 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
1588 (IB_WIDTH_1X | IB_WIDTH_4X))
1589 ppd->cpspec->ibcddrctrl |= IBA7220_IBC_WIDTH_AUTONEG;
1591 ppd->cpspec->ibcddrctrl |=
1592 ppd->link_width_enabled == IB_WIDTH_4X ?
1593 IBA7220_IBC_WIDTH_4X_ONLY :
1594 IBA7220_IBC_WIDTH_1X_ONLY;
1596 /* always enable these on driver reload, not sticky */
1597 ppd->cpspec->ibcddrctrl |=
1598 IBA7220_IBC_RXPOL_MASK << IBA7220_IBC_RXPOL_SHIFT;
1599 ppd->cpspec->ibcddrctrl |=
1600 IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
1602 /* enable automatic lane reversal detection for receive */
1603 ppd->cpspec->ibcddrctrl |= IBA7220_IBC_LANE_REV_SUPPORTED;
1605 /* write to chip to prevent back-to-back writes of ibc reg */
1606 qib_write_kreg(dd, kr_scratch, 0);
1608 qib_write_kreg(dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
1609 qib_write_kreg(dd, kr_scratch, 0);
1611 qib_write_kreg(dd, kr_ncmodectrl, 0Ull);
1612 qib_write_kreg(dd, kr_scratch, 0);
1614 ret = qib_sd7220_init(dd);
1616 val = qib_read_kreg64(dd, kr_xgxs_cfg);
1618 val |= QLOGIC_IB_XGXS_FC_SAFE;
1619 if (val != prev_val) {
1620 qib_write_kreg(dd, kr_xgxs_cfg, val);
1621 qib_read_kreg32(dd, kr_scratch);
1623 if (val & QLOGIC_IB_XGXS_RESET)
1624 val &= ~QLOGIC_IB_XGXS_RESET;
1625 if (val != prev_val)
1626 qib_write_kreg(dd, kr_xgxs_cfg, val);
1628 /* first time through, set port guid */
1630 ppd->guid = dd->base_guid;
1631 guid = be64_to_cpu(ppd->guid);
1633 qib_write_kreg(dd, kr_hrtbt_guid, guid);
1635 dd->control |= QLOGIC_IB_C_LINKENABLE;
1636 qib_write_kreg(dd, kr_control, dd->control);
1638 /* write to chip to prevent back-to-back writes of ibc reg */
1639 qib_write_kreg(dd, kr_scratch, 0);
1644 * qib_7220_quiet_serdes - set serdes to txidle
1645 * @ppd: physical port of the qlogic_ib device
1646 * Called when driver is being unloaded
1648 static void qib_7220_quiet_serdes(struct qib_pportdata *ppd)
1651 struct qib_devdata *dd = ppd->dd;
1652 unsigned long flags;
1655 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1656 qib_write_kreg(dd, kr_control,
1657 dd->control | QLOGIC_IB_C_FREEZEMODE);
1659 ppd->cpspec->chase_end = 0;
1660 if (ppd->cpspec->chase_timer.data) /* if initted */
1661 del_timer_sync(&ppd->cpspec->chase_timer);
1663 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
1664 ppd->cpspec->ibdeltainprog) {
1667 /* enable counter writes */
1668 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1669 qib_write_kreg(dd, kr_hwdiagctrl,
1670 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
1672 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
1673 val = read_7220_creg32(dd, cr_ibsymbolerr);
1674 if (ppd->cpspec->ibdeltainprog)
1675 val -= val - ppd->cpspec->ibsymsnap;
1676 val -= ppd->cpspec->ibsymdelta;
1677 write_7220_creg(dd, cr_ibsymbolerr, val);
1679 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
1680 val = read_7220_creg32(dd, cr_iblinkerrrecov);
1681 if (ppd->cpspec->ibdeltainprog)
1682 val -= val - ppd->cpspec->iblnkerrsnap;
1683 val -= ppd->cpspec->iblnkerrdelta;
1684 write_7220_creg(dd, cr_iblinkerrrecov, val);
1687 /* and disable counter writes */
1688 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
1690 qib_set_ib_7220_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1692 spin_lock_irqsave(&ppd->lflags_lock, flags);
1693 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
1694 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1695 wake_up(&ppd->cpspec->autoneg_wait);
1696 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
1698 shutdown_7220_relock_poll(ppd->dd);
1699 val = qib_read_kreg64(ppd->dd, kr_xgxs_cfg);
1700 val |= QLOGIC_IB_XGXS_RESET;
1701 qib_write_kreg(ppd->dd, kr_xgxs_cfg, val);
1705 * qib_setup_7220_setextled - set the state of the two external LEDs
1706 * @dd: the qlogic_ib device
1707 * @on: whether the link is up or not
1709 * The exact combo of LEDs if on is true is determined by looking
1712 * These LEDs indicate the physical and logical state of IB link.
1713 * For this chip (at least with recommended board pinouts), LED1
1714 * is Yellow (logical state) and LED2 is Green (physical state),
1716 * Note: We try to match the Mellanox HCA LED behavior as best
1717 * we can. Green indicates physical link state is OK (something is
1718 * plugged in, and we can train).
1719 * Amber indicates the link is logically up (ACTIVE).
1720 * Mellanox further blinks the amber LED to indicate data packet
1721 * activity, but we have no hardware support for that, so it would
1722 * require waking up every 10-20 msecs and checking the counters
1723 * on the chip, and then turning the LED off if appropriate. That's
1724 * visible overhead, so not something we will do.
1727 static void qib_setup_7220_setextled(struct qib_pportdata *ppd, u32 on)
1729 struct qib_devdata *dd = ppd->dd;
1730 u64 extctl, ledblink = 0, val, lst, ltst;
1731 unsigned long flags;
1734 * The diags use the LED to indicate diag info, so we leave
1735 * the external LED alone when the diags are running.
1737 if (dd->diag_client)
1740 if (ppd->led_override) {
1741 ltst = (ppd->led_override & QIB_LED_PHYS) ?
1742 IB_PHYSPORTSTATE_LINKUP : IB_PHYSPORTSTATE_DISABLED,
1743 lst = (ppd->led_override & QIB_LED_LOG) ?
1744 IB_PORT_ACTIVE : IB_PORT_DOWN;
1746 val = qib_read_kreg64(dd, kr_ibcstatus);
1747 ltst = qib_7220_phys_portstate(val);
1748 lst = qib_7220_iblink_state(val);
1754 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1755 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1756 SYM_MASK(EXTCtrl, LEDPriPortYellowOn));
1757 if (ltst == IB_PHYSPORTSTATE_LINKUP) {
1758 extctl |= SYM_MASK(EXTCtrl, LEDPriPortGreenOn);
1760 * counts are in chip clock (4ns) periods.
1761 * This is 1/16 sec (66.6ms) on,
1762 * 3/16 sec (187.5 ms) off, with packets rcvd
1764 ledblink = ((66600 * 1000UL / 4) << IBA7220_LEDBLINK_ON_SHIFT)
1765 | ((187500 * 1000UL / 4) << IBA7220_LEDBLINK_OFF_SHIFT);
1767 if (lst == IB_PORT_ACTIVE)
1768 extctl |= SYM_MASK(EXTCtrl, LEDPriPortYellowOn);
1769 dd->cspec->extctrl = extctl;
1770 qib_write_kreg(dd, kr_extctrl, extctl);
1771 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1773 if (ledblink) /* blink the LED on packet receive */
1774 qib_write_kreg(dd, kr_rcvpktledcnt, ledblink);
1777 static void qib_7220_free_irq(struct qib_devdata *dd)
1779 if (dd->cspec->irq) {
1780 free_irq(dd->cspec->irq, dd);
1787 * qib_setup_7220_cleanup - clean up any per-chip chip-specific stuff
1788 * @dd: the qlogic_ib device
1790 * This is called during driver unload.
1793 static void qib_setup_7220_cleanup(struct qib_devdata *dd)
1795 qib_7220_free_irq(dd);
1796 kfree(dd->cspec->cntrs);
1797 kfree(dd->cspec->portcntrs);
1801 * This is only called for SDmaInt.
1802 * SDmaDisabled is handled on the error path.
1804 static void sdma_7220_intr(struct qib_pportdata *ppd, u64 istat)
1806 unsigned long flags;
1808 spin_lock_irqsave(&ppd->sdma_lock, flags);
1810 switch (ppd->sdma_state.current_state) {
1811 case qib_sdma_state_s00_hw_down:
1814 case qib_sdma_state_s10_hw_start_up_wait:
1815 __qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
1818 case qib_sdma_state_s20_idle:
1821 case qib_sdma_state_s30_sw_clean_up_wait:
1824 case qib_sdma_state_s40_hw_clean_up_wait:
1827 case qib_sdma_state_s50_hw_halt_wait:
1828 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1831 case qib_sdma_state_s99_running:
1832 /* too chatty to print here */
1833 __qib_sdma_intr(ppd);
1836 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1839 static void qib_wantpiobuf_7220_intr(struct qib_devdata *dd, u32 needint)
1841 unsigned long flags;
1843 spin_lock_irqsave(&dd->sendctrl_lock, flags);
1845 if (!(dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
1848 * blip the availupd off, next write will be on, so
1849 * we ensure an avail update, regardless of threshold or
1850 * buffers becoming free, whenever we want an interrupt
1852 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl &
1853 ~SYM_MASK(SendCtrl, SendBufAvailUpd));
1854 qib_write_kreg(dd, kr_scratch, 0ULL);
1855 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
1857 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
1858 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
1859 qib_write_kreg(dd, kr_scratch, 0ULL);
1861 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
1865 * Handle errors and unusual events first, separate function
1866 * to improve cache hits for fast path interrupt handling.
1868 static noinline void unlikely_7220_intr(struct qib_devdata *dd, u64 istat)
1870 if (unlikely(istat & ~QLOGIC_IB_I_BITSEXTANT))
1872 "interrupt with unknown interrupts %Lx set\n",
1873 istat & ~QLOGIC_IB_I_BITSEXTANT);
1875 if (istat & QLOGIC_IB_I_GPIO) {
1879 * Boards for this chip currently don't use GPIO interrupts,
1880 * so clear by writing GPIOstatus to GPIOclear, and complain
1881 * to alert developer. To avoid endless repeats, clear
1882 * the bits in the mask, since there is some kind of
1883 * programming error or chip problem.
1885 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
1887 * In theory, writing GPIOstatus to GPIOclear could
1888 * have a bad side-effect on some diagnostic that wanted
1889 * to poll for a status-change, but the various shadows
1890 * make that problematic at best. Diags will just suppress
1891 * all GPIO interrupts during such tests.
1893 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
1896 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
1897 u32 gpio_irq = mask & gpiostatus;
1900 * A bit set in status and (chip) Mask register
1901 * would cause an interrupt. Since we are not
1902 * expecting any, report it. Also check that the
1903 * chip reflects our shadow, report issues,
1904 * and refresh from the shadow.
1907 * Clear any troublemakers, and update chip
1910 dd->cspec->gpio_mask &= ~gpio_irq;
1911 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1915 if (istat & QLOGIC_IB_I_ERROR) {
1918 qib_stats.sps_errints++;
1919 estat = qib_read_kreg64(dd, kr_errstatus);
1921 qib_devinfo(dd->pcidev, "error interrupt (%Lx), "
1922 "but no error bits set!\n", istat);
1924 handle_7220_errors(dd, estat);
1928 static irqreturn_t qib_7220intr(int irq, void *data)
1930 struct qib_devdata *dd = data;
1937 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
1939 * This return value is not great, but we do not want the
1940 * interrupt core code to remove our interrupt handler
1941 * because we don't appear to be handling an interrupt
1942 * during a chip reset.
1948 istat = qib_read_kreg64(dd, kr_intstatus);
1950 if (unlikely(!istat)) {
1951 ret = IRQ_NONE; /* not our interrupt, or already handled */
1954 if (unlikely(istat == -1)) {
1955 qib_bad_intrstatus(dd);
1956 /* don't know if it was our interrupt or not */
1961 qib_stats.sps_ints++;
1962 if (dd->int_counter != (u32) -1)
1965 if (unlikely(istat & (~QLOGIC_IB_I_BITSEXTANT |
1966 QLOGIC_IB_I_GPIO | QLOGIC_IB_I_ERROR)))
1967 unlikely_7220_intr(dd, istat);
1970 * Clear the interrupt bits we found set, relatively early, so we
1971 * "know" know the chip will have seen this by the time we process
1972 * the queue, and will re-interrupt if necessary. The processor
1973 * itself won't take the interrupt again until we return.
1975 qib_write_kreg(dd, kr_intclear, istat);
1978 * Handle kernel receive queues before checking for pio buffers
1979 * available since receives can overflow; piobuf waiters can afford
1980 * a few extra cycles, since they were waiting anyway.
1983 ((QLOGIC_IB_I_RCVAVAIL_MASK << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1984 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT));
1986 rmask = (1ULL << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1987 (1ULL << QLOGIC_IB_I_RCVURG_SHIFT);
1988 for (i = 0; i < dd->first_user_ctxt; i++) {
1989 if (ctxtrbits & rmask) {
1990 ctxtrbits &= ~rmask;
1991 qib_kreceive(dd->rcd[i], NULL, NULL);
1997 (ctxtrbits >> QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1998 (ctxtrbits >> QLOGIC_IB_I_RCVURG_SHIFT);
1999 qib_handle_urcv(dd, ctxtrbits);
2003 /* only call for SDmaInt */
2004 if (istat & QLOGIC_IB_I_SDMAINT)
2005 sdma_7220_intr(dd->pport, istat);
2007 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2008 qib_ib_piobufavail(dd);
2016 * Set up our chip-specific interrupt handler.
2017 * The interrupt type has already been setup, so
2018 * we just need to do the registration and error checking.
2019 * If we are using MSI interrupts, we may fall back to
2020 * INTx later, if the interrupt handler doesn't get called
2021 * within 1/2 second (see verify_interrupt()).
2023 static void qib_setup_7220_interrupt(struct qib_devdata *dd)
2025 if (!dd->cspec->irq)
2026 qib_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
2029 int ret = request_irq(dd->cspec->irq, qib_7220intr,
2030 dd->msi_lo ? 0 : IRQF_SHARED,
2034 qib_dev_err(dd, "Couldn't setup %s interrupt "
2035 "(irq=%d): %d\n", dd->msi_lo ?
2036 "MSI" : "INTx", dd->cspec->irq, ret);
2041 * qib_7220_boardname - fill in the board name
2042 * @dd: the qlogic_ib device
2044 * info is based on the board revision register
2046 static void qib_7220_boardname(struct qib_devdata *dd)
2049 u32 boardid, namelen;
2051 boardid = SYM_FIELD(dd->revision, Revision,
2056 n = "InfiniPath_QLE7240";
2059 n = "InfiniPath_QLE7280";
2062 qib_dev_err(dd, "Unknown 7220 board with ID %u\n", boardid);
2063 n = "Unknown_InfiniPath_7220";
2067 namelen = strlen(n) + 1;
2068 dd->boardname = kmalloc(namelen, GFP_KERNEL);
2070 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
2072 snprintf(dd->boardname, namelen, "%s", n);
2074 if (dd->majrev != 5 || !dd->minrev || dd->minrev > 2)
2075 qib_dev_err(dd, "Unsupported InfiniPath hardware "
2076 "revision %u.%u!\n",
2077 dd->majrev, dd->minrev);
2079 snprintf(dd->boardversion, sizeof(dd->boardversion),
2080 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
2081 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
2082 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
2083 dd->majrev, dd->minrev,
2084 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
2088 * This routine sleeps, so it can only be called from user context, not
2089 * from interrupt context.
2091 static int qib_setup_7220_reset(struct qib_devdata *dd)
2097 u8 int_line, clinesz;
2098 unsigned long flags;
2100 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
2102 /* Use dev_err so it shows up in logs, etc. */
2103 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
2105 /* no interrupts till re-initted */
2106 qib_7220_set_intr_state(dd, 0);
2108 dd->pport->cpspec->ibdeltainprog = 0;
2109 dd->pport->cpspec->ibsymdelta = 0;
2110 dd->pport->cpspec->iblnkerrdelta = 0;
2113 * Keep chip from being accessed until we are ready. Use
2114 * writeq() directly, to allow the write even though QIB_PRESENT
2117 dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
2118 dd->int_counter = 0; /* so we check interrupts work again */
2119 val = dd->control | QLOGIC_IB_C_RESET;
2120 writeq(val, &dd->kregbase[kr_control]);
2121 mb(); /* prevent compiler reordering around actual reset */
2123 for (i = 1; i <= 5; i++) {
2125 * Allow MBIST, etc. to complete; longer on each retry.
2126 * We sometimes get machine checks from bus timeout if no
2127 * response, so for now, make it *really* long.
2129 msleep(1000 + (1 + i) * 2000);
2131 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
2134 * Use readq directly, so we don't need to mark it as PRESENT
2135 * until we get a successful indication that all is well.
2137 val = readq(&dd->kregbase[kr_revision]);
2138 if (val == dd->revision) {
2139 dd->flags |= QIB_PRESENT; /* it's back */
2140 ret = qib_reinit_intr(dd);
2144 ret = 0; /* failed */
2148 if (qib_pcie_params(dd, dd->lbus_width, NULL, NULL))
2149 qib_dev_err(dd, "Reset failed to setup PCIe or "
2150 "interrupts; continuing anyway\n");
2152 /* hold IBC in reset, no sends, etc till later */
2153 qib_write_kreg(dd, kr_control, 0ULL);
2155 /* clear the reset error, init error/hwerror mask */
2156 qib_7220_init_hwerrors(dd);
2158 /* do setup similar to speed or link-width changes */
2159 if (dd->pport->cpspec->ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK)
2160 dd->cspec->presets_needed = 1;
2161 spin_lock_irqsave(&dd->pport->lflags_lock, flags);
2162 dd->pport->lflags |= QIBL_IB_FORCE_NOTIFY;
2163 dd->pport->lflags &= ~QIBL_IB_AUTONEG_FAILED;
2164 spin_unlock_irqrestore(&dd->pport->lflags_lock, flags);
2171 * qib_7220_put_tid - write a TID to the chip
2172 * @dd: the qlogic_ib device
2173 * @tidptr: pointer to the expected TID (in chip) to update
2174 * @tidtype: 0 for eager, 1 for expected
2175 * @pa: physical address of in memory buffer; tidinvalid if freeing
2177 static void qib_7220_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
2178 u32 type, unsigned long pa)
2180 if (pa != dd->tidinvalid) {
2181 u64 chippa = pa >> IBA7220_TID_PA_SHIFT;
2183 /* paranoia checks */
2184 if (pa != (chippa << IBA7220_TID_PA_SHIFT)) {
2185 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
2189 if (chippa >= (1UL << IBA7220_TID_SZ_SHIFT)) {
2190 qib_dev_err(dd, "Physical page address 0x%lx "
2191 "larger than supported\n", pa);
2195 if (type == RCVHQ_RCV_TYPE_EAGER)
2196 chippa |= dd->tidtemplate;
2197 else /* for now, always full 4KB page */
2198 chippa |= IBA7220_TID_SZ_4K;
2206 * qib_7220_clear_tids - clear all TID entries for a ctxt, expected and eager
2207 * @dd: the qlogic_ib device
2210 * clear all TID entries for a ctxt, expected and eager.
2211 * Used from qib_close(). On this chip, TIDs are only 32 bits,
2212 * not 64, but they are still on 64 bit boundaries, so tidbase
2213 * is declared as u64 * for the pointer math, even though we write 32 bits
2215 static void qib_7220_clear_tids(struct qib_devdata *dd,
2216 struct qib_ctxtdata *rcd)
2218 u64 __iomem *tidbase;
2219 unsigned long tidinv;
2223 if (!dd->kregbase || !rcd)
2228 tidinv = dd->tidinvalid;
2229 tidbase = (u64 __iomem *)
2230 ((char __iomem *)(dd->kregbase) +
2232 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
2234 for (i = 0; i < dd->rcvtidcnt; i++)
2235 qib_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
2238 tidbase = (u64 __iomem *)
2239 ((char __iomem *)(dd->kregbase) +
2241 rcd->rcvegr_tid_base * sizeof(*tidbase));
2243 for (i = 0; i < rcd->rcvegrcnt; i++)
2244 qib_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
2249 * qib_7220_tidtemplate - setup constants for TID updates
2250 * @dd: the qlogic_ib device
2252 * We setup stuff that we use a lot, to avoid calculating each time
2254 static void qib_7220_tidtemplate(struct qib_devdata *dd)
2256 if (dd->rcvegrbufsize == 2048)
2257 dd->tidtemplate = IBA7220_TID_SZ_2K;
2258 else if (dd->rcvegrbufsize == 4096)
2259 dd->tidtemplate = IBA7220_TID_SZ_4K;
2264 * qib_init_7220_get_base_info - set chip-specific flags for user code
2265 * @rcd: the qlogic_ib ctxt
2266 * @kbase: qib_base_info pointer
2268 * We set the PCIE flag because the lower bandwidth on PCIe vs
2269 * HyperTransport can affect some user packet algorithims.
2271 static int qib_7220_get_base_info(struct qib_ctxtdata *rcd,
2272 struct qib_base_info *kinfo)
2274 kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE |
2275 QIB_RUNTIME_NODMA_RTAIL | QIB_RUNTIME_SDMA;
2277 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
2278 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
2283 static struct qib_message_header *
2284 qib_7220_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
2286 u32 offset = qib_hdrget_offset(rhf_addr);
2288 return (struct qib_message_header *)
2289 (rhf_addr - dd->rhf_offset + offset);
2292 static void qib_7220_config_ctxts(struct qib_devdata *dd)
2294 unsigned long flags;
2297 nchipctxts = qib_read_kreg32(dd, kr_portcnt);
2298 dd->cspec->numctxts = nchipctxts;
2299 if (qib_n_krcv_queues > 1) {
2300 dd->qpn_mask = 0x3e;
2301 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
2302 if (dd->first_user_ctxt > nchipctxts)
2303 dd->first_user_ctxt = nchipctxts;
2305 dd->first_user_ctxt = dd->num_pports;
2306 dd->n_krcv_queues = dd->first_user_ctxt;
2308 if (!qib_cfgctxts) {
2309 int nctxts = dd->first_user_ctxt + num_online_cpus();
2313 else if (nctxts <= 9)
2315 else if (nctxts <= nchipctxts)
2316 dd->ctxtcnt = nchipctxts;
2317 } else if (qib_cfgctxts <= nchipctxts)
2318 dd->ctxtcnt = qib_cfgctxts;
2319 if (!dd->ctxtcnt) /* none of the above, set to max */
2320 dd->ctxtcnt = nchipctxts;
2323 * Chip can be configured for 5, 9, or 17 ctxts, and choice
2324 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
2325 * Lock to be paranoid about later motion, etc.
2327 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2328 if (dd->ctxtcnt > 9)
2329 dd->rcvctrl |= 2ULL << IBA7220_R_CTXTCFG_SHIFT;
2330 else if (dd->ctxtcnt > 5)
2331 dd->rcvctrl |= 1ULL << IBA7220_R_CTXTCFG_SHIFT;
2332 /* else configure for default 5 receive ctxts */
2334 dd->rcvctrl |= 1ULL << QIB_7220_RcvCtrl_RcvQPMapEnable_LSB;
2335 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2336 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2338 /* kr_rcvegrcnt changes based on the number of contexts enabled */
2339 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
2340 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, IBA7220_KRCVEGRCNT);
2343 static int qib_7220_get_ib_cfg(struct qib_pportdata *ppd, int which)
2346 u64 maskr; /* right-justified mask */
2349 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
2350 ret = ppd->link_width_enabled;
2353 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
2354 ret = ppd->link_width_active;
2357 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
2358 ret = ppd->link_speed_enabled;
2361 case QIB_IB_CFG_SPD: /* Get current Link spd */
2362 ret = ppd->link_speed_active;
2365 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
2366 lsb = IBA7220_IBC_RXPOL_SHIFT;
2367 maskr = IBA7220_IBC_RXPOL_MASK;
2370 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
2371 lsb = IBA7220_IBC_LREV_SHIFT;
2372 maskr = IBA7220_IBC_LREV_MASK;
2375 case QIB_IB_CFG_LINKLATENCY:
2376 ret = qib_read_kreg64(ppd->dd, kr_ibcddrstatus)
2377 & IBA7220_DDRSTAT_LINKLAT_MASK;
2380 case QIB_IB_CFG_OP_VLS:
2381 ret = ppd->vls_operational;
2384 case QIB_IB_CFG_VL_HIGH_CAP:
2388 case QIB_IB_CFG_VL_LOW_CAP:
2392 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2393 ret = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2397 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2398 ret = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2402 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2403 /* will only take effect when the link state changes */
2404 ret = (ppd->cpspec->ibcctrl &
2405 SYM_MASK(IBCCtrl, LinkDownDefaultState)) ?
2406 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
2409 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
2410 lsb = IBA7220_IBC_HRTBT_SHIFT;
2411 maskr = IBA7220_IBC_HRTBT_MASK;
2414 case QIB_IB_CFG_PMA_TICKS:
2416 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
2417 * Since the clock is always 250MHz, the value is 1 or 0.
2419 ret = (ppd->link_speed_active == QIB_IB_DDR);
2426 ret = (int)((ppd->cpspec->ibcddrctrl >> lsb) & maskr);
2431 static int qib_7220_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
2433 struct qib_devdata *dd = ppd->dd;
2434 u64 maskr; /* right-justified mask */
2435 int lsb, ret = 0, setforce = 0;
2437 unsigned long flags;
2441 case QIB_IB_CFG_LIDLMC:
2443 * Set LID and LMC. Combined to avoid possible hazard
2444 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
2446 lsb = IBA7220_IBC_DLIDLMC_SHIFT;
2447 maskr = IBA7220_IBC_DLIDLMC_MASK;
2450 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
2452 * As with speed, only write the actual register if
2453 * the link is currently down, otherwise takes effect
2454 * on next link change.
2456 ppd->link_width_enabled = val;
2457 if (!(ppd->lflags & QIBL_LINKDOWN))
2460 * We set the QIBL_IB_FORCE_NOTIFY bit so updown
2461 * will get called because we want update
2462 * link_width_active, and the change may not take
2463 * effect for some time (if we are in POLL), so this
2464 * flag will force the updown routine to be called
2465 * on the next ibstatuschange down interrupt, even
2466 * if it's not an down->up transition.
2468 val--; /* convert from IB to chip */
2469 maskr = IBA7220_IBC_WIDTH_MASK;
2470 lsb = IBA7220_IBC_WIDTH_SHIFT;
2474 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
2476 * If we turn off IB1.2, need to preset SerDes defaults,
2477 * but not right now. Set a flag for the next time
2478 * we command the link down. As with width, only write the
2479 * actual register if the link is currently down, otherwise
2480 * takes effect on next link change. Since setting is being
2481 * explicitly requested (via MAD or sysfs), clear autoneg
2482 * failure status if speed autoneg is enabled.
2484 ppd->link_speed_enabled = val;
2485 if ((ppd->cpspec->ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK) &&
2487 dd->cspec->presets_needed = 1;
2488 if (!(ppd->lflags & QIBL_LINKDOWN))
2491 * We set the QIBL_IB_FORCE_NOTIFY bit so updown
2492 * will get called because we want update
2493 * link_speed_active, and the change may not take
2494 * effect for some time (if we are in POLL), so this
2495 * flag will force the updown routine to be called
2496 * on the next ibstatuschange down interrupt, even
2497 * if it's not an down->up transition.
2499 if (val == (QIB_IB_SDR | QIB_IB_DDR)) {
2500 val = IBA7220_IBC_SPEED_AUTONEG_MASK |
2501 IBA7220_IBC_IBTA_1_2_MASK;
2502 spin_lock_irqsave(&ppd->lflags_lock, flags);
2503 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
2504 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2506 val = val == QIB_IB_DDR ?
2507 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
2508 maskr = IBA7220_IBC_SPEED_AUTONEG_MASK |
2509 IBA7220_IBC_IBTA_1_2_MASK;
2510 /* IBTA 1.2 mode + speed bits are contiguous */
2511 lsb = SYM_LSB(IBCDDRCtrl, IB_ENHANCED_MODE);
2515 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
2516 lsb = IBA7220_IBC_RXPOL_SHIFT;
2517 maskr = IBA7220_IBC_RXPOL_MASK;
2520 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
2521 lsb = IBA7220_IBC_LREV_SHIFT;
2522 maskr = IBA7220_IBC_LREV_MASK;
2525 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2526 maskr = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2529 ppd->cpspec->ibcctrl &=
2530 ~SYM_MASK(IBCCtrl, OverrunThreshold);
2531 ppd->cpspec->ibcctrl |= (u64) val <<
2532 SYM_LSB(IBCCtrl, OverrunThreshold);
2533 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2534 qib_write_kreg(dd, kr_scratch, 0);
2538 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2539 maskr = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2542 ppd->cpspec->ibcctrl &=
2543 ~SYM_MASK(IBCCtrl, PhyerrThreshold);
2544 ppd->cpspec->ibcctrl |= (u64) val <<
2545 SYM_LSB(IBCCtrl, PhyerrThreshold);
2546 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2547 qib_write_kreg(dd, kr_scratch, 0);
2551 case QIB_IB_CFG_PKEYS: /* update pkeys */
2552 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
2553 ((u64) ppd->pkeys[2] << 32) |
2554 ((u64) ppd->pkeys[3] << 48);
2555 qib_write_kreg(dd, kr_partitionkey, maskr);
2558 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2559 /* will only take effect when the link state changes */
2560 if (val == IB_LINKINITCMD_POLL)
2561 ppd->cpspec->ibcctrl &=
2562 ~SYM_MASK(IBCCtrl, LinkDownDefaultState);
2564 ppd->cpspec->ibcctrl |=
2565 SYM_MASK(IBCCtrl, LinkDownDefaultState);
2566 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2567 qib_write_kreg(dd, kr_scratch, 0);
2570 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
2572 * Update our housekeeping variables, and set IBC max
2573 * size, same as init code; max IBC is max we allow in
2574 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2575 * Set even if it's unchanged, print debug message only
2578 val = (ppd->ibmaxlen >> 2) + 1;
2579 ppd->cpspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen);
2580 ppd->cpspec->ibcctrl |= (u64)val << SYM_LSB(IBCCtrl, MaxPktLen);
2581 qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2582 qib_write_kreg(dd, kr_scratch, 0);
2585 case QIB_IB_CFG_LSTATE: /* set the IB link state */
2586 switch (val & 0xffff0000) {
2587 case IB_LINKCMD_DOWN:
2588 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
2589 if (!ppd->cpspec->ibdeltainprog &&
2590 qib_compat_ddr_negotiate) {
2591 ppd->cpspec->ibdeltainprog = 1;
2592 ppd->cpspec->ibsymsnap =
2593 read_7220_creg32(dd, cr_ibsymbolerr);
2594 ppd->cpspec->iblnkerrsnap =
2595 read_7220_creg32(dd, cr_iblinkerrrecov);
2599 case IB_LINKCMD_ARMED:
2600 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
2603 case IB_LINKCMD_ACTIVE:
2604 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
2609 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
2612 switch (val & 0xffff) {
2613 case IB_LINKINITCMD_NOP:
2617 case IB_LINKINITCMD_POLL:
2618 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
2621 case IB_LINKINITCMD_SLEEP:
2622 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
2625 case IB_LINKINITCMD_DISABLE:
2626 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
2627 ppd->cpspec->chase_end = 0;
2629 * stop state chase counter and timer, if running.
2630 * wait forpending timer, but don't clear .data (ppd)!
2632 if (ppd->cpspec->chase_timer.expires) {
2633 del_timer_sync(&ppd->cpspec->chase_timer);
2634 ppd->cpspec->chase_timer.expires = 0;
2640 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
2644 qib_set_ib_7220_lstate(ppd, lcmd, licmd);
2646 maskr = IBA7220_IBC_WIDTH_MASK;
2647 lsb = IBA7220_IBC_WIDTH_SHIFT;
2648 tmp = (ppd->cpspec->ibcddrctrl >> lsb) & maskr;
2649 /* If the width active on the chip does not match the
2650 * width in the shadow register, write the new active
2651 * width to the chip.
2652 * We don't have to worry about speed as the speed is taken
2653 * care of by set_7220_ibspeed_fast called by ib_updown.
2655 if (ppd->link_width_enabled-1 != tmp) {
2656 ppd->cpspec->ibcddrctrl &= ~(maskr << lsb);
2657 ppd->cpspec->ibcddrctrl |=
2658 (((u64)(ppd->link_width_enabled-1) & maskr) <<
2660 qib_write_kreg(dd, kr_ibcddrctrl,
2661 ppd->cpspec->ibcddrctrl);
2662 qib_write_kreg(dd, kr_scratch, 0);
2663 spin_lock_irqsave(&ppd->lflags_lock, flags);
2664 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
2665 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2669 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
2670 if (val > IBA7220_IBC_HRTBT_MASK) {
2674 lsb = IBA7220_IBC_HRTBT_SHIFT;
2675 maskr = IBA7220_IBC_HRTBT_MASK;
2682 ppd->cpspec->ibcddrctrl &= ~(maskr << lsb);
2683 ppd->cpspec->ibcddrctrl |= (((u64) val & maskr) << lsb);
2684 qib_write_kreg(dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
2685 qib_write_kreg(dd, kr_scratch, 0);
2687 spin_lock_irqsave(&ppd->lflags_lock, flags);
2688 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
2689 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2695 static int qib_7220_set_loopback(struct qib_pportdata *ppd, const char *what)
2700 if (!strncmp(what, "ibc", 3)) {
2701 ppd->cpspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback);
2702 val = 0; /* disable heart beat, so link will come up */
2703 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
2704 ppd->dd->unit, ppd->port);
2705 } else if (!strncmp(what, "off", 3)) {
2706 ppd->cpspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback);
2707 /* enable heart beat again */
2708 val = IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
2709 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
2710 "(normal)\n", ppd->dd->unit, ppd->port);
2714 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2715 ddr = ppd->cpspec->ibcddrctrl & ~(IBA7220_IBC_HRTBT_MASK
2716 << IBA7220_IBC_HRTBT_SHIFT);
2717 ppd->cpspec->ibcddrctrl = ddr | val;
2718 qib_write_kreg(ppd->dd, kr_ibcddrctrl,
2719 ppd->cpspec->ibcddrctrl);
2720 qib_write_kreg(ppd->dd, kr_scratch, 0);
2725 static void qib_update_7220_usrhead(struct qib_ctxtdata *rcd, u64 hd,
2726 u32 updegr, u32 egrhd, u32 npkts)
2729 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
2731 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
2735 static u32 qib_7220_hdrqempty(struct qib_ctxtdata *rcd)
2739 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
2740 if (rcd->rcvhdrtail_kvaddr)
2741 tail = qib_get_rcvhdrtail(rcd);
2743 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
2744 return head == tail;
2748 * Modify the RCVCTRL register in chip-specific way. This
2749 * is a function because bit positions and (future) register
2750 * location is chip-specifc, but the needed operations are
2751 * generic. <op> is a bit-mask because we often want to
2752 * do multiple modifications.
2754 static void rcvctrl_7220_mod(struct qib_pportdata *ppd, unsigned int op,
2757 struct qib_devdata *dd = ppd->dd;
2759 unsigned long flags;
2761 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2762 if (op & QIB_RCVCTRL_TAILUPD_ENB)
2763 dd->rcvctrl |= (1ULL << IBA7220_R_TAILUPD_SHIFT);
2764 if (op & QIB_RCVCTRL_TAILUPD_DIS)
2765 dd->rcvctrl &= ~(1ULL << IBA7220_R_TAILUPD_SHIFT);
2766 if (op & QIB_RCVCTRL_PKEY_ENB)
2767 dd->rcvctrl &= ~(1ULL << IBA7220_R_PKEY_DIS_SHIFT);
2768 if (op & QIB_RCVCTRL_PKEY_DIS)
2769 dd->rcvctrl |= (1ULL << IBA7220_R_PKEY_DIS_SHIFT);
2771 mask = (1ULL << dd->ctxtcnt) - 1;
2773 mask = (1ULL << ctxt);
2774 if (op & QIB_RCVCTRL_CTXT_ENB) {
2775 /* always done for specific ctxt */
2776 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable));
2777 if (!(dd->flags & QIB_NODMA_RTAIL))
2778 dd->rcvctrl |= 1ULL << IBA7220_R_TAILUPD_SHIFT;
2779 /* Write these registers before the context is enabled. */
2780 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2781 dd->rcd[ctxt]->rcvhdrqtailaddr_phys);
2782 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2783 dd->rcd[ctxt]->rcvhdrq_phys);
2784 dd->rcd[ctxt]->seq_cnt = 1;
2786 if (op & QIB_RCVCTRL_CTXT_DIS)
2787 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable));
2788 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
2789 dd->rcvctrl |= (mask << IBA7220_R_INTRAVAIL_SHIFT);
2790 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
2791 dd->rcvctrl &= ~(mask << IBA7220_R_INTRAVAIL_SHIFT);
2792 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2793 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) {
2794 /* arm rcv interrupt */
2795 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) |
2796 dd->rhdrhead_intr_off;
2797 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2799 if (op & QIB_RCVCTRL_CTXT_ENB) {
2801 * Init the context registers also; if we were
2802 * disabled, tail and head should both be zero
2803 * already from the enable, but since we don't
2804 * know, we have to do it explicitly.
2806 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2807 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
2809 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
2810 dd->rcd[ctxt]->head = val;
2811 /* If kctxt, interrupt on next receive. */
2812 if (ctxt < dd->first_user_ctxt)
2813 val |= dd->rhdrhead_intr_off;
2814 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2816 if (op & QIB_RCVCTRL_CTXT_DIS) {
2818 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt, 0);
2819 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt, 0);
2823 for (i = 0; i < dd->cfgctxts; i++) {
2824 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr,
2826 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, i, 0);
2830 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2834 * Modify the SENDCTRL register in chip-specific way. This
2835 * is a function there may be multiple such registers with
2836 * slightly different layouts. To start, we assume the
2837 * "canonical" register layout of the first chips.
2838 * Chip requires no back-back sendctrl writes, so write
2839 * scratch register after writing sendctrl
2841 static void sendctrl_7220_mod(struct qib_pportdata *ppd, u32 op)
2843 struct qib_devdata *dd = ppd->dd;
2844 u64 tmp_dd_sendctrl;
2845 unsigned long flags;
2847 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2849 /* First the ones that are "sticky", saved in shadow */
2850 if (op & QIB_SENDCTRL_CLEAR)
2852 if (op & QIB_SENDCTRL_SEND_DIS)
2853 dd->sendctrl &= ~SYM_MASK(SendCtrl, SPioEnable);
2854 else if (op & QIB_SENDCTRL_SEND_ENB) {
2855 dd->sendctrl |= SYM_MASK(SendCtrl, SPioEnable);
2856 if (dd->flags & QIB_USE_SPCL_TRIG)
2857 dd->sendctrl |= SYM_MASK(SendCtrl,
2860 if (op & QIB_SENDCTRL_AVAIL_DIS)
2861 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
2862 else if (op & QIB_SENDCTRL_AVAIL_ENB)
2863 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
2865 if (op & QIB_SENDCTRL_DISARM_ALL) {
2868 tmp_dd_sendctrl = dd->sendctrl;
2870 * disarm any that are not yet launched, disabling sends
2871 * and updates until done.
2873 last = dd->piobcnt2k + dd->piobcnt4k;
2875 ~(SYM_MASK(SendCtrl, SPioEnable) |
2876 SYM_MASK(SendCtrl, SendBufAvailUpd));
2877 for (i = 0; i < last; i++) {
2878 qib_write_kreg(dd, kr_sendctrl,
2880 SYM_MASK(SendCtrl, Disarm) | i);
2881 qib_write_kreg(dd, kr_scratch, 0);
2885 tmp_dd_sendctrl = dd->sendctrl;
2887 if (op & QIB_SENDCTRL_FLUSH)
2888 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Abort);
2889 if (op & QIB_SENDCTRL_DISARM)
2890 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
2891 ((op & QIB_7220_SendCtrl_DisarmPIOBuf_RMASK) <<
2892 SYM_LSB(SendCtrl, DisarmPIOBuf));
2893 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
2894 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
2895 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
2897 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
2898 qib_write_kreg(dd, kr_scratch, 0);
2900 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
2901 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2902 qib_write_kreg(dd, kr_scratch, 0);
2905 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2907 if (op & QIB_SENDCTRL_FLUSH) {
2910 * ensure writes have hit chip, then do a few
2911 * more reads, to allow DMA of pioavail registers
2912 * to occur, so in-memory copy is in sync with
2913 * the chip. Not always safe to sleep.
2915 v = qib_read_kreg32(dd, kr_scratch);
2916 qib_write_kreg(dd, kr_scratch, v);
2917 v = qib_read_kreg32(dd, kr_scratch);
2918 qib_write_kreg(dd, kr_scratch, v);
2919 qib_read_kreg32(dd, kr_scratch);
2924 * qib_portcntr_7220 - read a per-port counter
2925 * @dd: the qlogic_ib device
2926 * @creg: the counter to snapshot
2928 static u64 qib_portcntr_7220(struct qib_pportdata *ppd, u32 reg)
2931 struct qib_devdata *dd = ppd->dd;
2933 /* 0xffff for unimplemented or synthesized counters */
2934 static const u16 xlator[] = {
2935 [QIBPORTCNTR_PKTSEND] = cr_pktsend,
2936 [QIBPORTCNTR_WORDSEND] = cr_wordsend,
2937 [QIBPORTCNTR_PSXMITDATA] = cr_psxmitdatacount,
2938 [QIBPORTCNTR_PSXMITPKTS] = cr_psxmitpktscount,
2939 [QIBPORTCNTR_PSXMITWAIT] = cr_psxmitwaitcount,
2940 [QIBPORTCNTR_SENDSTALL] = cr_sendstall,
2941 [QIBPORTCNTR_PKTRCV] = cr_pktrcv,
2942 [QIBPORTCNTR_PSRCVDATA] = cr_psrcvdatacount,
2943 [QIBPORTCNTR_PSRCVPKTS] = cr_psrcvpktscount,
2944 [QIBPORTCNTR_RCVEBP] = cr_rcvebp,
2945 [QIBPORTCNTR_RCVOVFL] = cr_rcvovfl,
2946 [QIBPORTCNTR_WORDRCV] = cr_wordrcv,
2947 [QIBPORTCNTR_RXDROPPKT] = cr_rxdroppkt,
2948 [QIBPORTCNTR_RXLOCALPHYERR] = cr_rxotherlocalphyerr,
2949 [QIBPORTCNTR_RXVLERR] = cr_rxvlerr,
2950 [QIBPORTCNTR_ERRICRC] = cr_erricrc,
2951 [QIBPORTCNTR_ERRVCRC] = cr_errvcrc,
2952 [QIBPORTCNTR_ERRLPCRC] = cr_errlpcrc,
2953 [QIBPORTCNTR_BADFORMAT] = cr_badformat,
2954 [QIBPORTCNTR_ERR_RLEN] = cr_err_rlen,
2955 [QIBPORTCNTR_IBSYMBOLERR] = cr_ibsymbolerr,
2956 [QIBPORTCNTR_INVALIDRLEN] = cr_invalidrlen,
2957 [QIBPORTCNTR_UNSUPVL] = cr_txunsupvl,
2958 [QIBPORTCNTR_EXCESSBUFOVFL] = cr_excessbufferovfl,
2959 [QIBPORTCNTR_ERRLINK] = cr_errlink,
2960 [QIBPORTCNTR_IBLINKDOWN] = cr_iblinkdown,
2961 [QIBPORTCNTR_IBLINKERRRECOV] = cr_iblinkerrrecov,
2962 [QIBPORTCNTR_LLI] = cr_locallinkintegrityerr,
2963 [QIBPORTCNTR_PSINTERVAL] = cr_psinterval,
2964 [QIBPORTCNTR_PSSTART] = cr_psstart,
2965 [QIBPORTCNTR_PSSTAT] = cr_psstat,
2966 [QIBPORTCNTR_VL15PKTDROP] = cr_vl15droppedpkt,
2967 [QIBPORTCNTR_ERRPKEY] = cr_errpkey,
2968 [QIBPORTCNTR_KHDROVFL] = 0xffff,
2971 if (reg >= ARRAY_SIZE(xlator)) {
2972 qib_devinfo(ppd->dd->pcidev,
2973 "Unimplemented portcounter %u\n", reg);
2978 if (reg == QIBPORTCNTR_KHDROVFL) {
2981 /* sum over all kernel contexts */
2982 for (i = 0; i < dd->first_user_ctxt; i++)
2983 ret += read_7220_creg32(dd, cr_portovfl + i);
2989 * only fast incrementing counters are 64bit; use 32 bit reads to
2990 * avoid two independent reads when on opteron
2992 if ((creg == cr_wordsend || creg == cr_wordrcv ||
2993 creg == cr_pktsend || creg == cr_pktrcv))
2994 ret = read_7220_creg(dd, creg);
2996 ret = read_7220_creg32(dd, creg);
2997 if (creg == cr_ibsymbolerr) {
2998 if (dd->pport->cpspec->ibdeltainprog)
2999 ret -= ret - ppd->cpspec->ibsymsnap;
3000 ret -= dd->pport->cpspec->ibsymdelta;
3001 } else if (creg == cr_iblinkerrrecov) {
3002 if (dd->pport->cpspec->ibdeltainprog)
3003 ret -= ret - ppd->cpspec->iblnkerrsnap;
3004 ret -= dd->pport->cpspec->iblnkerrdelta;
3011 * Device counter names (not port-specific), one line per stat,
3012 * single string. Used by utilities like ipathstats to print the stats
3013 * in a way which works for different versions of drivers, without changing
3014 * the utility. Names need to be 12 chars or less (w/o newline), for proper
3015 * display by utility.
3016 * Non-error counters are first.
3017 * Start of "error" conters is indicated by a leading "E " on the first
3018 * "error" counter, and doesn't count in label length.
3019 * The EgrOvfl list needs to be last so we truncate them at the configured
3020 * context count for the device.
3021 * cntr7220indices contains the corresponding register indices.
3023 static const char cntr7220names[] =
3046 static const size_t cntr7220indices[] = {
3071 * same as cntr7220names and cntr7220indices, but for port-specific counters.
3072 * portcntr7220indices is somewhat complicated by some registers needing
3073 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
3075 static const char portcntr7220names[] =
3083 "TxDmaDesc\n" /* 7220 and 7322-only */
3084 "E RxDlidFltr\n" /* 7220 and 7322-only */
3107 "RxLclPhyErr\n" /* 7220 and 7322-only */
3108 "RxVL15Drop\n" /* 7220 and 7322-only */
3109 "RxVlErr\n" /* 7220 and 7322-only */
3110 "XcessBufOvfl\n" /* 7220 and 7322-only */
3113 #define _PORT_VIRT_FLAG 0x8000 /* "virtual", need adjustments */
3114 static const size_t portcntr7220indices[] = {
3115 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
3117 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
3118 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
3120 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
3121 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
3125 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
3126 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
3127 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
3128 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
3129 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
3130 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
3131 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
3132 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
3133 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
3135 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
3136 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
3137 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
3138 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
3139 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
3140 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
3146 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
3147 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
3148 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
3149 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
3152 /* do all the setup to make the counter reads efficient later */
3153 static void init_7220_cntrnames(struct qib_devdata *dd)
3158 for (i = 0, s = (char *)cntr7220names; s && j <= dd->cfgctxts;
3160 /* we always have at least one counter before the egrovfl */
3161 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
3163 s = strchr(s + 1, '\n');
3167 dd->cspec->ncntrs = i;
3169 /* full list; size is without terminating null */
3170 dd->cspec->cntrnamelen = sizeof(cntr7220names) - 1;
3172 dd->cspec->cntrnamelen = 1 + s - cntr7220names;
3173 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
3174 * sizeof(u64), GFP_KERNEL);
3175 if (!dd->cspec->cntrs)
3176 qib_dev_err(dd, "Failed allocation for counters\n");
3178 for (i = 0, s = (char *)portcntr7220names; s; i++)
3179 s = strchr(s + 1, '\n');
3180 dd->cspec->nportcntrs = i - 1;
3181 dd->cspec->portcntrnamelen = sizeof(portcntr7220names) - 1;
3182 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs
3183 * sizeof(u64), GFP_KERNEL);
3184 if (!dd->cspec->portcntrs)
3185 qib_dev_err(dd, "Failed allocation for portcounters\n");
3188 static u32 qib_read_7220cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
3193 if (!dd->cspec->cntrs) {
3199 *namep = (char *)cntr7220names;
3200 ret = dd->cspec->cntrnamelen;
3202 ret = 0; /* final read after getting everything */
3204 u64 *cntr = dd->cspec->cntrs;
3207 ret = dd->cspec->ncntrs * sizeof(u64);
3208 if (!cntr || pos >= ret) {
3209 /* everything read, or couldn't get memory */
3215 for (i = 0; i < dd->cspec->ncntrs; i++)
3216 *cntr++ = read_7220_creg32(dd, cntr7220indices[i]);
3222 static u32 qib_read_7220portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
3223 char **namep, u64 **cntrp)
3227 if (!dd->cspec->portcntrs) {
3232 *namep = (char *)portcntr7220names;
3233 ret = dd->cspec->portcntrnamelen;
3235 ret = 0; /* final read after getting everything */
3237 u64 *cntr = dd->cspec->portcntrs;
3238 struct qib_pportdata *ppd = &dd->pport[port];
3241 ret = dd->cspec->nportcntrs * sizeof(u64);
3242 if (!cntr || pos >= ret) {
3243 /* everything read, or couldn't get memory */
3248 for (i = 0; i < dd->cspec->nportcntrs; i++) {
3249 if (portcntr7220indices[i] & _PORT_VIRT_FLAG)
3250 *cntr++ = qib_portcntr_7220(ppd,
3251 portcntr7220indices[i] &
3254 *cntr++ = read_7220_creg32(dd,
3255 portcntr7220indices[i]);
3263 * qib_get_7220_faststats - get word counters from chip before they overflow
3264 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
3266 * This needs more work; in particular, decision on whether we really
3267 * need traffic_wds done the way it is
3268 * called from add_timer
3270 static void qib_get_7220_faststats(unsigned long opaque)
3272 struct qib_devdata *dd = (struct qib_devdata *) opaque;
3273 struct qib_pportdata *ppd = dd->pport;
3274 unsigned long flags;
3278 * don't access the chip while running diags, or memory diags can
3281 if (!(dd->flags & QIB_INITTED) || dd->diag_client)
3282 /* but re-arm the timer, for diags case; won't hurt other */
3286 * We now try to maintain an activity timer, based on traffic
3287 * exceeding a threshold, so we need to check the word-counts
3288 * even if they are 64-bit.
3290 traffic_wds = qib_portcntr_7220(ppd, cr_wordsend) +
3291 qib_portcntr_7220(ppd, cr_wordrcv);
3292 spin_lock_irqsave(&dd->eep_st_lock, flags);
3293 traffic_wds -= dd->traffic_wds;
3294 dd->traffic_wds += traffic_wds;
3295 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
3296 atomic_add(5, &dd->active_time); /* S/B #define */
3297 spin_unlock_irqrestore(&dd->eep_st_lock, flags);
3299 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
3303 * If we are using MSI, try to fallback to INTx.
3305 static int qib_7220_intr_fallback(struct qib_devdata *dd)
3310 qib_devinfo(dd->pcidev, "MSI interrupt not detected,"
3311 " trying INTx interrupts\n");
3312 qib_7220_free_irq(dd);
3313 qib_enable_intx(dd->pcidev);
3315 * Some newer kernels require free_irq before disable_msi,
3316 * and irq can be changed during disable and INTx enable
3317 * and we need to therefore use the pcidev->irq value,
3318 * not our saved MSI value.
3320 dd->cspec->irq = dd->pcidev->irq;
3321 qib_setup_7220_interrupt(dd);
3326 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
3327 * than resetting the IBC or external link state, and useful in some
3328 * cases to cause some retraining. To do this right, we reset IBC
3331 static void qib_7220_xgxs_reset(struct qib_pportdata *ppd)
3334 struct qib_devdata *dd = ppd->dd;
3336 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
3337 val = prev_val | QLOGIC_IB_XGXS_RESET;
3338 prev_val &= ~QLOGIC_IB_XGXS_RESET; /* be sure */
3339 qib_write_kreg(dd, kr_control,
3340 dd->control & ~QLOGIC_IB_C_LINKENABLE);
3341 qib_write_kreg(dd, kr_xgxs_cfg, val);
3342 qib_read_kreg32(dd, kr_scratch);
3343 qib_write_kreg(dd, kr_xgxs_cfg, prev_val);
3344 qib_write_kreg(dd, kr_control, dd->control);
3348 * For this chip, we want to use the same buffer every time
3349 * when we are trying to bring the link up (they are always VL15
3350 * packets). At that link state the packet should always go out immediately
3351 * (or at least be discarded at the tx interface if the link is down).
3352 * If it doesn't, and the buffer isn't available, that means some other
3353 * sender has gotten ahead of us, and is preventing our packet from going
3354 * out. In that case, we flush all packets, and try again. If that still
3355 * fails, we fail the request, and hope things work the next time around.
3357 * We don't need very complicated heuristics on whether the packet had
3358 * time to go out or not, since even at SDR 1X, it goes out in very short
3359 * time periods, covered by the chip reads done here and as part of the
3362 static u32 __iomem *get_7220_link_buf(struct qib_pportdata *ppd, u32 *bnum)
3365 u32 lbuf = ppd->dd->cspec->lastbuf_for_pio;
3367 unsigned long flags;
3370 * always blip to get avail list updated, since it's almost
3371 * always needed, and is fairly cheap.
3373 sendctrl_7220_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
3374 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3375 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3379 spin_lock_irqsave(&ppd->sdma_lock, flags);
3380 if (ppd->sdma_state.current_state == qib_sdma_state_s20_idle &&
3381 ppd->sdma_state.current_state != qib_sdma_state_s00_hw_down) {
3382 __qib_sdma_process_event(ppd, qib_sdma_event_e00_go_hw_down);
3386 qib_7220_sdma_hw_clean_up(ppd);
3388 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3391 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3392 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3399 * This code for non-IBTA-compliant IB speed negotiation is only known to
3400 * work for the SDR to DDR transition, and only between an HCA and a switch
3401 * with recent firmware. It is based on observed heuristics, rather than
3402 * actual knowledge of the non-compliant speed negotiation.
3403 * It has a number of hard-coded fields, since the hope is to rewrite this
3404 * when a spec is available on how the negoation is intended to work.
3406 static void autoneg_7220_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
3407 u32 dcnt, u32 *data)
3411 u32 __iomem *piobuf;
3413 struct qib_devdata *dd = ppd->dd;
3416 pbc = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
3417 pbc |= PBC_7220_VL15_SEND;
3418 while (!(piobuf = get_7220_link_buf(ppd, &pnum))) {
3423 sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_DISARM_BUF(pnum));
3424 writeq(pbc, piobuf);
3426 qib_pio_copy(piobuf + 2, hdr, 7);
3427 qib_pio_copy(piobuf + 9, data, dcnt);
3428 if (dd->flags & QIB_USE_SPCL_TRIG) {
3429 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
3432 __raw_writel(0xaebecede, piobuf + spcl_off);
3435 qib_sendbuf_done(dd, pnum);
3439 * _start packet gets sent twice at start, _done gets sent twice at end
3441 static void autoneg_7220_send(struct qib_pportdata *ppd, int which)
3443 struct qib_devdata *dd = ppd->dd;
3445 u32 dw, i, hcnt, dcnt, *data;
3446 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
3447 static u32 madpayload_start[0x40] = {
3448 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
3449 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
3450 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
3452 static u32 madpayload_done[0x40] = {
3453 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
3454 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
3455 0x40000001, 0x1388, 0x15e, /* rest 0's */
3458 dcnt = ARRAY_SIZE(madpayload_start);
3459 hcnt = ARRAY_SIZE(hdr);
3461 /* for maintainability, do it at runtime */
3462 for (i = 0; i < hcnt; i++) {
3463 dw = (__force u32) cpu_to_be32(hdr[i]);
3466 for (i = 0; i < dcnt; i++) {
3467 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
3468 madpayload_start[i] = dw;
3469 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
3470 madpayload_done[i] = dw;
3475 data = which ? madpayload_done : madpayload_start;
3477 autoneg_7220_sendpkt(ppd, hdr, dcnt, data);
3478 qib_read_kreg64(dd, kr_scratch);
3480 autoneg_7220_sendpkt(ppd, hdr, dcnt, data);
3481 qib_read_kreg64(dd, kr_scratch);
3486 * Do the absolute minimum to cause an IB speed change, and make it
3487 * ready, but don't actually trigger the change. The caller will
3488 * do that when ready (if link is in Polling training state, it will
3489 * happen immediately, otherwise when link next goes down)
3491 * This routine should only be used as part of the DDR autonegotation
3492 * code for devices that are not compliant with IB 1.2 (or code that
3493 * fixes things up for same).
3495 * When link has gone down, and autoneg enabled, or autoneg has
3496 * failed and we give up until next time we set both speeds, and
3497 * then we want IBTA enabled as well as "use max enabled speed.
3499 static void set_7220_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
3501 ppd->cpspec->ibcddrctrl &= ~(IBA7220_IBC_SPEED_AUTONEG_MASK |
3502 IBA7220_IBC_IBTA_1_2_MASK);
3504 if (speed == (QIB_IB_SDR | QIB_IB_DDR))
3505 ppd->cpspec->ibcddrctrl |= IBA7220_IBC_SPEED_AUTONEG_MASK |
3506 IBA7220_IBC_IBTA_1_2_MASK;
3508 ppd->cpspec->ibcddrctrl |= speed == QIB_IB_DDR ?
3509 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
3511 qib_write_kreg(ppd->dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
3512 qib_write_kreg(ppd->dd, kr_scratch, 0);
3516 * This routine is only used when we are not talking to another
3517 * IB 1.2-compliant device that we think can do DDR.
3518 * (This includes all existing switch chips as of Oct 2007.)
3519 * 1.2-compliant devices go directly to DDR prior to reaching INIT
3521 static void try_7220_autoneg(struct qib_pportdata *ppd)
3523 unsigned long flags;
3526 * Required for older non-IB1.2 DDR switches. Newer
3527 * non-IB-compliant switches don't need it, but so far,
3528 * aren't bothered by it either. "Magic constant"
3530 qib_write_kreg(ppd->dd, kr_ncmodectrl, 0x3b9dc07);
3532 spin_lock_irqsave(&ppd->lflags_lock, flags);
3533 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
3534 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3535 autoneg_7220_send(ppd, 0);
3536 set_7220_ibspeed_fast(ppd, QIB_IB_DDR);
3538 toggle_7220_rclkrls(ppd->dd);
3539 /* 2 msec is minimum length of a poll cycle */
3540 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
3541 msecs_to_jiffies(2));
3545 * Handle the empirically determined mechanism for auto-negotiation
3546 * of DDR speed with switches.
3548 static void autoneg_7220_work(struct work_struct *work)
3550 struct qib_pportdata *ppd;
3551 struct qib_devdata *dd;
3554 unsigned long flags;
3556 ppd = &container_of(work, struct qib_chippport_specific,
3557 autoneg_work.work)->pportdata;
3560 startms = jiffies_to_msecs(jiffies);
3563 * Busy wait for this first part, it should be at most a
3564 * few hundred usec, since we scheduled ourselves for 2msec.
3566 for (i = 0; i < 25; i++) {
3567 if (SYM_FIELD(ppd->lastibcstat, IBCStatus, LinkTrainingState)
3568 == IB_7220_LT_STATE_POLLQUIET) {
3569 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
3575 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
3576 goto done; /* we got there early or told to stop */
3578 /* we expect this to timeout */
3579 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
3580 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3581 msecs_to_jiffies(90)))
3584 toggle_7220_rclkrls(dd);
3586 /* we expect this to timeout */
3587 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
3588 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3589 msecs_to_jiffies(1700)))
3592 set_7220_ibspeed_fast(ppd, QIB_IB_SDR);
3593 toggle_7220_rclkrls(dd);
3596 * Wait up to 250 msec for link to train and get to INIT at DDR;
3597 * this should terminate early.
3599 wait_event_timeout(ppd->cpspec->autoneg_wait,
3600 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3601 msecs_to_jiffies(250));
3603 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
3604 spin_lock_irqsave(&ppd->lflags_lock, flags);
3605 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
3606 if (dd->cspec->autoneg_tries == AUTONEG_TRIES) {
3607 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
3608 dd->cspec->autoneg_tries = 0;
3610 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3611 set_7220_ibspeed_fast(ppd, ppd->link_speed_enabled);
3615 static u32 qib_7220_iblink_state(u64 ibcs)
3617 u32 state = (u32)SYM_FIELD(ibcs, IBCStatus, LinkState);
3620 case IB_7220_L_STATE_INIT:
3621 state = IB_PORT_INIT;
3623 case IB_7220_L_STATE_ARM:
3624 state = IB_PORT_ARMED;
3626 case IB_7220_L_STATE_ACTIVE:
3628 case IB_7220_L_STATE_ACT_DEFER:
3629 state = IB_PORT_ACTIVE;
3631 default: /* fall through */
3632 case IB_7220_L_STATE_DOWN:
3633 state = IB_PORT_DOWN;
3639 /* returns the IBTA port state, rather than the IBC link training state */
3640 static u8 qib_7220_phys_portstate(u64 ibcs)
3642 u8 state = (u8)SYM_FIELD(ibcs, IBCStatus, LinkTrainingState);
3643 return qib_7220_physportstate[state];
3646 static int qib_7220_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
3648 int ret = 0, symadj = 0;
3649 struct qib_devdata *dd = ppd->dd;
3650 unsigned long flags;
3652 spin_lock_irqsave(&ppd->lflags_lock, flags);
3653 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
3654 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3658 * When the link goes down we don't want AEQ running, so it
3659 * won't interfere with IBC training, etc., and we need
3660 * to go back to the static SerDes preset values.
3662 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
3663 QIBL_IB_AUTONEG_INPROG)))
3664 set_7220_ibspeed_fast(ppd, ppd->link_speed_enabled);
3665 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
3666 qib_sd7220_presets(dd);
3667 qib_cancel_sends(ppd); /* initial disarm, etc. */
3668 spin_lock_irqsave(&ppd->sdma_lock, flags);
3669 if (__qib_sdma_running(ppd))
3670 __qib_sdma_process_event(ppd,
3671 qib_sdma_event_e70_go_idle);
3672 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3674 /* this might better in qib_sd7220_presets() */
3675 set_7220_relock_poll(dd, ibup);
3677 if (qib_compat_ddr_negotiate &&
3678 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
3679 QIBL_IB_AUTONEG_INPROG)) &&
3680 ppd->link_speed_active == QIB_IB_SDR &&
3681 (ppd->link_speed_enabled & (QIB_IB_DDR | QIB_IB_SDR)) ==
3682 (QIB_IB_DDR | QIB_IB_SDR) &&
3683 dd->cspec->autoneg_tries < AUTONEG_TRIES) {
3684 /* we are SDR, and DDR auto-negotiation enabled */
3685 ++dd->cspec->autoneg_tries;
3686 if (!ppd->cpspec->ibdeltainprog) {
3687 ppd->cpspec->ibdeltainprog = 1;
3688 ppd->cpspec->ibsymsnap = read_7220_creg32(dd,
3690 ppd->cpspec->iblnkerrsnap = read_7220_creg32(dd,
3693 try_7220_autoneg(ppd);
3694 ret = 1; /* no other IB status change processing */
3695 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
3696 ppd->link_speed_active == QIB_IB_SDR) {
3697 autoneg_7220_send(ppd, 1);
3698 set_7220_ibspeed_fast(ppd, QIB_IB_DDR);
3700 toggle_7220_rclkrls(dd);
3701 ret = 1; /* no other IB status change processing */
3703 if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
3704 (ppd->link_speed_active & QIB_IB_DDR)) {
3705 spin_lock_irqsave(&ppd->lflags_lock, flags);
3706 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
3707 QIBL_IB_AUTONEG_FAILED);
3708 spin_unlock_irqrestore(&ppd->lflags_lock,
3710 dd->cspec->autoneg_tries = 0;
3711 /* re-enable SDR, for next link down */
3712 set_7220_ibspeed_fast(ppd,
3713 ppd->link_speed_enabled);
3714 wake_up(&ppd->cpspec->autoneg_wait);
3716 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
3718 * Clear autoneg failure flag, and do setup
3719 * so we'll try next time link goes down and
3720 * back to INIT (possibly connected to a
3721 * different device).
3723 spin_lock_irqsave(&ppd->lflags_lock, flags);
3724 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3725 spin_unlock_irqrestore(&ppd->lflags_lock,
3727 ppd->cpspec->ibcddrctrl |=
3728 IBA7220_IBC_IBTA_1_2_MASK;
3729 qib_write_kreg(dd, kr_ncmodectrl, 0);
3734 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
3738 ppd->delay_mult = rate_to_delay
3739 [(ibcs >> IBA7220_LINKSPEED_SHIFT) & 1]
3740 [(ibcs >> IBA7220_LINKWIDTH_SHIFT) & 1];
3742 set_7220_relock_poll(dd, ibup);
3743 spin_lock_irqsave(&ppd->sdma_lock, flags);
3745 * Unlike 7322, the 7220 needs this, due to lack of
3746 * interrupt in some cases when we have sdma active
3747 * when the link goes down.
3749 if (ppd->sdma_state.current_state !=
3750 qib_sdma_state_s20_idle)
3751 __qib_sdma_process_event(ppd,
3752 qib_sdma_event_e00_go_hw_down);
3753 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3758 if (ppd->cpspec->ibdeltainprog) {
3759 ppd->cpspec->ibdeltainprog = 0;
3760 ppd->cpspec->ibsymdelta += read_7220_creg32(ppd->dd,
3761 cr_ibsymbolerr) - ppd->cpspec->ibsymsnap;
3762 ppd->cpspec->iblnkerrdelta += read_7220_creg32(ppd->dd,
3763 cr_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
3765 } else if (!ibup && qib_compat_ddr_negotiate &&
3766 !ppd->cpspec->ibdeltainprog &&
3767 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
3768 ppd->cpspec->ibdeltainprog = 1;
3769 ppd->cpspec->ibsymsnap = read_7220_creg32(ppd->dd,
3771 ppd->cpspec->iblnkerrsnap = read_7220_creg32(ppd->dd,
3776 qib_setup_7220_setextled(ppd, ibup);
3781 * Does read/modify/write to appropriate registers to
3782 * set output and direction bits selected by mask.
3783 * these are in their canonical postions (e.g. lsb of
3784 * dir will end up in D48 of extctrl on existing chips).
3785 * returns contents of GP Inputs.
3787 static int gpio_7220_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
3789 u64 read_val, new_out;
3790 unsigned long flags;
3793 /* some bits being written, lock access to GPIO */
3796 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3797 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3798 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3799 new_out = (dd->cspec->gpio_out & ~mask) | out;
3801 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3802 qib_write_kreg(dd, kr_gpio_out, new_out);
3803 dd->cspec->gpio_out = new_out;
3804 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3807 * It is unlikely that a read at this time would get valid
3808 * data on a pin whose direction line was set in the same
3809 * call to this function. We include the read here because
3810 * that allows us to potentially combine a change on one pin with
3811 * a read on another, and because the old code did something like
3814 read_val = qib_read_kreg64(dd, kr_extstatus);
3815 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
3819 * Read fundamental info we need to use the chip. These are
3820 * the registers that describe chip capabilities, and are
3821 * saved in shadow registers.
3823 static void get_7220_chip_params(struct qib_devdata *dd)
3829 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
3831 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
3832 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
3833 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
3834 dd->palign = qib_read_kreg32(dd, kr_palign);
3835 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3836 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
3838 val = qib_read_kreg64(dd, kr_sendpiosize);
3839 dd->piosize2k = val & ~0U;
3840 dd->piosize4k = val >> 32;
3842 mtu = ib_mtu_enum_to_int(qib_ibmtu);
3844 mtu = QIB_DEFAULT_MTU;
3845 dd->pport->ibmtu = (u32)mtu;
3847 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3848 dd->piobcnt2k = val & ~0U;
3849 dd->piobcnt4k = val >> 32;
3850 /* these may be adjusted in init_chip_wc_pat() */
3851 dd->pio2kbase = (u32 __iomem *)
3852 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
3853 if (dd->piobcnt4k) {
3854 dd->pio4kbase = (u32 __iomem *)
3855 ((char __iomem *) dd->kregbase +
3856 (dd->piobufbase >> 32));
3858 * 4K buffers take 2 pages; we use roundup just to be
3859 * paranoid; we calculate it once here, rather than on
3862 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
3865 piobufs = dd->piobcnt4k + dd->piobcnt2k;
3867 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
3868 (sizeof(u64) * BITS_PER_BYTE / 2);
3872 * The chip base addresses in cspec and cpspec have to be set
3873 * after possible init_chip_wc_pat(), rather than in
3874 * qib_get_7220_chip_params(), so split out as separate function
3876 static void set_7220_baseaddrs(struct qib_devdata *dd)
3879 /* init after possible re-map in init_chip_wc_pat() */
3880 cregbase = qib_read_kreg32(dd, kr_counterregbase);
3881 dd->cspec->cregbase = (u64 __iomem *)
3882 ((char __iomem *) dd->kregbase + cregbase);
3884 dd->egrtidbase = (u64 __iomem *)
3885 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
3889 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl, SendIntBufAvail) | \
3890 SYM_MASK(SendCtrl, SPioEnable) | \
3891 SYM_MASK(SendCtrl, SSpecialTriggerEn) | \
3892 SYM_MASK(SendCtrl, SendBufAvailUpd) | \
3893 SYM_MASK(SendCtrl, AvailUpdThld) | \
3894 SYM_MASK(SendCtrl, SDmaEnable) | \
3895 SYM_MASK(SendCtrl, SDmaIntEnable) | \
3896 SYM_MASK(SendCtrl, SDmaHalt) | \
3897 SYM_MASK(SendCtrl, SDmaSingleDescriptor))
3899 static int sendctrl_hook(struct qib_devdata *dd,
3900 const struct diag_observer *op,
3901 u32 offs, u64 *data, u64 mask, int only_32)
3903 unsigned long flags;
3904 unsigned idx = offs / sizeof(u64);
3905 u64 local_data, all_bits;
3907 if (idx != kr_sendctrl) {
3908 qib_dev_err(dd, "SendCtrl Hook called with offs %X, %s-bit\n",
3909 offs, only_32 ? "32" : "64");
3916 spin_lock_irqsave(&dd->sendctrl_lock, flags);
3917 if ((mask & all_bits) != all_bits) {
3919 * At least some mask bits are zero, so we need
3920 * to read. The judgement call is whether from
3921 * reg or shadow. First-cut: read reg, and complain
3922 * if any bits which should be shadowed are different
3923 * from their shadowed value.
3926 local_data = (u64)qib_read_kreg32(dd, idx);
3928 local_data = qib_read_kreg64(dd, idx);
3929 qib_dev_err(dd, "Sendctrl -> %X, Shad -> %X\n",
3930 (u32)local_data, (u32)dd->sendctrl);
3931 if ((local_data & SENDCTRL_SHADOWED) !=
3932 (dd->sendctrl & SENDCTRL_SHADOWED))
3933 qib_dev_err(dd, "Sendctrl read: %X shadow is %X\n",
3934 (u32)local_data, (u32) dd->sendctrl);
3935 *data = (local_data & ~mask) | (*data & mask);
3939 * At least some mask bits are one, so we need
3940 * to write, but only shadow some bits.
3942 u64 sval, tval; /* Shadowed, transient */
3945 * New shadow val is bits we don't want to touch,
3946 * ORed with bits we do, that are intended for shadow.
3948 sval = (dd->sendctrl & ~mask);
3949 sval |= *data & SENDCTRL_SHADOWED & mask;
3950 dd->sendctrl = sval;
3951 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
3952 qib_dev_err(dd, "Sendctrl <- %X, Shad <- %X\n",
3953 (u32)tval, (u32)sval);
3954 qib_write_kreg(dd, kr_sendctrl, tval);
3955 qib_write_kreg(dd, kr_scratch, 0Ull);
3957 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
3959 return only_32 ? 4 : 8;
3962 static const struct diag_observer sendctrl_observer = {
3963 sendctrl_hook, kr_sendctrl * sizeof(u64),
3964 kr_sendctrl * sizeof(u64)
3968 * write the final few registers that depend on some of the
3969 * init setup. Done late in init, just before bringing up
3972 static int qib_late_7220_initreg(struct qib_devdata *dd)
3977 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
3978 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
3979 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
3980 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
3981 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3982 if (val != dd->pioavailregs_phys) {
3983 qib_dev_err(dd, "Catastrophic software error, "
3984 "SendPIOAvailAddr written as %lx, "
3985 "read back as %llx\n",
3986 (unsigned long) dd->pioavailregs_phys,
3987 (unsigned long long) val);
3990 qib_register_observer(dd, &sendctrl_observer);
3994 static int qib_init_7220_variables(struct qib_devdata *dd)
3996 struct qib_chippport_specific *cpspec;
3997 struct qib_pportdata *ppd;
3999 u32 sbufs, updthresh;
4001 cpspec = (struct qib_chippport_specific *)(dd + 1);
4002 ppd = &cpspec->pportdata;
4006 dd->cspec = (struct qib_chip_specific *)(cpspec + dd->num_pports);
4007 ppd->cpspec = cpspec;
4009 spin_lock_init(&dd->cspec->sdepb_lock);
4010 spin_lock_init(&dd->cspec->rcvmod_lock);
4011 spin_lock_init(&dd->cspec->gpio_lock);
4013 /* we haven't yet set QIB_PRESENT, so use read directly */
4014 dd->revision = readq(&dd->kregbase[kr_revision]);
4016 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
4017 qib_dev_err(dd, "Revision register read failure, "
4018 "giving up initialization\n");
4022 dd->flags |= QIB_PRESENT; /* now register routines work */
4024 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R,
4026 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R,
4029 get_7220_chip_params(dd);
4030 qib_7220_boardname(dd);
4033 * GPIO bits for TWSI data and clock,
4034 * used for serial EEPROM.
4036 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
4037 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
4038 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
4040 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
4041 QIB_NODMA_RTAIL | QIB_HAS_THRESH_UPDATE;
4042 dd->flags |= qib_special_trigger ?
4043 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
4046 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
4047 * 2 is Some Misc, 3 is reserved for future.
4049 dd->eep_st_masks[0].hwerrs_to_log = HWE_MASK(TXEMemParityErr);
4051 dd->eep_st_masks[1].hwerrs_to_log = HWE_MASK(RXEMemParityErr);
4053 dd->eep_st_masks[2].errs_to_log = ERR_MASK(ResetNegated);
4055 init_waitqueue_head(&cpspec->autoneg_wait);
4056 INIT_DELAYED_WORK(&cpspec->autoneg_work, autoneg_7220_work);
4058 qib_init_pportdata(ppd, dd, 0, 1);
4059 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
4060 ppd->link_speed_supported = QIB_IB_SDR | QIB_IB_DDR;
4062 ppd->link_width_enabled = ppd->link_width_supported;
4063 ppd->link_speed_enabled = ppd->link_speed_supported;
4065 * Set the initial values to reasonable default, will be set
4066 * for real when link is up.
4068 ppd->link_width_active = IB_WIDTH_4X;
4069 ppd->link_speed_active = QIB_IB_SDR;
4070 ppd->delay_mult = rate_to_delay[0][1];
4071 ppd->vls_supported = IB_VL_VL0;
4072 ppd->vls_operational = ppd->vls_supported;
4075 qib_write_kreg(dd, kr_rcvbthqp, QIB_KD_QP);
4077 init_timer(&ppd->cpspec->chase_timer);
4078 ppd->cpspec->chase_timer.function = reenable_7220_chase;
4079 ppd->cpspec->chase_timer.data = (unsigned long)ppd;
4081 qib_num_cfg_vls = 1; /* if any 7220's, only one VL */
4083 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
4084 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
4086 dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
4088 /* we always allocate at least 2048 bytes for eager buffers */
4089 ret = ib_mtu_enum_to_int(qib_ibmtu);
4090 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU;
4091 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
4092 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
4094 qib_7220_tidtemplate(dd);
4097 * We can request a receive interrupt for 1 or
4098 * more packets from current offset. For now, we set this
4099 * up for a single packet.
4101 dd->rhdrhead_intr_off = 1ULL << 32;
4103 /* setup the stats timer; the add_timer is done at end of init */
4104 init_timer(&dd->stats_timer);
4105 dd->stats_timer.function = qib_get_7220_faststats;
4106 dd->stats_timer.data = (unsigned long) dd;
4107 dd->stats_timer.expires = jiffies + ACTIVITY_TIMER * HZ;
4110 * Control[4] has been added to change the arbitration within
4111 * the SDMA engine between favoring data fetches over descriptor
4112 * fetches. qib_sdma_fetch_arb==0 gives data fetches priority.
4114 if (qib_sdma_fetch_arb)
4115 dd->control |= 1 << 4;
4117 dd->ureg_align = 0x10000; /* 64KB alignment */
4119 dd->piosize2kmax_dwords = (dd->piosize2k >> 2)-1;
4120 qib_7220_config_ctxts(dd);
4121 qib_set_ctxtcnt(dd); /* needed for PAT setup */
4124 ret = init_chip_wc_pat(dd, 0);
4128 set_7220_baseaddrs(dd); /* set chip access pointers now */
4134 ret = qib_create_ctxts(dd);
4135 init_7220_cntrnames(dd);
4137 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
4138 * reserve the update threshold amount for other kernel use, such
4139 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
4140 * unless we aren't enabling SDMA, in which case we want to use
4141 * all the 4k bufs for the kernel.
4142 * if this was less than the update threshold, we could wait
4143 * a long time for an update. Coded this way because we
4144 * sometimes change the update threshold for various reasons,
4145 * and we want this to remain robust.
4147 updthresh = 8U; /* update threshold */
4148 if (dd->flags & QIB_HAS_SEND_DMA) {
4149 dd->cspec->sdmabufcnt = dd->piobcnt4k;
4150 sbufs = updthresh > 3 ? updthresh : 3;
4152 dd->cspec->sdmabufcnt = 0;
4153 sbufs = dd->piobcnt4k;
4156 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
4157 dd->cspec->sdmabufcnt;
4158 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
4159 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
4160 dd->last_pio = dd->cspec->lastbuf_for_pio;
4161 dd->pbufsctxt = dd->lastctxt_piobuf /
4162 (dd->cfgctxts - dd->first_user_ctxt);
4165 * if we are at 16 user contexts, we will have one 7 sbufs
4166 * per context, so drop the update threshold to match. We
4167 * want to update before we actually run out, at low pbufs/ctxt
4168 * so give ourselves some margin
4170 if ((dd->pbufsctxt - 2) < updthresh)
4171 updthresh = dd->pbufsctxt - 2;
4173 dd->cspec->updthresh_dflt = updthresh;
4174 dd->cspec->updthresh = updthresh;
4176 /* before full enable, no interrupts, no locking needed */
4177 dd->sendctrl |= (updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
4178 << SYM_LSB(SendCtrl, AvailUpdThld);
4180 dd->psxmitwait_supported = 1;
4181 dd->psxmitwait_check_rate = QIB_7220_PSXMITWAIT_CHECK_RATE;
4186 static u32 __iomem *qib_7220_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
4189 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
4190 struct qib_devdata *dd = ppd->dd;
4193 if (((pbc >> 32) & PBC_7220_VL15_SEND_CTRL) &&
4194 !(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE)))
4195 buf = get_7220_link_buf(ppd, pbufnum);
4197 if ((plen + 1) > dd->piosize2kmax_dwords)
4198 first = dd->piobcnt2k;
4201 /* try 4k if all 2k busy, so same last for both sizes */
4202 last = dd->cspec->lastbuf_for_pio;
4203 buf = qib_getsendbuf_range(dd, pbufnum, first, last);
4208 /* these 2 "counters" are really control registers, and are always RW */
4209 static void qib_set_cntr_7220_sample(struct qib_pportdata *ppd, u32 intv,
4212 write_7220_creg(ppd->dd, cr_psinterval, intv);
4213 write_7220_creg(ppd->dd, cr_psstart, start);
4217 * NOTE: no real attempt is made to generalize the SDMA stuff.
4218 * At some point "soon" we will have a new more generalized
4219 * set of sdma interface, and then we'll clean this up.
4222 /* Must be called with sdma_lock held, or before init finished */
4223 static void qib_sdma_update_7220_tail(struct qib_pportdata *ppd, u16 tail)
4225 /* Commit writes to memory and advance the tail on the chip */
4227 ppd->sdma_descq_tail = tail;
4228 qib_write_kreg(ppd->dd, kr_senddmatail, tail);
4231 static void qib_sdma_set_7220_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
4235 static struct sdma_set_state_action sdma_7220_action_table[] = {
4236 [qib_sdma_state_s00_hw_down] = {
4240 .go_s99_running_tofalse = 1,
4242 [qib_sdma_state_s10_hw_start_up_wait] = {
4247 [qib_sdma_state_s20_idle] = {
4252 [qib_sdma_state_s30_sw_clean_up_wait] = {
4257 [qib_sdma_state_s40_hw_clean_up_wait] = {
4262 [qib_sdma_state_s50_hw_halt_wait] = {
4267 [qib_sdma_state_s99_running] = {
4271 .go_s99_running_totrue = 1,
4275 static void qib_7220_sdma_init_early(struct qib_pportdata *ppd)
4277 ppd->sdma_state.set_state_action = sdma_7220_action_table;
4280 static int init_sdma_7220_regs(struct qib_pportdata *ppd)
4282 struct qib_devdata *dd = ppd->dd;
4284 u64 senddmabufmask[3] = { 0 };
4286 /* Set SendDmaBase */
4287 qib_write_kreg(dd, kr_senddmabase, ppd->sdma_descq_phys);
4288 qib_sdma_7220_setlengen(ppd);
4289 qib_sdma_update_7220_tail(ppd, 0); /* Set SendDmaTail */
4290 /* Set SendDmaHeadAddr */
4291 qib_write_kreg(dd, kr_senddmaheadaddr, ppd->sdma_head_phys);
4294 * Reserve all the former "kernel" piobufs, using high number range
4295 * so we get as many 4K buffers as possible
4297 n = dd->piobcnt2k + dd->piobcnt4k;
4298 i = n - dd->cspec->sdmabufcnt;
4300 for (; i < n; ++i) {
4301 unsigned word = i / 64;
4302 unsigned bit = i & 63;
4305 senddmabufmask[word] |= 1ULL << bit;
4307 qib_write_kreg(dd, kr_senddmabufmask0, senddmabufmask[0]);
4308 qib_write_kreg(dd, kr_senddmabufmask1, senddmabufmask[1]);
4309 qib_write_kreg(dd, kr_senddmabufmask2, senddmabufmask[2]);
4311 ppd->sdma_state.first_sendbuf = i;
4312 ppd->sdma_state.last_sendbuf = n;
4317 /* sdma_lock must be held */
4318 static u16 qib_sdma_7220_gethead(struct qib_pportdata *ppd)
4320 struct qib_devdata *dd = ppd->dd;
4328 use_dmahead = __qib_sdma_running(ppd) &&
4329 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
4331 hwhead = use_dmahead ?
4332 (u16)le64_to_cpu(*ppd->sdma_head_dma) :
4333 (u16)qib_read_kreg32(dd, kr_senddmahead);
4335 swhead = ppd->sdma_descq_head;
4336 swtail = ppd->sdma_descq_tail;
4337 cnt = ppd->sdma_descq_cnt;
4339 if (swhead < swtail) {
4341 sane = (hwhead >= swhead) & (hwhead <= swtail);
4342 } else if (swhead > swtail) {
4343 /* wrapped around */
4344 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
4348 sane = (hwhead == swhead);
4351 if (unlikely(!sane)) {
4353 /* try one more time, directly from the register */
4357 /* assume no progress */
4364 static int qib_sdma_7220_busy(struct qib_pportdata *ppd)
4366 u64 hwstatus = qib_read_kreg64(ppd->dd, kr_senddmastatus);
4368 return (hwstatus & SYM_MASK(SendDmaStatus, ScoreBoardDrainInProg)) ||
4369 (hwstatus & SYM_MASK(SendDmaStatus, AbortInProg)) ||
4370 (hwstatus & SYM_MASK(SendDmaStatus, InternalSDmaEnable)) ||
4371 !(hwstatus & SYM_MASK(SendDmaStatus, ScbEmpty));
4375 * Compute the amount of delay before sending the next packet if the
4376 * port's send rate differs from the static rate set for the QP.
4377 * Since the delay affects this packet but the amount of the delay is
4378 * based on the length of the previous packet, use the last delay computed
4379 * and save the delay count for this packet to be used next time
4382 static u32 qib_7220_setpbc_control(struct qib_pportdata *ppd, u32 plen,
4385 u8 snd_mult = ppd->delay_mult;
4386 u8 rcv_mult = ib_rate_to_delay[srate];
4387 u32 ret = ppd->cpspec->last_delay_mult;
4389 ppd->cpspec->last_delay_mult = (rcv_mult > snd_mult) ?
4390 (plen * (rcv_mult - snd_mult) + 1) >> 1 : 0;
4392 /* Indicate VL15, if necessary */
4394 ret |= PBC_7220_VL15_SEND_CTRL;
4398 static void qib_7220_initvl15_bufs(struct qib_devdata *dd)
4402 static void qib_7220_init_ctxt(struct qib_ctxtdata *rcd)
4405 rcd->rcvegrcnt = IBA7220_KRCVEGRCNT;
4406 rcd->rcvegr_tid_base = 0;
4408 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
4409 rcd->rcvegr_tid_base = IBA7220_KRCVEGRCNT +
4410 (rcd->ctxt - 1) * rcd->rcvegrcnt;
4414 static void qib_7220_txchk_change(struct qib_devdata *dd, u32 start,
4415 u32 len, u32 which, struct qib_ctxtdata *rcd)
4418 unsigned long flags;
4421 case TXCHK_CHG_TYPE_KERN:
4422 /* see if we need to raise avail update threshold */
4423 spin_lock_irqsave(&dd->uctxt_lock, flags);
4424 for (i = dd->first_user_ctxt;
4425 dd->cspec->updthresh != dd->cspec->updthresh_dflt
4426 && i < dd->cfgctxts; i++)
4427 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
4428 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
4429 < dd->cspec->updthresh_dflt)
4431 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
4432 if (i == dd->cfgctxts) {
4433 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4434 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
4435 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
4436 dd->sendctrl |= (dd->cspec->updthresh &
4437 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
4438 SYM_LSB(SendCtrl, AvailUpdThld);
4439 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4440 sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
4443 case TXCHK_CHG_TYPE_USER:
4444 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4445 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
4446 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
4447 dd->cspec->updthresh = (rcd->piocnt /
4448 rcd->subctxt_cnt) - 1;
4449 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
4450 dd->sendctrl |= (dd->cspec->updthresh &
4451 SYM_RMASK(SendCtrl, AvailUpdThld))
4452 << SYM_LSB(SendCtrl, AvailUpdThld);
4453 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4454 sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
4456 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4461 static void writescratch(struct qib_devdata *dd, u32 val)
4463 qib_write_kreg(dd, kr_scratch, val);
4466 #define VALID_TS_RD_REG_MASK 0xBF
4468 * qib_7220_tempsense_read - read register of temp sensor via TWSI
4469 * @dd: the qlogic_ib device
4470 * @regnum: register to read from
4472 * returns reg contents (0..255) or < 0 for error
4474 static int qib_7220_tempsense_rd(struct qib_devdata *dd, int regnum)
4484 /* return a bogus value for (the one) register we do not have */
4485 if (!((1 << regnum) & VALID_TS_RD_REG_MASK)) {
4490 ret = mutex_lock_interruptible(&dd->eep_lock);
4494 ret = qib_twsi_blk_rd(dd, QIB_TWSI_TEMP_DEV, regnum, &rdata, 1);
4498 mutex_unlock(&dd->eep_lock);
4501 * There are three possibilities here:
4502 * ret is actual value (0..255)
4503 * ret is -ENXIO or -EINVAL from twsi code or this file
4504 * ret is -EINTR from mutex_lock_interruptible.
4510 /* Dummy function, as 7220 boards never disable EEPROM Write */
4511 static int qib_7220_eeprom_wen(struct qib_devdata *dd, int wen)
4517 * qib_init_iba7220_funcs - set up the chip-specific function pointers
4518 * @dev: the pci_dev for qlogic_ib device
4519 * @ent: pci_device_id struct for this dev
4521 * This is global, and is called directly at init to set up the
4522 * chip-specific function pointers for later use.
4524 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *pdev,
4525 const struct pci_device_id *ent)
4527 struct qib_devdata *dd;
4529 u32 boardid, minwidth;
4531 dd = qib_alloc_devdata(pdev, sizeof(struct qib_chip_specific) +
4532 sizeof(struct qib_chippport_specific));
4536 dd->f_bringup_serdes = qib_7220_bringup_serdes;
4537 dd->f_cleanup = qib_setup_7220_cleanup;
4538 dd->f_clear_tids = qib_7220_clear_tids;
4539 dd->f_free_irq = qib_7220_free_irq;
4540 dd->f_get_base_info = qib_7220_get_base_info;
4541 dd->f_get_msgheader = qib_7220_get_msgheader;
4542 dd->f_getsendbuf = qib_7220_getsendbuf;
4543 dd->f_gpio_mod = gpio_7220_mod;
4544 dd->f_eeprom_wen = qib_7220_eeprom_wen;
4545 dd->f_hdrqempty = qib_7220_hdrqempty;
4546 dd->f_ib_updown = qib_7220_ib_updown;
4547 dd->f_init_ctxt = qib_7220_init_ctxt;
4548 dd->f_initvl15_bufs = qib_7220_initvl15_bufs;
4549 dd->f_intr_fallback = qib_7220_intr_fallback;
4550 dd->f_late_initreg = qib_late_7220_initreg;
4551 dd->f_setpbc_control = qib_7220_setpbc_control;
4552 dd->f_portcntr = qib_portcntr_7220;
4553 dd->f_put_tid = qib_7220_put_tid;
4554 dd->f_quiet_serdes = qib_7220_quiet_serdes;
4555 dd->f_rcvctrl = rcvctrl_7220_mod;
4556 dd->f_read_cntrs = qib_read_7220cntrs;
4557 dd->f_read_portcntrs = qib_read_7220portcntrs;
4558 dd->f_reset = qib_setup_7220_reset;
4559 dd->f_init_sdma_regs = init_sdma_7220_regs;
4560 dd->f_sdma_busy = qib_sdma_7220_busy;
4561 dd->f_sdma_gethead = qib_sdma_7220_gethead;
4562 dd->f_sdma_sendctrl = qib_7220_sdma_sendctrl;
4563 dd->f_sdma_set_desc_cnt = qib_sdma_set_7220_desc_cnt;
4564 dd->f_sdma_update_tail = qib_sdma_update_7220_tail;
4565 dd->f_sdma_hw_clean_up = qib_7220_sdma_hw_clean_up;
4566 dd->f_sdma_hw_start_up = qib_7220_sdma_hw_start_up;
4567 dd->f_sdma_init_early = qib_7220_sdma_init_early;
4568 dd->f_sendctrl = sendctrl_7220_mod;
4569 dd->f_set_armlaunch = qib_set_7220_armlaunch;
4570 dd->f_set_cntr_sample = qib_set_cntr_7220_sample;
4571 dd->f_iblink_state = qib_7220_iblink_state;
4572 dd->f_ibphys_portstate = qib_7220_phys_portstate;
4573 dd->f_get_ib_cfg = qib_7220_get_ib_cfg;
4574 dd->f_set_ib_cfg = qib_7220_set_ib_cfg;
4575 dd->f_set_ib_loopback = qib_7220_set_loopback;
4576 dd->f_set_intr_state = qib_7220_set_intr_state;
4577 dd->f_setextled = qib_setup_7220_setextled;
4578 dd->f_txchk_change = qib_7220_txchk_change;
4579 dd->f_update_usrhead = qib_update_7220_usrhead;
4580 dd->f_wantpiobuf_intr = qib_wantpiobuf_7220_intr;
4581 dd->f_xgxs_reset = qib_7220_xgxs_reset;
4582 dd->f_writescratch = writescratch;
4583 dd->f_tempsense_rd = qib_7220_tempsense_rd;
4585 * Do remaining pcie setup and save pcie values in dd.
4586 * Any error printing is already done by the init code.
4587 * On return, we have the chip mapped, but chip registers
4588 * are not set up until start of qib_init_7220_variables.
4590 ret = qib_pcie_ddinit(dd, pdev, ent);
4594 /* initialize chip-specific variables */
4595 ret = qib_init_7220_variables(dd);
4602 boardid = SYM_FIELD(dd->revision, Revision,
4609 minwidth = 16; /* x16 capable boards */
4612 minwidth = 8; /* x8 capable boards */
4615 if (qib_pcie_params(dd, minwidth, NULL, NULL))
4616 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
4617 "continuing anyway\n");
4619 /* save IRQ for possible later use */
4620 dd->cspec->irq = pdev->irq;
4622 if (qib_read_kreg64(dd, kr_hwerrstatus) &
4623 QLOGIC_IB_HWE_SERDESPLLFAILED)
4624 qib_write_kreg(dd, kr_hwerrclear,
4625 QLOGIC_IB_HWE_SERDESPLLFAILED);
4627 /* setup interrupt handler (interrupt type handled above) */
4628 qib_setup_7220_interrupt(dd);
4629 qib_7220_init_hwerrors(dd);
4631 /* clear diagctrl register, in case diags were running and crashed */
4632 qib_write_kreg(dd, kr_hwdiagctrl, 0);
4637 qib_pcie_ddcleanup(dd);
4639 qib_free_devdata(dd);
projects / firefly-linux-kernel-4.4.55.git / blob