1 /******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
3 * File Name : lis3dh_acc.c
4 * Authors : MSH - Motion Mems BU - Application Team
5 * : Carmine Iascone (carmine.iascone@st.com)
6 * : Matteo Dameno (matteo.dameno@st.com)
9 * Description : LIS3DH accelerometer sensor API
11 *******************************************************************************
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
17 * THE PRESENT SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES
18 * OR CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED, FOR THE SOLE
19 * PURPOSE TO SUPPORT YOUR APPLICATION DEVELOPMENT.
20 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
21 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
22 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
23 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
25 * THIS SOFTWARE IS SPECIFICALLY DESIGNED FOR EXCLUSIVE USE WITH ST PARTS.
27 ******************************************************************************
28 Revision 1.0.0 05/11/09
30 Revision 1.0.3 22/01/2010
31 Linux K&R Compliant Release;
32 Revision 1.0.5 16/08/2010
33 modified _get_acceleration_data function
34 modified _update_odr function
37 ******************************************************************************/
39 #include <linux/err.h>
40 #include <linux/errno.h>
41 #include <linux/delay.h>
43 #include <linux/i2c.h>
45 #include <linux/input.h>
46 #include <linux/input-polldev.h>
47 #include <linux/miscdevice.h>
48 #include <linux/uaccess.h>
50 #include <linux/workqueue.h>
51 #include <linux/irq.h>
52 #include <linux/gpio.h>
53 #include <linux/interrupt.h>
55 //#include <linux/i2c/lis3dh.h>
56 #include "lis3dh_acc_misc.h"
61 #define INTERRUPT_MANAGEMENT 1
63 #define G_MAX 16000 /** Maximum polled-device-reported g value */
66 #define SHIFT_ADJ_2G 4
67 #define SHIFT_ADJ_4G 3
68 #define SHIFT_ADJ_8G 2
69 #define SHIFT_ADJ_16G 1
72 #define SENSITIVITY_2G 1 /** mg/LSB */
73 #define SENSITIVITY_4G 2 /** mg/LSB */
74 #define SENSITIVITY_8G 4 /** mg/LSB */
75 #define SENSITIVITY_16G 12 /** mg/LSB */
78 #define HIGH_RESOLUTION 0x08
80 #define AXISDATA_REG 0x28
81 #define WHOAMI_LIS3DH_ACC 0x33 /* Expctd content for WAI */
83 /* CONTROL REGISTERS */
84 #define WHO_AM_I 0x0F /* WhoAmI register */
85 #define TEMP_CFG_REG 0x1F /* temper sens control reg */
86 /* ctrl 1: ODR3 ODR2 ODR ODR0 LPen Zenable Yenable Zenable */
87 #define CTRL_REG1 0x20 /* control reg 1 */
88 #define CTRL_REG2 0x21 /* control reg 2 */
89 #define CTRL_REG3 0x22 /* control reg 3 */
90 #define CTRL_REG4 0x23 /* control reg 4 */
91 #define CTRL_REG5 0x24 /* control reg 5 */
92 #define CTRL_REG6 0x25 /* control reg 6 */
94 #define FIFO_CTRL_REG 0x2E /* FiFo control reg */
96 #define INT_CFG1 0x30 /* interrupt 1 config */
97 #define INT_SRC1 0x31 /* interrupt 1 source */
98 #define INT_THS1 0x32 /* interrupt 1 threshold */
99 #define INT_DUR1 0x33 /* interrupt 1 duration */
101 #define INT_CFG2 0x34 /* interrupt 2 config */
102 #define INT_SRC2 0x35 /* interrupt 2 source */
103 #define INT_THS2 0x36 /* interrupt 2 threshold */
104 #define INT_DUR2 0x37 /* interrupt 2 duration */
106 #define TT_CFG 0x38 /* tap config */
107 #define TT_SRC 0x39 /* tap source */
108 #define TT_THS 0x3A /* tap threshold */
109 #define TT_LIM 0x3B /* tap time limit */
110 #define TT_TLAT 0x3C /* tap time latency */
111 #define TT_TW 0x3D /* tap time window */
112 /* end CONTROL REGISTRES */
115 #define ENABLE_HIGH_RESOLUTION 1
117 #define LIS3DH_ACC_PM_OFF 0x00
118 #define LIS3DH_ACC_ENABLE_ALL_AXES 0x07
120 #define PMODE_MASK 0x08
121 #define ODR_MASK 0XF0
123 #define ODR1 0x10 /* 1Hz output data rate */
124 #define ODR10 0x20 /* 10Hz output data rate */
125 #define ODR25 0x30 /* 25Hz output data rate */
126 #define ODR50 0x40 /* 50Hz output data rate */
127 #define ODR100 0x50 /* 100Hz output data rate */
128 #define ODR200 0x60 /* 200Hz output data rate */
129 #define ODR400 0x70 /* 400Hz output data rate */
130 #define ODR1250 0x90 /* 1250Hz output data rate */
143 #define CTRL_REG3_I1_AOI1 0x40
144 #define CTRL_REG6_I2_TAPEN 0x80
145 #define CTRL_REG6_HLACTIVE 0x02
148 /* TAP_SOURCE_REG BIT */
159 #define I2C_RETRY_DELAY 5
160 #define I2C_RETRIES 5
161 #define I2C_AUTO_INCREMENT 0x80
163 /* RESUME STATE INDICES */
164 #define RES_CTRL_REG1 0
165 #define RES_CTRL_REG2 1
166 #define RES_CTRL_REG3 2
167 #define RES_CTRL_REG4 3
168 #define RES_CTRL_REG5 4
169 #define RES_CTRL_REG6 5
171 #define RES_INT_CFG1 6
172 #define RES_INT_THS1 7
173 #define RES_INT_DUR1 8
174 #define RES_INT_CFG2 9
175 #define RES_INT_THS2 10
176 #define RES_INT_DUR2 11
178 #define RES_TT_CFG 12
179 #define RES_TT_THS 13
180 #define RES_TT_LIM 14
181 #define RES_TT_TLAT 15
184 #define RES_TEMP_CFG_REG 17
185 #define RES_REFERENCE_REG 18
186 #define RES_FIFO_CTRL_REG 19
188 #define RESUME_ENTRIES 20
189 /* end RESUME STATE INDICES */
192 unsigned int cutoff_ms;
194 } lis3dh_acc_odr_table[] = {
205 struct lis3dh_acc_data {
206 struct i2c_client *client;
207 struct lis3dh_acc_platform_data *pdata;
210 struct delayed_work input_work;
212 struct input_dev *input_dev;
215 /* hw_working=-1 means not tested yet */
218 int on_before_suspend;
222 u8 resume_state[RESUME_ENTRIES];
225 struct work_struct irq1_work;
226 struct workqueue_struct *irq1_work_queue;
228 struct work_struct irq2_work;
229 struct workqueue_struct *irq2_work_queue;
233 * Because misc devices can not carry a pointer from driver register to
234 * open, we keep this global. This limits the driver to a single instance.
236 struct lis3dh_acc_data *lis3dh_acc_misc_data;
238 static int lis3dh_acc_i2c_read(struct lis3dh_acc_data *acc, u8 * buf, int len)
243 struct i2c_msg msgs[] = {
245 .addr = acc->client->addr,
246 .flags = acc->client->flags & I2C_M_TEN,
250 .addr = acc->client->addr,
251 .flags = (acc->client->flags & I2C_M_TEN) | I2C_M_RD,
257 err = i2c_transfer(acc->client->adapter, msgs, 2);
259 msleep_interruptible(I2C_RETRY_DELAY);
260 } while ((err != 2) && (++tries < I2C_RETRIES));
263 dev_err(&acc->client->dev, "read transfer error\n");
272 static int lis3dh_acc_i2c_write(struct lis3dh_acc_data *acc, u8 * buf, int len)
277 struct i2c_msg msgs[] = { { .addr = acc->client->addr,
278 .flags = acc->client->flags & I2C_M_TEN,
279 .len = len + 1, .buf = buf, }, };
281 err = i2c_transfer(acc->client->adapter, msgs, 1);
283 msleep_interruptible(I2C_RETRY_DELAY);
284 } while ((err != 1) && (++tries < I2C_RETRIES));
287 dev_err(&acc->client->dev, "write transfer error\n");
296 static int lis3dh_acc_hw_init(struct lis3dh_acc_data *acc)
301 printk(KERN_INFO "%s: hw init start\n", LIS3DH_ACC_DEV_NAME);
304 err = lis3dh_acc_i2c_read(acc, buf, 1);
306 goto error_firstread;
309 if (buf[0] != WHOAMI_LIS3DH_ACC) {
310 err = -1; /* choose the right coded error */
311 goto error_unknown_device;
315 buf[1] = acc->resume_state[RES_CTRL_REG1];
316 err = lis3dh_acc_i2c_write(acc, buf, 1);
320 buf[0] = TEMP_CFG_REG;
321 buf[1] = acc->resume_state[RES_TEMP_CFG_REG];
322 err = lis3dh_acc_i2c_write(acc, buf, 1);
326 buf[0] = FIFO_CTRL_REG;
327 buf[1] = acc->resume_state[RES_FIFO_CTRL_REG];
328 err = lis3dh_acc_i2c_write(acc, buf, 1);
332 buf[0] = (I2C_AUTO_INCREMENT | TT_THS);
333 buf[1] = acc->resume_state[RES_TT_THS];
334 buf[2] = acc->resume_state[RES_TT_LIM];
335 buf[3] = acc->resume_state[RES_TT_TLAT];
336 buf[4] = acc->resume_state[RES_TT_TW];
337 err = lis3dh_acc_i2c_write(acc, buf, 4);
341 buf[1] = acc->resume_state[RES_TT_CFG];
342 err = lis3dh_acc_i2c_write(acc, buf, 1);
346 buf[0] = (I2C_AUTO_INCREMENT | INT_THS1);
347 buf[1] = acc->resume_state[RES_INT_THS1];
348 buf[2] = acc->resume_state[RES_INT_DUR1];
349 err = lis3dh_acc_i2c_write(acc, buf, 2);
353 buf[1] = acc->resume_state[RES_INT_CFG1];
354 err = lis3dh_acc_i2c_write(acc, buf, 1);
358 buf[0] = (I2C_AUTO_INCREMENT | INT_THS2);
359 buf[1] = acc->resume_state[RES_INT_THS2];
360 buf[2] = acc->resume_state[RES_INT_DUR2];
361 err = lis3dh_acc_i2c_write(acc, buf, 2);
365 buf[1] = acc->resume_state[RES_INT_CFG2];
366 err = lis3dh_acc_i2c_write(acc, buf, 1);
370 buf[0] = (I2C_AUTO_INCREMENT | CTRL_REG2);
371 buf[1] = acc->resume_state[RES_CTRL_REG2];
372 buf[2] = acc->resume_state[RES_CTRL_REG3];
373 buf[3] = acc->resume_state[RES_CTRL_REG4];
374 buf[4] = acc->resume_state[RES_CTRL_REG5];
375 buf[5] = acc->resume_state[RES_CTRL_REG6];
376 err = lis3dh_acc_i2c_write(acc, buf, 5);
380 acc->hw_initialized = 1;
381 printk(KERN_INFO "%s: hw init done\n", LIS3DH_ACC_DEV_NAME);
386 dev_warn(&acc->client->dev, "Error reading WHO_AM_I: is device "
387 "available/working?\n");
389 error_unknown_device:
390 dev_err(&acc->client->dev,
391 "device unknown. Expected: 0x%x,"
392 " Replies: 0x%x\n", WHOAMI_LIS3DH_ACC, buf[0]);
394 acc->hw_initialized = 0;
395 dev_err(&acc->client->dev, "hw init error 0x%x,0x%x: %d\n", buf[0],
400 static void lis3dh_acc_device_power_off(struct lis3dh_acc_data *acc)
403 u8 buf[2] = { CTRL_REG1, LIS3DH_ACC_PM_OFF };
405 err = lis3dh_acc_i2c_write(acc, buf, 1);
407 dev_err(&acc->client->dev, "soft power off failed: %d\n", err);
409 if (acc->pdata->power_off) {
410 disable_irq_nosync(acc->irq1);
411 disable_irq_nosync(acc->irq2);
412 acc->pdata->power_off();
413 acc->hw_initialized = 0;
415 if (acc->hw_initialized) {
416 disable_irq_nosync(acc->irq1);
417 disable_irq_nosync(acc->irq2);
418 acc->hw_initialized = 0;
423 static int lis3dh_acc_device_power_on(struct lis3dh_acc_data *acc)
427 if (acc->pdata->power_on) {
428 err = acc->pdata->power_on();
430 dev_err(&acc->client->dev,
431 "power_on failed: %d\n", err);
434 enable_irq(acc->irq1);
435 enable_irq(acc->irq2);
438 if (!acc->hw_initialized) {
439 err = lis3dh_acc_hw_init(acc);
440 if (acc->hw_working == 1 && err < 0) {
441 lis3dh_acc_device_power_off(acc);
446 if (acc->hw_initialized) {
447 enable_irq(acc->irq1);
448 enable_irq(acc->irq2);
449 printk(KERN_INFO "%s: power on: irq enabled\n",
450 LIS3DH_ACC_DEV_NAME);
455 static irqreturn_t lis3dh_acc_isr1(int irq, void *dev)
457 struct lis3dh_acc_data *acc = dev;
459 disable_irq_nosync(irq);
460 queue_work(acc->irq1_work_queue, &acc->irq1_work);
461 printk(KERN_INFO "%s: isr1 queued\n", LIS3DH_ACC_DEV_NAME);
466 static irqreturn_t lis3dh_acc_isr2(int irq, void *dev)
468 struct lis3dh_acc_data *acc = dev;
470 disable_irq_nosync(irq);
471 queue_work(acc->irq2_work_queue, &acc->irq2_work);
472 printk(KERN_INFO "%s: isr2 queued\n", LIS3DH_ACC_DEV_NAME);
479 static void lis3dh_acc_irq1_work_func(struct work_struct *work)
482 struct lis3dh_acc_data *acc =
483 container_of(work, struct lis3dh_acc_data, irq1_work);
484 /* TODO add interrupt service procedure.
485 ie:lis3dh_acc_get_int1_source(acc); */
488 printk(KERN_INFO "%s: IRQ1 triggered\n", LIS3DH_ACC_DEV_NAME);
490 enable_irq(acc->irq1);
493 static void lis3dh_acc_irq2_work_func(struct work_struct *work)
496 struct lis3dh_acc_data *acc =
497 container_of(work, struct lis3dh_acc_data, irq2_work);
498 /* TODO add interrupt service procedure.
499 ie:lis3dh_acc_get_tap_source(acc); */
503 printk(KERN_INFO "%s: IRQ2 triggered\n", LIS3DH_ACC_DEV_NAME);
505 enable_irq(acc->irq2);
508 int lis3dh_acc_update_g_range(struct lis3dh_acc_data *acc, u8 new_g_range)
517 u8 mask = LIS3DH_ACC_FS_MASK | HIGH_RESOLUTION;
519 switch (new_g_range) {
520 case LIS3DH_ACC_G_2G:
522 sensitivity = SENSITIVITY_2G;
524 case LIS3DH_ACC_G_4G:
526 sensitivity = SENSITIVITY_4G;
528 case LIS3DH_ACC_G_8G:
530 sensitivity = SENSITIVITY_8G;
532 case LIS3DH_ACC_G_16G:
534 sensitivity = SENSITIVITY_16G;
537 dev_err(&acc->client->dev, "invalid g range requested: %u\n",
542 if (atomic_read(&acc->enabled)) {
543 /* Set configuration register 4, which contains g range setting
544 * NOTE: this is a straight overwrite because this driver does
545 * not use any of the other configuration bits in this
546 * register. Should this become untrue, we will have to read
547 * out the value and only change the relevant bits --XX----
550 err = lis3dh_acc_i2c_read(acc, buf, 1);
554 acc->resume_state[RES_CTRL_REG4] = init_val;
555 new_val = new_g_range | HIGH_RESOLUTION;
556 updated_val = ((mask & new_val) | ((~mask) & init_val));
557 buf[1] = updated_val;
559 err = lis3dh_acc_i2c_write(acc, buf, 1);
562 acc->resume_state[RES_CTRL_REG4] = updated_val;
563 acc->sensitivity = sensitivity;
569 dev_err(&acc->client->dev, "update g range failed 0x%x,0x%x: %d\n",
570 buf[0], buf[1], err);
575 int lis3dh_acc_update_odr(struct lis3dh_acc_data *acc, int poll_interval_ms)
581 /* Convert the poll interval into an output data rate configuration
582 * that is as low as possible. The ordering of these checks must be
583 * maintained due to the cascading cut off values - poll intervals are
584 * checked from shortest to longest. At each check, if the next lower
585 * ODR cannot support the current poll interval, we stop searching */
586 for (i = ARRAY_SIZE(lis3dh_acc_odr_table) - 1; i >= 0; i--) {
587 if (lis3dh_acc_odr_table[i].cutoff_ms <= poll_interval_ms)
590 config[1] = lis3dh_acc_odr_table[i].mask;
592 config[1] |= LIS3DH_ACC_ENABLE_ALL_AXES;
594 /* If device is currently enabled, we need to write new
595 * configuration out to it */
596 if (atomic_read(&acc->enabled)) {
597 config[0] = CTRL_REG1;
598 err = lis3dh_acc_i2c_write(acc, config, 1);
601 acc->resume_state[RES_CTRL_REG1] = config[1];
607 dev_err(&acc->client->dev, "update odr failed 0x%x,0x%x: %d\n",
608 config[0], config[1], err);
615 static int lis3dh_acc_register_write(struct lis3dh_acc_data *acc, u8 *buf,
616 u8 reg_address, u8 new_value)
620 if (atomic_read(&acc->enabled)) {
621 /* Sets configuration register at reg_address
622 * NOTE: this is a straight overwrite */
623 buf[0] = reg_address;
625 err = lis3dh_acc_i2c_write(acc, buf, 1);
632 static int lis3dh_acc_register_read(struct lis3dh_acc_data *acc, u8 *buf,
637 buf[0] = (reg_address);
638 err = lis3dh_acc_i2c_read(acc, buf, 1);
642 static int lis3dh_acc_register_update(struct lis3dh_acc_data *acc, u8 *buf,
643 u8 reg_address, u8 mask, u8 new_bit_values)
648 err = lis3dh_acc_register_read(acc, buf, reg_address);
651 updated_val = ((mask & new_bit_values) | ((~mask) & init_val));
652 err = lis3dh_acc_register_write(acc, buf, reg_address,
660 static int lis3dh_acc_get_acceleration_data(struct lis3dh_acc_data *acc,
664 /* Data bytes from hardware xL, xH, yL, yH, zL, zH */
666 /* x,y,z hardware data */
669 acc_data[0] = (I2C_AUTO_INCREMENT | AXISDATA_REG);
670 err = lis3dh_acc_i2c_read(acc, acc_data, 6);
674 hw_d[0] = (((s16) ((acc_data[1] << 8) | acc_data[0])) >> 4);
675 hw_d[1] = (((s16) ((acc_data[3] << 8) | acc_data[2])) >> 4);
676 hw_d[2] = (((s16) ((acc_data[5] << 8) | acc_data[4])) >> 4);
678 hw_d[0] = hw_d[0] * acc->sensitivity;
679 hw_d[1] = hw_d[1] * acc->sensitivity;
680 hw_d[2] = hw_d[2] * acc->sensitivity;
683 xyz[0] = ((acc->pdata->negate_x) ? (-hw_d[acc->pdata->axis_map_x])
684 : (hw_d[acc->pdata->axis_map_x]));
685 xyz[1] = ((acc->pdata->negate_y) ? (-hw_d[acc->pdata->axis_map_y])
686 : (hw_d[acc->pdata->axis_map_y]));
687 xyz[2] = ((acc->pdata->negate_z) ? (-hw_d[acc->pdata->axis_map_z])
688 : (hw_d[acc->pdata->axis_map_z]));
692 printk(KERN_INFO "%s read x=%d, y=%d, z=%d\n",
693 LIS3DH_ACC_DEV_NAME, xyz[0], xyz[1], xyz[2]);
699 static void lis3dh_acc_report_values(struct lis3dh_acc_data *acc, int *xyz)
701 input_report_abs(acc->input_dev, ABS_X, xyz[0]);
702 input_report_abs(acc->input_dev, ABS_Y, xyz[1]);
703 input_report_abs(acc->input_dev, ABS_Z, xyz[2]);
704 input_sync(acc->input_dev);
707 static int lis3dh_acc_enable(struct lis3dh_acc_data *acc)
711 if (!atomic_cmpxchg(&acc->enabled, 0, 1)) {
712 err = lis3dh_acc_device_power_on(acc);
714 atomic_set(&acc->enabled, 0);
717 schedule_delayed_work(&acc->input_work, msecs_to_jiffies(
718 acc->pdata->poll_interval));
724 static int lis3dh_acc_disable(struct lis3dh_acc_data *acc)
726 if (atomic_cmpxchg(&acc->enabled, 1, 0)) {
727 cancel_delayed_work_sync(&acc->input_work);
728 lis3dh_acc_device_power_off(acc);
734 static int lis3dh_acc_misc_open(struct inode *inode, struct file *file)
737 err = nonseekable_open(inode, file);
741 file->private_data = lis3dh_acc_misc_data;
746 static int lis3dh_acc_misc_ioctl(struct inode *inode, struct file *file,
747 unsigned int cmd, unsigned long arg)
749 void __user *argp = (void __user *)arg;
756 struct lis3dh_acc_data *acc = file->private_data;
758 printk(KERN_INFO "%s: %s call with cmd 0x%x and arg 0x%x\n",
759 LIS3DH_ACC_DEV_NAME, __func__, cmd, (unsigned int)arg);
762 case LIS3DH_ACC_IOCTL_GET_DELAY:
763 interval = acc->pdata->poll_interval;
764 if (copy_to_user(argp, &interval, sizeof(interval)))
768 case LIS3DH_ACC_IOCTL_SET_DELAY:
769 if (copy_from_user(&interval, argp, sizeof(interval)))
771 if (interval < 0 || interval > 1000)
774 acc->pdata->poll_interval = max(interval,
775 acc->pdata->min_interval);
776 err = lis3dh_acc_update_odr(acc, acc->pdata->poll_interval);
777 /* TODO: if update fails poll is still set */
782 case LIS3DH_ACC_IOCTL_SET_ENABLE:
783 if (copy_from_user(&interval, argp, sizeof(interval)))
788 err = lis3dh_acc_enable(acc);
790 err = lis3dh_acc_disable(acc);
794 case LIS3DH_ACC_IOCTL_GET_ENABLE:
795 interval = atomic_read(&acc->enabled);
796 if (copy_to_user(argp, &interval, sizeof(interval)))
800 case LIS3DH_ACC_IOCTL_SET_G_RANGE:
801 if (copy_from_user(buf, argp, 1))
804 err = lis3dh_acc_update_g_range(acc, bit_values);
809 #ifdef INTERRUPT_MANAGEMENT
810 case LIS3DH_ACC_IOCTL_SET_CTRL_REG3:
811 if (copy_from_user(buf, argp, 2))
813 reg_address = CTRL_REG3;
816 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
820 acc->resume_state[RES_CTRL_REG3] = ((mask & bit_values) |
821 ( ~mask & acc->resume_state[RES_CTRL_REG3]));
824 case LIS3DH_ACC_IOCTL_SET_CTRL_REG6:
825 if (copy_from_user(buf, argp, 2))
827 reg_address = CTRL_REG6;
830 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
834 acc->resume_state[RES_CTRL_REG6] = ((mask & bit_values) |
835 ( ~mask & acc->resume_state[RES_CTRL_REG6]));
838 case LIS3DH_ACC_IOCTL_SET_DURATION1:
839 if (copy_from_user(buf, argp, 1))
841 reg_address = INT_DUR1;
844 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
848 acc->resume_state[RES_INT_DUR1] = ((mask & bit_values) |
849 ( ~mask & acc->resume_state[RES_INT_DUR1]));
852 case LIS3DH_ACC_IOCTL_SET_THRESHOLD1:
853 if (copy_from_user(buf, argp, 1))
855 reg_address = INT_THS1;
858 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
862 acc->resume_state[RES_INT_THS1] = ((mask & bit_values) |
863 ( ~mask & acc->resume_state[RES_INT_THS1]));
866 case LIS3DH_ACC_IOCTL_SET_CONFIG1:
867 if (copy_from_user(buf, argp, 2))
869 reg_address = INT_CFG1;
872 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
876 acc->resume_state[RES_INT_CFG1] = ((mask & bit_values) |
877 ( ~mask & acc->resume_state[RES_INT_CFG1]));
880 case LIS3DH_ACC_IOCTL_GET_SOURCE1:
881 err = lis3dh_acc_register_read(acc, buf, INT_SRC1);
885 printk(KERN_ALERT "INT1_SRC content: %d , 0x%x\n",
888 if (copy_to_user(argp, buf, 1))
892 case LIS3DH_ACC_IOCTL_SET_DURATION2:
893 if (copy_from_user(buf, argp, 1))
895 reg_address = INT_DUR2;
898 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
902 acc->resume_state[RES_INT_DUR2] = ((mask & bit_values) |
903 ( ~mask & acc->resume_state[RES_INT_DUR2]));
906 case LIS3DH_ACC_IOCTL_SET_THRESHOLD2:
907 if (copy_from_user(buf, argp, 1))
909 reg_address = INT_THS2;
912 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
916 acc->resume_state[RES_INT_THS2] = ((mask & bit_values) |
917 ( ~mask & acc->resume_state[RES_INT_THS2]));
920 case LIS3DH_ACC_IOCTL_SET_CONFIG2:
921 if (copy_from_user(buf, argp, 2))
923 reg_address = INT_CFG2;
926 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
930 acc->resume_state[RES_INT_CFG2] = ((mask & bit_values) |
931 ( ~mask & acc->resume_state[RES_INT_CFG2]));
934 case LIS3DH_ACC_IOCTL_GET_SOURCE2:
935 err = lis3dh_acc_register_read(acc, buf, INT_SRC2);
939 printk(KERN_ALERT "INT2_SRC content: %d , 0x%x\n",
942 if (copy_to_user(argp, buf, 1))
946 case LIS3DH_ACC_IOCTL_GET_TAP_SOURCE:
947 err = lis3dh_acc_register_read(acc, buf, TT_SRC);
951 printk(KERN_ALERT "TT_SRC content: %d , 0x%x\n",
954 if (copy_to_user(argp, buf, 1)) {
955 printk(KERN_ERR "%s: %s error in copy_to_user \n",
956 LIS3DH_ACC_DEV_NAME, __func__);
961 case LIS3DH_ACC_IOCTL_SET_TAP_CFG:
962 if (copy_from_user(buf, argp, 2))
964 reg_address = TT_CFG;
967 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
971 acc->resume_state[RES_TT_CFG] = ((mask & bit_values) |
972 ( ~mask & acc->resume_state[RES_TT_CFG]));
975 case LIS3DH_ACC_IOCTL_SET_TAP_TLIM:
976 if (copy_from_user(buf, argp, 2))
978 reg_address = TT_LIM;
981 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
985 acc->resume_state[RES_TT_LIM] = ((mask & bit_values) |
986 ( ~mask & acc->resume_state[RES_TT_LIM]));
989 case LIS3DH_ACC_IOCTL_SET_TAP_THS:
990 if (copy_from_user(buf, argp, 2))
992 reg_address = TT_THS;
995 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
999 acc->resume_state[RES_TT_THS] = ((mask & bit_values) |
1000 ( ~mask & acc->resume_state[RES_TT_THS]));
1003 case LIS3DH_ACC_IOCTL_SET_TAP_TLAT:
1004 if (copy_from_user(buf, argp, 2))
1006 reg_address = TT_TLAT;
1008 bit_values = buf[0];
1009 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
1013 acc->resume_state[RES_TT_TLAT] = ((mask & bit_values) |
1014 ( ~mask & acc->resume_state[RES_TT_TLAT]));
1017 case LIS3DH_ACC_IOCTL_SET_TAP_TW:
1018 if (copy_from_user(buf, argp, 2))
1020 reg_address = TT_TW;
1022 bit_values = buf[0];
1023 err = lis3dh_acc_register_update(acc, (u8 *) arg, reg_address,
1027 acc->resume_state[RES_TT_TW] = ((mask & bit_values) |
1028 ( ~mask & acc->resume_state[RES_TT_TW]));
1031 #endif /* INTERRUPT_MANAGEMENT */
1040 static const struct file_operations lis3dh_acc_misc_fops = {
1041 .owner = THIS_MODULE,
1042 .open = lis3dh_acc_misc_open,
1043 .ioctl = lis3dh_acc_misc_ioctl,
1046 static struct miscdevice lis3dh_acc_misc_device = {
1047 .minor = MISC_DYNAMIC_MINOR,
1048 .name = LIS3DH_ACC_DEV_NAME,
1049 .fops = &lis3dh_acc_misc_fops,
1052 static void lis3dh_acc_input_work_func(struct work_struct *work)
1054 struct lis3dh_acc_data *acc;
1059 acc = container_of((struct delayed_work *)work,
1060 struct lis3dh_acc_data, input_work);
1062 mutex_lock(&acc->lock);
1063 err = lis3dh_acc_get_acceleration_data(acc, xyz);
1065 dev_err(&acc->client->dev, "get_acceleration_data failed\n");
1067 lis3dh_acc_report_values(acc, xyz);
1069 schedule_delayed_work(&acc->input_work, msecs_to_jiffies(
1070 acc->pdata->poll_interval));
1071 mutex_unlock(&acc->lock);
1074 #ifdef LIS3DH_OPEN_ENABLE
1075 int lis3dh_acc_input_open(struct input_dev *input)
1077 struct lis3dh_acc_data *acc = input_get_drvdata(input);
1079 return lis3dh_acc_enable(acc);
1082 void lis3dh_acc_input_close(struct input_dev *dev)
1084 struct lis3dh_acc_data *acc = input_get_drvdata(dev);
1086 lis3dh_acc_disable(acc);
1090 static int lis3dh_acc_validate_pdata(struct lis3dh_acc_data *acc)
1092 acc->pdata->poll_interval = max(acc->pdata->poll_interval,
1093 acc->pdata->min_interval);
1095 if (acc->pdata->axis_map_x > 2 || acc->pdata->axis_map_y > 2
1096 || acc->pdata->axis_map_z > 2) {
1097 dev_err(&acc->client->dev, "invalid axis_map value "
1098 "x:%u y:%u z%u\n", acc->pdata->axis_map_x,
1099 acc->pdata->axis_map_y, acc->pdata->axis_map_z);
1103 /* Only allow 0 and 1 for negation boolean flag */
1104 if (acc->pdata->negate_x > 1 || acc->pdata->negate_y > 1
1105 || acc->pdata->negate_z > 1) {
1106 dev_err(&acc->client->dev, "invalid negate value "
1107 "x:%u y:%u z:%u\n", acc->pdata->negate_x,
1108 acc->pdata->negate_y, acc->pdata->negate_z);
1112 /* Enforce minimum polling interval */
1113 if (acc->pdata->poll_interval < acc->pdata->min_interval) {
1114 dev_err(&acc->client->dev, "minimum poll interval violated\n");
1121 static int lis3dh_acc_input_init(struct lis3dh_acc_data *acc)
1125 INIT_DELAYED_WORK(&acc->input_work, lis3dh_acc_input_work_func);
1126 acc->input_dev = input_allocate_device();
1127 if (!acc->input_dev) {
1129 dev_err(&acc->client->dev, "input device allocate failed\n");
1133 #ifdef LIS3DH_ACC_OPEN_ENABLE
1134 acc->input_dev->open = lis3dh_acc_input_open;
1135 acc->input_dev->close = lis3dh_acc_input_close;
1138 input_set_drvdata(acc->input_dev, acc);
1140 set_bit(EV_ABS, acc->input_dev->evbit);
1141 /* next is used for interruptA sources data if the case */
1142 set_bit(ABS_MISC, acc->input_dev->absbit);
1143 /* next is used for interruptB sources data if the case */
1144 set_bit(ABS_WHEEL, acc->input_dev->absbit);
1146 input_set_abs_params(acc->input_dev, ABS_X, -G_MAX, G_MAX, FUZZ, FLAT);
1147 input_set_abs_params(acc->input_dev, ABS_Y, -G_MAX, G_MAX, FUZZ, FLAT);
1148 input_set_abs_params(acc->input_dev, ABS_Z, -G_MAX, G_MAX, FUZZ, FLAT);
1149 /* next is used for interruptA sources data if the case */
1150 input_set_abs_params(acc->input_dev, ABS_MISC, INT_MIN, INT_MAX, 0, 0);
1151 /* next is used for interruptB sources data if the case */
1152 input_set_abs_params(acc->input_dev, ABS_WHEEL, INT_MIN, INT_MAX, 0, 0);
1154 acc->input_dev->name = "accelerometer";
1156 err = input_register_device(acc->input_dev);
1158 dev_err(&acc->client->dev,
1159 "unable to register input polled device %s\n",
1160 acc->input_dev->name);
1167 input_free_device(acc->input_dev);
1172 static void lis3dh_acc_input_cleanup(struct lis3dh_acc_data *acc)
1174 input_unregister_device(acc->input_dev);
1175 input_free_device(acc->input_dev);
1178 static int lis3dh_acc_probe(struct i2c_client *client,
1179 const struct i2c_device_id *id)
1182 struct lis3dh_acc_data *acc;
1187 pr_info("%s: probe start.\n", LIS3DH_ACC_DEV_NAME);
1189 if (client->dev.platform_data == NULL) {
1190 dev_err(&client->dev, "platform data is NULL. exiting.\n");
1192 goto exit_check_functionality_failed;
1195 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1196 dev_err(&client->dev, "client not i2c capable\n");
1198 goto exit_check_functionality_failed;
1201 if (!i2c_check_functionality(client->adapter,
1202 I2C_FUNC_SMBUS_BYTE |
1203 I2C_FUNC_SMBUS_BYTE_DATA |
1204 I2C_FUNC_SMBUS_WORD_DATA)) {
1205 dev_err(&client->dev, "client not smb-i2c capable:2\n");
1207 goto exit_check_functionality_failed;
1211 if (!i2c_check_functionality(client->adapter,
1212 I2C_FUNC_SMBUS_I2C_BLOCK)){
1213 dev_err(&client->dev, "client not smb-i2c capable:3\n");
1215 goto exit_check_functionality_failed;
1218 * OK. From now, we presume we have a valid client. We now create the
1219 * client structure, even though we cannot fill it completely yet.
1222 acc = kzalloc(sizeof(struct lis3dh_acc_data), GFP_KERNEL);
1225 dev_err(&client->dev,
1226 "failed to allocate memory for module data: "
1228 goto exit_alloc_data_failed;
1231 mutex_init(&acc->lock);
1232 mutex_lock(&acc->lock);
1234 acc->client = client;
1235 i2c_set_clientdata(client, acc);
1238 INIT_WORK(&acc->irq1_work, lis3dh_acc_irq1_work_func);
1239 acc->irq1_work_queue = create_singlethread_workqueue("lis3dh_acc_wq1");
1240 if (!acc->irq1_work_queue) {
1242 dev_err(&client->dev, "cannot create work queue1: %d\n", err);
1243 goto err_mutexunlockfreedata;
1246 INIT_WORK(&acc->irq2_work, lis3dh_acc_irq2_work_func);
1247 acc->irq2_work_queue = create_singlethread_workqueue("lis3dh_acc_wq2");
1248 if (!acc->irq2_work_queue) {
1250 dev_err(&client->dev, "cannot create work queue2: %d\n", err);
1251 goto err_destoyworkqueue1;
1256 if (i2c_smbus_read_byte(client) < 0) {
1257 printk(KERN_ERR "i2c_smbus_read_byte error!!\n");
1258 goto err_destoyworkqueue2;
1260 printk(KERN_INFO "%s Device detected!\n", LIS3DH_ACC_DEV_NAME);
1265 tempvalue = i2c_smbus_read_word_data(client, WHO_AM_I);
1266 if ((tempvalue & 0x00FF) == WHOAMI_LIS3DH_ACC) {
1267 printk(KERN_INFO "%s I2C driver registered!\n",
1268 LIS3DH_ACC_DEV_NAME);
1271 printk(KERN_INFO "I2C driver not registered!"
1272 " Device unknown\n");
1273 goto err_destoyworkqueue2;
1276 acc->pdata = kmalloc(sizeof(*acc->pdata), GFP_KERNEL);
1277 if (acc->pdata == NULL) {
1279 dev_err(&client->dev,
1280 "failed to allocate memory for pdata: %d\n",
1282 goto err_destoyworkqueue2;
1285 memcpy(acc->pdata, client->dev.platform_data, sizeof(*acc->pdata));
1287 err = lis3dh_acc_validate_pdata(acc);
1289 dev_err(&client->dev, "failed to validate platform data\n");
1290 goto exit_kfree_pdata;
1293 i2c_set_clientdata(client, acc);
1296 if (acc->pdata->init) {
1297 err = acc->pdata->init();
1299 dev_err(&client->dev, "init failed: %d\n", err);
1304 memset(acc->resume_state, 0, ARRAY_SIZE(acc->resume_state));
1306 acc->irq1 = gpio_to_irq(acc->pdata->gpio_int1);
1307 printk(KERN_INFO "%s: %s has set irq1 to irq: %d mapped on gpio:%d\n",
1308 LIS3DH_ACC_DEV_NAME, __func__, acc->irq1,
1309 acc->pdata->gpio_int1);
1310 acc->irq2 = gpio_to_irq(acc->pdata->gpio_int2);
1311 printk(KERN_INFO "%s: %s has set irq2 to irq: %d mapped on gpio:%d\n",
1312 LIS3DH_ACC_DEV_NAME, __func__, acc->irq2,
1313 acc->pdata->gpio_int2);
1318 acc->resume_state[RES_CTRL_REG1] = LIS3DH_ACC_ENABLE_ALL_AXES;
1319 acc->resume_state[RES_CTRL_REG2] = 0x00;
1320 acc->resume_state[RES_CTRL_REG3] = 0x00;
1321 acc->resume_state[RES_CTRL_REG4] = 0x00;
1322 acc->resume_state[RES_CTRL_REG5] = 0x00;
1323 acc->resume_state[RES_CTRL_REG6] = 0x00;
1325 acc->resume_state[RES_TEMP_CFG_REG] = 0x00;
1326 acc->resume_state[RES_FIFO_CTRL_REG] = 0x00;
1327 acc->resume_state[RES_INT_CFG1] = 0x00;
1328 acc->resume_state[RES_INT_THS1] = 0x00;
1329 acc->resume_state[RES_INT_DUR1] = 0x00;
1330 acc->resume_state[RES_INT_CFG2] = 0x00;
1331 acc->resume_state[RES_INT_THS2] = 0x00;
1332 acc->resume_state[RES_INT_DUR2] = 0x00;
1334 acc->resume_state[RES_TT_CFG] = 0x00;
1335 acc->resume_state[RES_TT_THS] = 0x00;
1336 acc->resume_state[RES_TT_LIM] = 0x00;
1337 acc->resume_state[RES_TT_TLAT] = 0x00;
1338 acc->resume_state[RES_TT_TW] = 0x00;
1340 err = lis3dh_acc_device_power_on(acc);
1342 dev_err(&client->dev, "power on failed: %d\n", err);
1346 atomic_set(&acc->enabled, 1);
1348 err = lis3dh_acc_update_g_range(acc, acc->pdata->g_range);
1350 dev_err(&client->dev, "update_g_range failed\n");
1354 err = lis3dh_acc_update_odr(acc, acc->pdata->poll_interval);
1356 dev_err(&client->dev, "update_odr failed\n");
1360 err = lis3dh_acc_input_init(acc);
1362 dev_err(&client->dev, "input init failed\n");
1365 lis3dh_acc_misc_data = acc;
1367 err = misc_register(&lis3dh_acc_misc_device);
1369 dev_err(&client->dev,
1370 "misc LIS3DH_ACC_DEV_NAME register failed\n");
1371 goto err_input_cleanup;
1374 lis3dh_acc_device_power_off(acc);
1376 /* As default, do not report information */
1377 atomic_set(&acc->enabled, 0);
1379 err = request_irq(acc->irq1, lis3dh_acc_isr1, IRQF_TRIGGER_RISING,
1380 "lis3dh_acc_irq1", acc);
1382 dev_err(&client->dev, "request irq1 failed: %d\n", err);
1383 goto err_misc_dereg;
1385 disable_irq_nosync(acc->irq1);
1387 err = request_irq(acc->irq2, lis3dh_acc_isr2, IRQF_TRIGGER_RISING,
1388 "lis3dh_acc_irq2", acc);
1390 dev_err(&client->dev, "request irq2 failed: %d\n", err);
1393 disable_irq_nosync(acc->irq2);
1395 mutex_unlock(&acc->lock);
1397 dev_info(&client->dev, "%s: probed\n", LIS3DH_ACC_DEV_NAME);
1402 free_irq(acc->irq1, acc);
1404 misc_deregister(&lis3dh_acc_misc_device);
1406 lis3dh_acc_input_cleanup(acc);
1408 lis3dh_acc_device_power_off(acc);
1410 if (acc->pdata->exit)
1414 err_destoyworkqueue2:
1415 destroy_workqueue(acc->irq2_work_queue);
1416 err_destoyworkqueue1:
1417 destroy_workqueue(acc->irq1_work_queue);
1418 err_mutexunlockfreedata:
1419 mutex_unlock(&acc->lock);
1421 exit_alloc_data_failed:
1422 exit_check_functionality_failed:
1423 printk(KERN_ERR "%s: Driver Init failed\n", LIS3DH_ACC_DEV_NAME);
1427 static int __devexit lis3dh_acc_remove(struct i2c_client *client)
1429 /* TODO: revisit ordering here once _probe order is finalized */
1430 struct lis3dh_acc_data *acc = i2c_get_clientdata(client);
1432 free_irq(acc->irq1, acc);
1433 free_irq(acc->irq2, acc);
1434 gpio_free(acc->pdata->gpio_int1);
1435 gpio_free(acc->pdata->gpio_int2);
1436 destroy_workqueue(acc->irq1_work_queue);
1437 destroy_workqueue(acc->irq2_work_queue);
1439 misc_deregister(&lis3dh_acc_misc_device);
1440 lis3dh_acc_input_cleanup(acc);
1441 lis3dh_acc_device_power_off(acc);
1442 if (acc->pdata->exit)
1450 static int lis3dh_acc_resume(struct i2c_client *client)
1452 struct lis3dh_acc_data *acc = i2c_get_clientdata(client);
1454 if (acc->on_before_suspend)
1455 return lis3dh_acc_enable(acc);
1459 static int lis3dh_acc_suspend(struct i2c_client *client, pm_message_t mesg)
1461 struct lis3dh_acc_data *acc = i2c_get_clientdata(client);
1463 acc->on_before_suspend = atomic_read(&acc->enabled);
1464 return lis3dh_acc_disable(acc);
1467 static const struct i2c_device_id lis3dh_acc_id[]
1468 = { { LIS3DH_ACC_DEV_NAME, 0 }, { }, };
1470 MODULE_DEVICE_TABLE(i2c, lis3dh_acc_id);
1472 static struct i2c_driver lis3dh_acc_driver = {
1474 .name = LIS3DH_ACC_DEV_NAME,
1476 .probe = lis3dh_acc_probe,
1477 .remove = __devexit_p(lis3dh_acc_remove),
1478 .resume = lis3dh_acc_resume,
1479 .suspend = lis3dh_acc_suspend,
1480 .id_table = lis3dh_acc_id,
1483 static int __init lis3dh_acc_init(void)
1485 printk(KERN_INFO "%s accelerometer driver: init\n",
1486 LIS3DH_ACC_DEV_NAME);
1487 return i2c_add_driver(&lis3dh_acc_driver);
1490 static void __exit lis3dh_acc_exit(void)
1493 printk(KERN_INFO "%s accelerometer driver exit\n", LIS3DH_ACC_DEV_NAME);
1495 i2c_del_driver(&lis3dh_acc_driver);
1499 module_init(lis3dh_acc_init);
1500 module_exit(lis3dh_acc_exit);
1502 MODULE_DESCRIPTION("lis3dh accelerometer misc driver");
1503 MODULE_AUTHOR("STMicroelectronics");
1504 MODULE_LICENSE("GPL");