2 * i8042 keyboard and mouse controller driver for Linux
4 * Copyright (c) 1999-2004 Vojtech Pavlik
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/init.h>
21 #include <linux/serio.h>
22 #include <linux/err.h>
23 #include <linux/rcupdate.h>
24 #include <linux/platform_device.h>
25 #include <linux/i8042.h>
26 #include <linux/slab.h>
30 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
31 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
32 MODULE_LICENSE("GPL");
34 static bool i8042_nokbd;
35 module_param_named(nokbd, i8042_nokbd, bool, 0);
36 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
38 static bool i8042_noaux;
39 module_param_named(noaux, i8042_noaux, bool, 0);
40 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
42 static bool i8042_nomux;
43 module_param_named(nomux, i8042_nomux, bool, 0);
44 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
46 static bool i8042_unlock;
47 module_param_named(unlock, i8042_unlock, bool, 0);
48 MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
50 static bool i8042_reset;
51 module_param_named(reset, i8042_reset, bool, 0);
52 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
54 static bool i8042_direct;
55 module_param_named(direct, i8042_direct, bool, 0);
56 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
58 static bool i8042_dumbkbd;
59 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
60 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
62 static bool i8042_noloop;
63 module_param_named(noloop, i8042_noloop, bool, 0);
64 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
66 static bool i8042_notimeout;
67 module_param_named(notimeout, i8042_notimeout, bool, 0);
68 MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042");
70 static bool i8042_kbdreset;
71 module_param_named(kbdreset, i8042_kbdreset, bool, 0);
72 MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port");
75 static bool i8042_dritek;
76 module_param_named(dritek, i8042_dritek, bool, 0);
77 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
81 static bool i8042_nopnp;
82 module_param_named(nopnp, i8042_nopnp, bool, 0);
83 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
88 static bool i8042_debug;
89 module_param_named(debug, i8042_debug, bool, 0600);
90 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
93 static bool i8042_bypass_aux_irq_test;
94 static char i8042_kbd_firmware_id[128];
95 static char i8042_aux_firmware_id[128];
100 * i8042_lock protects serialization between i8042_command and
101 * the interrupt handler.
103 static DEFINE_SPINLOCK(i8042_lock);
106 * Writers to AUX and KBD ports as well as users issuing i8042_command
107 * directly should acquire i8042_mutex (by means of calling
108 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that
109 * they do not disturb each other (unfortunately in many i8042
110 * implementations write to one of the ports will immediately abort
111 * command that is being processed by another port).
113 static DEFINE_MUTEX(i8042_mutex);
122 #define I8042_KBD_PORT_NO 0
123 #define I8042_AUX_PORT_NO 1
124 #define I8042_MUX_PORT_NO 2
125 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
127 static struct i8042_port i8042_ports[I8042_NUM_PORTS];
129 static unsigned char i8042_initial_ctr;
130 static unsigned char i8042_ctr;
131 static bool i8042_mux_present;
132 static bool i8042_kbd_irq_registered;
133 static bool i8042_aux_irq_registered;
134 static unsigned char i8042_suppress_kbd_ack;
135 static struct platform_device *i8042_platform_device;
137 static irqreturn_t i8042_interrupt(int irq, void *dev_id);
138 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
139 struct serio *serio);
141 void i8042_lock_chip(void)
143 mutex_lock(&i8042_mutex);
145 EXPORT_SYMBOL(i8042_lock_chip);
147 void i8042_unlock_chip(void)
149 mutex_unlock(&i8042_mutex);
151 EXPORT_SYMBOL(i8042_unlock_chip);
153 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
154 struct serio *serio))
159 spin_lock_irqsave(&i8042_lock, flags);
161 if (i8042_platform_filter) {
166 i8042_platform_filter = filter;
169 spin_unlock_irqrestore(&i8042_lock, flags);
172 EXPORT_SYMBOL(i8042_install_filter);
174 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
180 spin_lock_irqsave(&i8042_lock, flags);
182 if (i8042_platform_filter != filter) {
187 i8042_platform_filter = NULL;
190 spin_unlock_irqrestore(&i8042_lock, flags);
193 EXPORT_SYMBOL(i8042_remove_filter);
196 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
197 * be ready for reading values from it / writing values to it.
198 * Called always with i8042_lock held.
201 static int i8042_wait_read(void)
205 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
209 return -(i == I8042_CTL_TIMEOUT);
212 static int i8042_wait_write(void)
216 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
220 return -(i == I8042_CTL_TIMEOUT);
224 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
225 * of the i8042 down the toilet.
228 static int i8042_flush(void)
231 unsigned char data, str;
235 spin_lock_irqsave(&i8042_lock, flags);
237 while ((str = i8042_read_status()) & I8042_STR_OBF) {
238 if (count++ < I8042_BUFFER_SIZE) {
240 data = i8042_read_data();
241 dbg("%02x <- i8042 (flush, %s)\n",
242 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
249 spin_unlock_irqrestore(&i8042_lock, flags);
255 * i8042_command() executes a command on the i8042. It also sends the input
256 * parameter(s) of the commands to it, and receives the output value(s). The
257 * parameters are to be stored in the param array, and the output is placed
258 * into the same array. The number of the parameters and output values is
259 * encoded in bits 8-11 of the command number.
262 static int __i8042_command(unsigned char *param, int command)
266 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
269 error = i8042_wait_write();
273 dbg("%02x -> i8042 (command)\n", command & 0xff);
274 i8042_write_command(command & 0xff);
276 for (i = 0; i < ((command >> 12) & 0xf); i++) {
277 error = i8042_wait_write();
280 dbg("%02x -> i8042 (parameter)\n", param[i]);
281 i8042_write_data(param[i]);
284 for (i = 0; i < ((command >> 8) & 0xf); i++) {
285 error = i8042_wait_read();
287 dbg(" -- i8042 (timeout)\n");
291 if (command == I8042_CMD_AUX_LOOP &&
292 !(i8042_read_status() & I8042_STR_AUXDATA)) {
293 dbg(" -- i8042 (auxerr)\n");
297 param[i] = i8042_read_data();
298 dbg("%02x <- i8042 (return)\n", param[i]);
304 int i8042_command(unsigned char *param, int command)
309 spin_lock_irqsave(&i8042_lock, flags);
310 retval = __i8042_command(param, command);
311 spin_unlock_irqrestore(&i8042_lock, flags);
315 EXPORT_SYMBOL(i8042_command);
318 * i8042_kbd_write() sends a byte out through the keyboard interface.
321 static int i8042_kbd_write(struct serio *port, unsigned char c)
326 spin_lock_irqsave(&i8042_lock, flags);
328 if (!(retval = i8042_wait_write())) {
329 dbg("%02x -> i8042 (kbd-data)\n", c);
333 spin_unlock_irqrestore(&i8042_lock, flags);
339 * i8042_aux_write() sends a byte out through the aux interface.
342 static int i8042_aux_write(struct serio *serio, unsigned char c)
344 struct i8042_port *port = serio->port_data;
346 return i8042_command(&c, port->mux == -1 ?
348 I8042_CMD_MUX_SEND + port->mux);
353 * i8042_aux_close attempts to clear AUX or KBD port state by disabling
354 * and then re-enabling it.
357 static void i8042_port_close(struct serio *serio)
361 const char *port_name;
363 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
364 irq_bit = I8042_CTR_AUXINT;
365 disable_bit = I8042_CTR_AUXDIS;
368 irq_bit = I8042_CTR_KBDINT;
369 disable_bit = I8042_CTR_KBDDIS;
373 i8042_ctr &= ~irq_bit;
374 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
375 pr_warn("Can't write CTR while closing %s port\n", port_name);
379 i8042_ctr &= ~disable_bit;
380 i8042_ctr |= irq_bit;
381 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
382 pr_err("Can't reactivate %s port\n", port_name);
385 * See if there is any data appeared while we were messing with
388 i8042_interrupt(0, NULL);
392 * i8042_start() is called by serio core when port is about to finish
393 * registering. It will mark port as existing so i8042_interrupt can
394 * start sending data through it.
396 static int i8042_start(struct serio *serio)
398 struct i8042_port *port = serio->port_data;
406 * i8042_stop() marks serio port as non-existing so i8042_interrupt
407 * will not try to send data to the port that is about to go away.
408 * The function is called by serio core as part of unregister procedure.
410 static void i8042_stop(struct serio *serio)
412 struct i8042_port *port = serio->port_data;
414 port->exists = false;
417 * We synchronize with both AUX and KBD IRQs because there is
418 * a (very unlikely) chance that AUX IRQ is raised for KBD port
421 synchronize_irq(I8042_AUX_IRQ);
422 synchronize_irq(I8042_KBD_IRQ);
427 * i8042_filter() filters out unwanted bytes from the input data stream.
428 * It is called from i8042_interrupt and thus is running with interrupts
429 * off and i8042_lock held.
431 static bool i8042_filter(unsigned char data, unsigned char str,
434 if (unlikely(i8042_suppress_kbd_ack)) {
435 if ((~str & I8042_STR_AUXDATA) &&
436 (data == 0xfa || data == 0xfe)) {
437 i8042_suppress_kbd_ack--;
438 dbg("Extra keyboard ACK - filtered out\n");
443 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
444 dbg("Filtered out by platform filter\n");
452 * i8042_interrupt() is the most important function in this driver -
453 * it handles the interrupts from the i8042, and sends incoming bytes
454 * to the upper layers.
457 static irqreturn_t i8042_interrupt(int irq, void *dev_id)
459 struct i8042_port *port;
462 unsigned char str, data;
464 unsigned int port_no;
468 spin_lock_irqsave(&i8042_lock, flags);
470 str = i8042_read_status();
471 if (unlikely(~str & I8042_STR_OBF)) {
472 spin_unlock_irqrestore(&i8042_lock, flags);
474 dbg("Interrupt %d, without any data\n", irq);
479 data = i8042_read_data();
481 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
482 static unsigned long last_transmit;
483 static unsigned char last_str;
486 if (str & I8042_STR_MUXERR) {
487 dbg("MUX error, status is %02x, data is %02x\n",
490 * When MUXERR condition is signalled the data register can only contain
491 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
492 * it is not always the case. Some KBCs also report 0xfc when there is
493 * nothing connected to the port while others sometimes get confused which
494 * port the data came from and signal error leaving the data intact. They
495 * _do not_ revert to legacy mode (actually I've never seen KBC reverting
496 * to legacy mode yet, when we see one we'll add proper handling).
497 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
498 * rest assume that the data came from the same serio last byte
499 * was transmitted (if transmission happened not too long ago).
504 if (time_before(jiffies, last_transmit + HZ/10)) {
508 /* fall through - report timeout */
511 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
512 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
516 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
518 last_transmit = jiffies;
521 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
522 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0);
524 port_no = (str & I8042_STR_AUXDATA) ?
525 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
528 port = &i8042_ports[port_no];
529 serio = port->exists ? port->serio : NULL;
531 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n",
533 dfl & SERIO_PARITY ? ", bad parity" : "",
534 dfl & SERIO_TIMEOUT ? ", timeout" : "");
536 filtered = i8042_filter(data, str, serio);
538 spin_unlock_irqrestore(&i8042_lock, flags);
540 if (likely(port->exists && !filtered))
541 serio_interrupt(serio, data, dfl);
544 return IRQ_RETVAL(ret);
548 * i8042_enable_kbd_port enables keyboard port on chip
551 static int i8042_enable_kbd_port(void)
553 i8042_ctr &= ~I8042_CTR_KBDDIS;
554 i8042_ctr |= I8042_CTR_KBDINT;
556 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
557 i8042_ctr &= ~I8042_CTR_KBDINT;
558 i8042_ctr |= I8042_CTR_KBDDIS;
559 pr_err("Failed to enable KBD port\n");
567 * i8042_enable_aux_port enables AUX (mouse) port on chip
570 static int i8042_enable_aux_port(void)
572 i8042_ctr &= ~I8042_CTR_AUXDIS;
573 i8042_ctr |= I8042_CTR_AUXINT;
575 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
576 i8042_ctr &= ~I8042_CTR_AUXINT;
577 i8042_ctr |= I8042_CTR_AUXDIS;
578 pr_err("Failed to enable AUX port\n");
586 * i8042_enable_mux_ports enables 4 individual AUX ports after
587 * the controller has been switched into Multiplexed mode
590 static int i8042_enable_mux_ports(void)
595 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
596 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
597 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
600 return i8042_enable_aux_port();
604 * i8042_set_mux_mode checks whether the controller has an
605 * active multiplexor and puts the chip into Multiplexed (true)
606 * or Legacy (false) mode.
609 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
612 unsigned char param, val;
614 * Get rid of bytes in the queue.
620 * Internal loopback test - send three bytes, they should come back from the
621 * mouse interface, the last should be version.
625 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
627 param = val = multiplex ? 0x56 : 0xf6;
628 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
630 param = val = multiplex ? 0xa4 : 0xa5;
631 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val)
635 * Workaround for interference with USB Legacy emulation
636 * that causes a v10.12 MUX to be found.
642 *mux_version = param;
648 * i8042_check_mux() checks whether the controller supports the PS/2 Active
649 * Multiplexing specification by Synaptics, Phoenix, Insyde and
653 static int __init i8042_check_mux(void)
655 unsigned char mux_version;
657 if (i8042_set_mux_mode(true, &mux_version))
660 pr_info("Detected active multiplexing controller, rev %d.%d\n",
661 (mux_version >> 4) & 0xf, mux_version & 0xf);
664 * Disable all muxed ports by disabling AUX.
666 i8042_ctr |= I8042_CTR_AUXDIS;
667 i8042_ctr &= ~I8042_CTR_AUXINT;
669 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
670 pr_err("Failed to disable AUX port, can't use MUX\n");
674 i8042_mux_present = true;
680 * The following is used to test AUX IRQ delivery.
682 static struct completion i8042_aux_irq_delivered __initdata;
683 static bool i8042_irq_being_tested __initdata;
685 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id)
688 unsigned char str, data;
691 spin_lock_irqsave(&i8042_lock, flags);
692 str = i8042_read_status();
693 if (str & I8042_STR_OBF) {
694 data = i8042_read_data();
695 dbg("%02x <- i8042 (aux_test_irq, %s)\n",
696 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
697 if (i8042_irq_being_tested &&
698 data == 0xa5 && (str & I8042_STR_AUXDATA))
699 complete(&i8042_aux_irq_delivered);
702 spin_unlock_irqrestore(&i8042_lock, flags);
704 return IRQ_RETVAL(ret);
708 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
709 * verifies success by readinng CTR. Used when testing for presence of AUX
712 static int __init i8042_toggle_aux(bool on)
717 if (i8042_command(¶m,
718 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
721 /* some chips need some time to set the I8042_CTR_AUXDIS bit */
722 for (i = 0; i < 100; i++) {
725 if (i8042_command(¶m, I8042_CMD_CTL_RCTR))
728 if (!(param & I8042_CTR_AUXDIS) == on)
736 * i8042_check_aux() applies as much paranoia as it can at detecting
737 * the presence of an AUX interface.
740 static int __init i8042_check_aux(void)
743 bool irq_registered = false;
744 bool aux_loop_broken = false;
749 * Get rid of bytes in the queue.
755 * Internal loopback test - filters out AT-type i8042's. Unfortunately
756 * SiS screwed up and their 5597 doesn't support the LOOP command even
757 * though it has an AUX port.
761 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP);
762 if (retval || param != 0x5a) {
765 * External connection test - filters out AT-soldered PS/2 i8042's
766 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
767 * 0xfa - no error on some notebooks which ignore the spec
768 * Because it's common for chipsets to return error on perfectly functioning
769 * AUX ports, we test for this only when the LOOP command failed.
772 if (i8042_command(¶m, I8042_CMD_AUX_TEST) ||
773 (param && param != 0xfa && param != 0xff))
777 * If AUX_LOOP completed without error but returned unexpected data
781 aux_loop_broken = true;
785 * Bit assignment test - filters out PS/2 i8042's in AT mode
788 if (i8042_toggle_aux(false)) {
789 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
790 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n");
793 if (i8042_toggle_aux(true))
797 * Reset keyboard (needed on some laptops to successfully detect
798 * touchpad, e.g., some Gigabyte laptop models with Elantech
801 if (i8042_kbdreset) {
802 pr_warn("Attempting to reset device connected to KBD port\n");
803 i8042_kbd_write(NULL, (unsigned char) 0xff);
807 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
808 * used it for a PCI card or somethig else.
811 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
813 * Without LOOP command we can't test AUX IRQ delivery. Assume the port
814 * is working and hope we are right.
820 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
821 "i8042", i8042_platform_device))
824 irq_registered = true;
826 if (i8042_enable_aux_port())
829 spin_lock_irqsave(&i8042_lock, flags);
831 init_completion(&i8042_aux_irq_delivered);
832 i8042_irq_being_tested = true;
835 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff);
837 spin_unlock_irqrestore(&i8042_lock, flags);
842 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
843 msecs_to_jiffies(250)) == 0) {
845 * AUX IRQ was never delivered so we need to flush the controller to
846 * get rid of the byte we put there; otherwise keyboard may not work.
848 dbg(" -- i8042 (aux irq test timeout)\n");
856 * Disable the interface.
859 i8042_ctr |= I8042_CTR_AUXDIS;
860 i8042_ctr &= ~I8042_CTR_AUXINT;
862 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
866 free_irq(I8042_AUX_IRQ, i8042_platform_device);
871 static int i8042_controller_check(void)
874 pr_err("No controller found\n");
881 static int i8042_controller_selftest(void)
887 * We try this 5 times; on some really fragile systems this does not
888 * take the first time...
892 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
893 pr_err("i8042 controller selftest timeout\n");
897 if (param == I8042_RET_CTL_TEST)
900 dbg("i8042 controller selftest: %#x != %#x\n",
901 param, I8042_RET_CTL_TEST);
907 * On x86, we don't fail entire i8042 initialization if controller
908 * reset fails in hopes that keyboard port will still be functional
909 * and user will still get a working keyboard. This is especially
910 * important on netbooks. On other arches we trust hardware more.
912 pr_info("giving up on controller selftest, continuing anyway...\n");
915 pr_err("i8042 controller selftest failed\n");
921 * i8042_controller init initializes the i8042 controller, and,
922 * most importantly, sets it into non-xlated mode if that's
926 static int i8042_controller_init(void)
930 unsigned char ctr[2];
933 * Save the CTR for restore on unload / reboot.
938 pr_err("Unable to get stable CTR read\n");
945 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
946 pr_err("Can't read CTR while initializing i8042\n");
950 } while (n < 2 || ctr[0] != ctr[1]);
952 i8042_initial_ctr = i8042_ctr = ctr[0];
955 * Disable the keyboard interface and interrupt.
958 i8042_ctr |= I8042_CTR_KBDDIS;
959 i8042_ctr &= ~I8042_CTR_KBDINT;
965 spin_lock_irqsave(&i8042_lock, flags);
966 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
968 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
970 pr_warn("Warning: Keylock active\n");
972 spin_unlock_irqrestore(&i8042_lock, flags);
975 * If the chip is configured into nontranslated mode by the BIOS, don't
976 * bother enabling translating and be happy.
979 if (~i8042_ctr & I8042_CTR_XLATE)
983 * Set nontranslated mode for the kbd interface if requested by an option.
984 * After this the kbd interface becomes a simple serial in/out, like the aux
985 * interface is. We don't do this by default, since it can confuse notebook
990 i8042_ctr &= ~I8042_CTR_XLATE;
996 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
997 pr_err("Can't write CTR while initializing i8042\n");
1002 * Flush whatever accumulated while we were disabling keyboard port.
1012 * Reset the controller and reset CRT to the original value set by BIOS.
1015 static void i8042_controller_reset(bool force_reset)
1020 * Disable both KBD and AUX interfaces so they don't get in the way
1023 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
1024 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
1026 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
1027 pr_warn("Can't write CTR while resetting\n");
1030 * Disable MUX mode if present.
1033 if (i8042_mux_present)
1034 i8042_set_mux_mode(false, NULL);
1037 * Reset the controller if requested.
1040 if (i8042_reset || force_reset)
1041 i8042_controller_selftest();
1044 * Restore the original control register setting.
1047 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1048 pr_warn("Can't restore CTR\n");
1053 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called
1054 * when kernel panics. Flashing LEDs is useful for users running X who may
1055 * not see the console and will help distinguishing panics from "real"
1058 * Note that DELAY has a limit of 10ms so we will not get stuck here
1059 * waiting for KBC to free up even if KBD interrupt is off
1062 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
1064 static long i8042_panic_blink(int state)
1069 led = (state) ? 0x01 | 0x04 : 0;
1070 while (i8042_read_status() & I8042_STR_IBF)
1072 dbg("%02x -> i8042 (panic blink)\n", 0xed);
1073 i8042_suppress_kbd_ack = 2;
1074 i8042_write_data(0xed); /* set leds */
1076 while (i8042_read_status() & I8042_STR_IBF)
1079 dbg("%02x -> i8042 (panic blink)\n", led);
1080 i8042_write_data(led);
1088 static void i8042_dritek_enable(void)
1090 unsigned char param = 0x90;
1093 error = i8042_command(¶m, 0x1059);
1095 pr_warn("Failed to enable DRITEK extension: %d\n", error);
1102 * Here we try to reset everything back to a state we had
1103 * before suspending.
1106 static int i8042_controller_resume(bool force_reset)
1110 error = i8042_controller_check();
1114 if (i8042_reset || force_reset) {
1115 error = i8042_controller_selftest();
1121 * Restore original CTR value and disable all ports
1124 i8042_ctr = i8042_initial_ctr;
1126 i8042_ctr &= ~I8042_CTR_XLATE;
1127 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
1128 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
1129 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1130 pr_warn("Can't write CTR to resume, retrying...\n");
1132 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1133 pr_err("CTR write retry failed\n");
1141 i8042_dritek_enable();
1144 if (i8042_mux_present) {
1145 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
1146 pr_warn("failed to resume active multiplexor, mouse won't work\n");
1147 } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
1148 i8042_enable_aux_port();
1150 if (i8042_ports[I8042_KBD_PORT_NO].serio)
1151 i8042_enable_kbd_port();
1153 i8042_interrupt(0, NULL);
1159 * Here we try to restore the original BIOS settings to avoid
1163 static int i8042_pm_suspend(struct device *dev)
1167 i8042_controller_reset(true);
1169 /* Set up serio interrupts for system wakeup. */
1170 for (i = 0; i < I8042_NUM_PORTS; i++) {
1171 struct serio *serio = i8042_ports[i].serio;
1173 if (serio && device_may_wakeup(&serio->dev))
1174 enable_irq_wake(i8042_ports[i].irq);
1180 static int i8042_pm_resume(struct device *dev)
1184 for (i = 0; i < I8042_NUM_PORTS; i++) {
1185 struct serio *serio = i8042_ports[i].serio;
1187 if (serio && device_may_wakeup(&serio->dev))
1188 disable_irq_wake(i8042_ports[i].irq);
1192 * On resume from S2R we always try to reset the controller
1193 * to bring it in a sane state. (In case of S2D we expect
1194 * BIOS to reset the controller for us.)
1196 return i8042_controller_resume(true);
1199 static int i8042_pm_thaw(struct device *dev)
1201 i8042_interrupt(0, NULL);
1206 static int i8042_pm_reset(struct device *dev)
1208 i8042_controller_reset(false);
1213 static int i8042_pm_restore(struct device *dev)
1215 return i8042_controller_resume(false);
1218 static const struct dev_pm_ops i8042_pm_ops = {
1219 .suspend = i8042_pm_suspend,
1220 .resume = i8042_pm_resume,
1221 .thaw = i8042_pm_thaw,
1222 .poweroff = i8042_pm_reset,
1223 .restore = i8042_pm_restore,
1226 #endif /* CONFIG_PM */
1229 * We need to reset the 8042 back to original mode on system shutdown,
1230 * because otherwise BIOSes will be confused.
1233 static void i8042_shutdown(struct platform_device *dev)
1235 i8042_controller_reset(false);
1238 static int __init i8042_create_kbd_port(void)
1240 struct serio *serio;
1241 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
1243 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1247 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
1248 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
1249 serio->start = i8042_start;
1250 serio->stop = i8042_stop;
1251 serio->close = i8042_port_close;
1252 serio->port_data = port;
1253 serio->dev.parent = &i8042_platform_device->dev;
1254 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
1255 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1256 strlcpy(serio->firmware_id, i8042_kbd_firmware_id,
1257 sizeof(serio->firmware_id));
1259 port->serio = serio;
1260 port->irq = I8042_KBD_IRQ;
1265 static int __init i8042_create_aux_port(int idx)
1267 struct serio *serio;
1268 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
1269 struct i8042_port *port = &i8042_ports[port_no];
1271 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1275 serio->id.type = SERIO_8042;
1276 serio->write = i8042_aux_write;
1277 serio->start = i8042_start;
1278 serio->stop = i8042_stop;
1279 serio->port_data = port;
1280 serio->dev.parent = &i8042_platform_device->dev;
1282 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
1283 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1284 strlcpy(serio->firmware_id, i8042_aux_firmware_id,
1285 sizeof(serio->firmware_id));
1286 serio->close = i8042_port_close;
1288 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
1289 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
1290 strlcpy(serio->firmware_id, i8042_aux_firmware_id,
1291 sizeof(serio->firmware_id));
1294 port->serio = serio;
1296 port->irq = I8042_AUX_IRQ;
1301 static void __init i8042_free_kbd_port(void)
1303 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
1304 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
1307 static void __init i8042_free_aux_ports(void)
1311 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
1312 kfree(i8042_ports[i].serio);
1313 i8042_ports[i].serio = NULL;
1317 static void __init i8042_register_ports(void)
1321 for (i = 0; i < I8042_NUM_PORTS; i++) {
1322 struct serio *serio = i8042_ports[i].serio;
1325 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1327 (unsigned long) I8042_DATA_REG,
1328 (unsigned long) I8042_COMMAND_REG,
1329 i8042_ports[i].irq);
1330 serio_register_port(serio);
1331 device_set_wakeup_capable(&serio->dev, true);
1336 static void i8042_unregister_ports(void)
1340 for (i = 0; i < I8042_NUM_PORTS; i++) {
1341 if (i8042_ports[i].serio) {
1342 serio_unregister_port(i8042_ports[i].serio);
1343 i8042_ports[i].serio = NULL;
1349 * Checks whether port belongs to i8042 controller.
1351 bool i8042_check_port_owner(const struct serio *port)
1355 for (i = 0; i < I8042_NUM_PORTS; i++)
1356 if (i8042_ports[i].serio == port)
1361 EXPORT_SYMBOL(i8042_check_port_owner);
1363 static void i8042_free_irqs(void)
1365 if (i8042_aux_irq_registered)
1366 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1367 if (i8042_kbd_irq_registered)
1368 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1370 i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
1373 static int __init i8042_setup_aux(void)
1375 int (*aux_enable)(void);
1379 if (i8042_check_aux())
1382 if (i8042_nomux || i8042_check_mux()) {
1383 error = i8042_create_aux_port(-1);
1385 goto err_free_ports;
1386 aux_enable = i8042_enable_aux_port;
1388 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1389 error = i8042_create_aux_port(i);
1391 goto err_free_ports;
1393 aux_enable = i8042_enable_mux_ports;
1396 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1397 "i8042", i8042_platform_device);
1399 goto err_free_ports;
1404 i8042_aux_irq_registered = true;
1408 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1410 i8042_free_aux_ports();
1414 static int __init i8042_setup_kbd(void)
1418 error = i8042_create_kbd_port();
1422 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1423 "i8042", i8042_platform_device);
1427 error = i8042_enable_kbd_port();
1431 i8042_kbd_irq_registered = true;
1435 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1437 i8042_free_kbd_port();
1441 static int __init i8042_probe(struct platform_device *dev)
1445 i8042_platform_device = dev;
1448 error = i8042_controller_selftest();
1453 error = i8042_controller_init();
1459 i8042_dritek_enable();
1463 error = i8042_setup_aux();
1464 if (error && error != -ENODEV && error != -EBUSY)
1469 error = i8042_setup_kbd();
1474 * Ok, everything is ready, let's register all serio ports
1476 i8042_register_ports();
1481 i8042_free_aux_ports(); /* in case KBD failed but AUX not */
1483 i8042_controller_reset(false);
1484 i8042_platform_device = NULL;
1489 static int i8042_remove(struct platform_device *dev)
1491 i8042_unregister_ports();
1493 i8042_controller_reset(false);
1494 i8042_platform_device = NULL;
1499 static struct platform_driver i8042_driver = {
1503 .pm = &i8042_pm_ops,
1506 .remove = i8042_remove,
1507 .shutdown = i8042_shutdown,
1510 static int __init i8042_init(void)
1512 struct platform_device *pdev;
1517 err = i8042_platform_init();
1521 err = i8042_controller_check();
1523 goto err_platform_exit;
1525 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0);
1527 err = PTR_ERR(pdev);
1528 goto err_platform_exit;
1531 panic_blink = i8042_panic_blink;
1536 i8042_platform_exit();
1540 static void __exit i8042_exit(void)
1542 platform_device_unregister(i8042_platform_device);
1543 platform_driver_unregister(&i8042_driver);
1544 i8042_platform_exit();
1549 module_init(i8042_init);
1550 module_exit(i8042_exit);