2 * i8042 keyboard and mouse controller driver for Linux
4 * Copyright (c) 1999-2004 Vojtech Pavlik
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/init.h>
21 #include <linux/serio.h>
22 #include <linux/err.h>
23 #include <linux/rcupdate.h>
24 #include <linux/platform_device.h>
25 #include <linux/i8042.h>
26 #include <linux/slab.h>
30 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
31 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
32 MODULE_LICENSE("GPL");
34 static bool i8042_nokbd;
35 module_param_named(nokbd, i8042_nokbd, bool, 0);
36 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
38 static bool i8042_noaux;
39 module_param_named(noaux, i8042_noaux, bool, 0);
40 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
42 static bool i8042_nomux;
43 module_param_named(nomux, i8042_nomux, bool, 0);
44 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
46 static bool i8042_unlock;
47 module_param_named(unlock, i8042_unlock, bool, 0);
48 MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
50 static bool i8042_reset;
51 module_param_named(reset, i8042_reset, bool, 0);
52 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
54 static bool i8042_direct;
55 module_param_named(direct, i8042_direct, bool, 0);
56 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
58 static bool i8042_dumbkbd;
59 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
60 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
62 static bool i8042_noloop;
63 module_param_named(noloop, i8042_noloop, bool, 0);
64 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
66 static bool i8042_notimeout;
67 module_param_named(notimeout, i8042_notimeout, bool, 0);
68 MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042");
71 static bool i8042_dritek;
72 module_param_named(dritek, i8042_dritek, bool, 0);
73 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
77 static bool i8042_nopnp;
78 module_param_named(nopnp, i8042_nopnp, bool, 0);
79 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
84 static bool i8042_debug;
85 module_param_named(debug, i8042_debug, bool, 0600);
86 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
89 static bool i8042_bypass_aux_irq_test;
90 static char i8042_kbd_firmware_id[128];
91 static char i8042_aux_firmware_id[128];
96 * i8042_lock protects serialization between i8042_command and
97 * the interrupt handler.
99 static DEFINE_SPINLOCK(i8042_lock);
102 * Writers to AUX and KBD ports as well as users issuing i8042_command
103 * directly should acquire i8042_mutex (by means of calling
104 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that
105 * they do not disturb each other (unfortunately in many i8042
106 * implementations write to one of the ports will immediately abort
107 * command that is being processed by another port).
109 static DEFINE_MUTEX(i8042_mutex);
118 #define I8042_KBD_PORT_NO 0
119 #define I8042_AUX_PORT_NO 1
120 #define I8042_MUX_PORT_NO 2
121 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
123 static struct i8042_port i8042_ports[I8042_NUM_PORTS];
125 static unsigned char i8042_initial_ctr;
126 static unsigned char i8042_ctr;
127 static bool i8042_mux_present;
128 static bool i8042_kbd_irq_registered;
129 static bool i8042_aux_irq_registered;
130 static unsigned char i8042_suppress_kbd_ack;
131 static struct platform_device *i8042_platform_device;
133 static irqreturn_t i8042_interrupt(int irq, void *dev_id);
134 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
135 struct serio *serio);
137 void i8042_lock_chip(void)
139 mutex_lock(&i8042_mutex);
141 EXPORT_SYMBOL(i8042_lock_chip);
143 void i8042_unlock_chip(void)
145 mutex_unlock(&i8042_mutex);
147 EXPORT_SYMBOL(i8042_unlock_chip);
149 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
150 struct serio *serio))
155 spin_lock_irqsave(&i8042_lock, flags);
157 if (i8042_platform_filter) {
162 i8042_platform_filter = filter;
165 spin_unlock_irqrestore(&i8042_lock, flags);
168 EXPORT_SYMBOL(i8042_install_filter);
170 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
176 spin_lock_irqsave(&i8042_lock, flags);
178 if (i8042_platform_filter != filter) {
183 i8042_platform_filter = NULL;
186 spin_unlock_irqrestore(&i8042_lock, flags);
189 EXPORT_SYMBOL(i8042_remove_filter);
192 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
193 * be ready for reading values from it / writing values to it.
194 * Called always with i8042_lock held.
197 static int i8042_wait_read(void)
201 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
205 return -(i == I8042_CTL_TIMEOUT);
208 static int i8042_wait_write(void)
212 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
216 return -(i == I8042_CTL_TIMEOUT);
220 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
221 * of the i8042 down the toilet.
224 static int i8042_flush(void)
227 unsigned char data, str;
231 spin_lock_irqsave(&i8042_lock, flags);
233 while ((str = i8042_read_status()) & I8042_STR_OBF) {
234 if (count++ < I8042_BUFFER_SIZE) {
236 data = i8042_read_data();
237 dbg("%02x <- i8042 (flush, %s)\n",
238 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
245 spin_unlock_irqrestore(&i8042_lock, flags);
251 * i8042_command() executes a command on the i8042. It also sends the input
252 * parameter(s) of the commands to it, and receives the output value(s). The
253 * parameters are to be stored in the param array, and the output is placed
254 * into the same array. The number of the parameters and output values is
255 * encoded in bits 8-11 of the command number.
258 static int __i8042_command(unsigned char *param, int command)
262 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
265 error = i8042_wait_write();
269 dbg("%02x -> i8042 (command)\n", command & 0xff);
270 i8042_write_command(command & 0xff);
272 for (i = 0; i < ((command >> 12) & 0xf); i++) {
273 error = i8042_wait_write();
276 dbg("%02x -> i8042 (parameter)\n", param[i]);
277 i8042_write_data(param[i]);
280 for (i = 0; i < ((command >> 8) & 0xf); i++) {
281 error = i8042_wait_read();
283 dbg(" -- i8042 (timeout)\n");
287 if (command == I8042_CMD_AUX_LOOP &&
288 !(i8042_read_status() & I8042_STR_AUXDATA)) {
289 dbg(" -- i8042 (auxerr)\n");
293 param[i] = i8042_read_data();
294 dbg("%02x <- i8042 (return)\n", param[i]);
300 int i8042_command(unsigned char *param, int command)
305 spin_lock_irqsave(&i8042_lock, flags);
306 retval = __i8042_command(param, command);
307 spin_unlock_irqrestore(&i8042_lock, flags);
311 EXPORT_SYMBOL(i8042_command);
314 * i8042_kbd_write() sends a byte out through the keyboard interface.
317 static int i8042_kbd_write(struct serio *port, unsigned char c)
322 spin_lock_irqsave(&i8042_lock, flags);
324 if (!(retval = i8042_wait_write())) {
325 dbg("%02x -> i8042 (kbd-data)\n", c);
329 spin_unlock_irqrestore(&i8042_lock, flags);
335 * i8042_aux_write() sends a byte out through the aux interface.
338 static int i8042_aux_write(struct serio *serio, unsigned char c)
340 struct i8042_port *port = serio->port_data;
342 return i8042_command(&c, port->mux == -1 ?
344 I8042_CMD_MUX_SEND + port->mux);
349 * i8042_aux_close attempts to clear AUX or KBD port state by disabling
350 * and then re-enabling it.
353 static void i8042_port_close(struct serio *serio)
357 const char *port_name;
359 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
360 irq_bit = I8042_CTR_AUXINT;
361 disable_bit = I8042_CTR_AUXDIS;
364 irq_bit = I8042_CTR_KBDINT;
365 disable_bit = I8042_CTR_KBDDIS;
369 i8042_ctr &= ~irq_bit;
370 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
371 pr_warn("Can't write CTR while closing %s port\n", port_name);
375 i8042_ctr &= ~disable_bit;
376 i8042_ctr |= irq_bit;
377 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
378 pr_err("Can't reactivate %s port\n", port_name);
381 * See if there is any data appeared while we were messing with
384 i8042_interrupt(0, NULL);
388 * i8042_start() is called by serio core when port is about to finish
389 * registering. It will mark port as existing so i8042_interrupt can
390 * start sending data through it.
392 static int i8042_start(struct serio *serio)
394 struct i8042_port *port = serio->port_data;
402 * i8042_stop() marks serio port as non-existing so i8042_interrupt
403 * will not try to send data to the port that is about to go away.
404 * The function is called by serio core as part of unregister procedure.
406 static void i8042_stop(struct serio *serio)
408 struct i8042_port *port = serio->port_data;
410 port->exists = false;
413 * We synchronize with both AUX and KBD IRQs because there is
414 * a (very unlikely) chance that AUX IRQ is raised for KBD port
417 synchronize_irq(I8042_AUX_IRQ);
418 synchronize_irq(I8042_KBD_IRQ);
423 * i8042_filter() filters out unwanted bytes from the input data stream.
424 * It is called from i8042_interrupt and thus is running with interrupts
425 * off and i8042_lock held.
427 static bool i8042_filter(unsigned char data, unsigned char str,
430 if (unlikely(i8042_suppress_kbd_ack)) {
431 if ((~str & I8042_STR_AUXDATA) &&
432 (data == 0xfa || data == 0xfe)) {
433 i8042_suppress_kbd_ack--;
434 dbg("Extra keyboard ACK - filtered out\n");
439 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
440 dbg("Filtered out by platform filter\n");
448 * i8042_interrupt() is the most important function in this driver -
449 * it handles the interrupts from the i8042, and sends incoming bytes
450 * to the upper layers.
453 static irqreturn_t i8042_interrupt(int irq, void *dev_id)
455 struct i8042_port *port;
458 unsigned char str, data;
460 unsigned int port_no;
464 spin_lock_irqsave(&i8042_lock, flags);
466 str = i8042_read_status();
467 if (unlikely(~str & I8042_STR_OBF)) {
468 spin_unlock_irqrestore(&i8042_lock, flags);
470 dbg("Interrupt %d, without any data\n", irq);
475 data = i8042_read_data();
477 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
478 static unsigned long last_transmit;
479 static unsigned char last_str;
482 if (str & I8042_STR_MUXERR) {
483 dbg("MUX error, status is %02x, data is %02x\n",
486 * When MUXERR condition is signalled the data register can only contain
487 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
488 * it is not always the case. Some KBCs also report 0xfc when there is
489 * nothing connected to the port while others sometimes get confused which
490 * port the data came from and signal error leaving the data intact. They
491 * _do not_ revert to legacy mode (actually I've never seen KBC reverting
492 * to legacy mode yet, when we see one we'll add proper handling).
493 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
494 * rest assume that the data came from the same serio last byte
495 * was transmitted (if transmission happened not too long ago).
500 if (time_before(jiffies, last_transmit + HZ/10)) {
504 /* fall through - report timeout */
507 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
508 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
512 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
514 last_transmit = jiffies;
517 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
518 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0);
520 port_no = (str & I8042_STR_AUXDATA) ?
521 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
524 port = &i8042_ports[port_no];
525 serio = port->exists ? port->serio : NULL;
527 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n",
529 dfl & SERIO_PARITY ? ", bad parity" : "",
530 dfl & SERIO_TIMEOUT ? ", timeout" : "");
532 filtered = i8042_filter(data, str, serio);
534 spin_unlock_irqrestore(&i8042_lock, flags);
536 if (likely(port->exists && !filtered))
537 serio_interrupt(serio, data, dfl);
540 return IRQ_RETVAL(ret);
544 * i8042_enable_kbd_port enables keyboard port on chip
547 static int i8042_enable_kbd_port(void)
549 i8042_ctr &= ~I8042_CTR_KBDDIS;
550 i8042_ctr |= I8042_CTR_KBDINT;
552 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
553 i8042_ctr &= ~I8042_CTR_KBDINT;
554 i8042_ctr |= I8042_CTR_KBDDIS;
555 pr_err("Failed to enable KBD port\n");
563 * i8042_enable_aux_port enables AUX (mouse) port on chip
566 static int i8042_enable_aux_port(void)
568 i8042_ctr &= ~I8042_CTR_AUXDIS;
569 i8042_ctr |= I8042_CTR_AUXINT;
571 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
572 i8042_ctr &= ~I8042_CTR_AUXINT;
573 i8042_ctr |= I8042_CTR_AUXDIS;
574 pr_err("Failed to enable AUX port\n");
582 * i8042_enable_mux_ports enables 4 individual AUX ports after
583 * the controller has been switched into Multiplexed mode
586 static int i8042_enable_mux_ports(void)
591 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
592 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
593 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
596 return i8042_enable_aux_port();
600 * i8042_set_mux_mode checks whether the controller has an
601 * active multiplexor and puts the chip into Multiplexed (true)
602 * or Legacy (false) mode.
605 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
608 unsigned char param, val;
610 * Get rid of bytes in the queue.
616 * Internal loopback test - send three bytes, they should come back from the
617 * mouse interface, the last should be version.
621 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
623 param = val = multiplex ? 0x56 : 0xf6;
624 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
626 param = val = multiplex ? 0xa4 : 0xa5;
627 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val)
631 * Workaround for interference with USB Legacy emulation
632 * that causes a v10.12 MUX to be found.
638 *mux_version = param;
644 * i8042_check_mux() checks whether the controller supports the PS/2 Active
645 * Multiplexing specification by Synaptics, Phoenix, Insyde and
649 static int __init i8042_check_mux(void)
651 unsigned char mux_version;
653 if (i8042_set_mux_mode(true, &mux_version))
656 pr_info("Detected active multiplexing controller, rev %d.%d\n",
657 (mux_version >> 4) & 0xf, mux_version & 0xf);
660 * Disable all muxed ports by disabling AUX.
662 i8042_ctr |= I8042_CTR_AUXDIS;
663 i8042_ctr &= ~I8042_CTR_AUXINT;
665 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
666 pr_err("Failed to disable AUX port, can't use MUX\n");
670 i8042_mux_present = true;
676 * The following is used to test AUX IRQ delivery.
678 static struct completion i8042_aux_irq_delivered __initdata;
679 static bool i8042_irq_being_tested __initdata;
681 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id)
684 unsigned char str, data;
687 spin_lock_irqsave(&i8042_lock, flags);
688 str = i8042_read_status();
689 if (str & I8042_STR_OBF) {
690 data = i8042_read_data();
691 dbg("%02x <- i8042 (aux_test_irq, %s)\n",
692 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
693 if (i8042_irq_being_tested &&
694 data == 0xa5 && (str & I8042_STR_AUXDATA))
695 complete(&i8042_aux_irq_delivered);
698 spin_unlock_irqrestore(&i8042_lock, flags);
700 return IRQ_RETVAL(ret);
704 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
705 * verifies success by readinng CTR. Used when testing for presence of AUX
708 static int __init i8042_toggle_aux(bool on)
713 if (i8042_command(¶m,
714 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
717 /* some chips need some time to set the I8042_CTR_AUXDIS bit */
718 for (i = 0; i < 100; i++) {
721 if (i8042_command(¶m, I8042_CMD_CTL_RCTR))
724 if (!(param & I8042_CTR_AUXDIS) == on)
732 * i8042_check_aux() applies as much paranoia as it can at detecting
733 * the presence of an AUX interface.
736 static int __init i8042_check_aux(void)
739 bool irq_registered = false;
740 bool aux_loop_broken = false;
745 * Get rid of bytes in the queue.
751 * Internal loopback test - filters out AT-type i8042's. Unfortunately
752 * SiS screwed up and their 5597 doesn't support the LOOP command even
753 * though it has an AUX port.
757 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP);
758 if (retval || param != 0x5a) {
761 * External connection test - filters out AT-soldered PS/2 i8042's
762 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
763 * 0xfa - no error on some notebooks which ignore the spec
764 * Because it's common for chipsets to return error on perfectly functioning
765 * AUX ports, we test for this only when the LOOP command failed.
768 if (i8042_command(¶m, I8042_CMD_AUX_TEST) ||
769 (param && param != 0xfa && param != 0xff))
773 * If AUX_LOOP completed without error but returned unexpected data
777 aux_loop_broken = true;
781 * Bit assignment test - filters out PS/2 i8042's in AT mode
784 if (i8042_toggle_aux(false)) {
785 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
786 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n");
789 if (i8042_toggle_aux(true))
793 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
794 * used it for a PCI card or somethig else.
797 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
799 * Without LOOP command we can't test AUX IRQ delivery. Assume the port
800 * is working and hope we are right.
806 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
807 "i8042", i8042_platform_device))
810 irq_registered = true;
812 if (i8042_enable_aux_port())
815 spin_lock_irqsave(&i8042_lock, flags);
817 init_completion(&i8042_aux_irq_delivered);
818 i8042_irq_being_tested = true;
821 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff);
823 spin_unlock_irqrestore(&i8042_lock, flags);
828 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
829 msecs_to_jiffies(250)) == 0) {
831 * AUX IRQ was never delivered so we need to flush the controller to
832 * get rid of the byte we put there; otherwise keyboard may not work.
834 dbg(" -- i8042 (aux irq test timeout)\n");
842 * Disable the interface.
845 i8042_ctr |= I8042_CTR_AUXDIS;
846 i8042_ctr &= ~I8042_CTR_AUXINT;
848 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
852 free_irq(I8042_AUX_IRQ, i8042_platform_device);
857 static int i8042_controller_check(void)
860 pr_err("No controller found\n");
867 static int i8042_controller_selftest(void)
873 * We try this 5 times; on some really fragile systems this does not
874 * take the first time...
878 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
879 pr_err("i8042 controller selftest timeout\n");
883 if (param == I8042_RET_CTL_TEST)
886 dbg("i8042 controller selftest: %#x != %#x\n",
887 param, I8042_RET_CTL_TEST);
893 * On x86, we don't fail entire i8042 initialization if controller
894 * reset fails in hopes that keyboard port will still be functional
895 * and user will still get a working keyboard. This is especially
896 * important on netbooks. On other arches we trust hardware more.
898 pr_info("giving up on controller selftest, continuing anyway...\n");
901 pr_err("i8042 controller selftest failed\n");
907 * i8042_controller init initializes the i8042 controller, and,
908 * most importantly, sets it into non-xlated mode if that's
912 static int i8042_controller_init(void)
916 unsigned char ctr[2];
919 * Save the CTR for restore on unload / reboot.
924 pr_err("Unable to get stable CTR read\n");
931 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
932 pr_err("Can't read CTR while initializing i8042\n");
936 } while (n < 2 || ctr[0] != ctr[1]);
938 i8042_initial_ctr = i8042_ctr = ctr[0];
941 * Disable the keyboard interface and interrupt.
944 i8042_ctr |= I8042_CTR_KBDDIS;
945 i8042_ctr &= ~I8042_CTR_KBDINT;
951 spin_lock_irqsave(&i8042_lock, flags);
952 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
954 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
956 pr_warn("Warning: Keylock active\n");
958 spin_unlock_irqrestore(&i8042_lock, flags);
961 * If the chip is configured into nontranslated mode by the BIOS, don't
962 * bother enabling translating and be happy.
965 if (~i8042_ctr & I8042_CTR_XLATE)
969 * Set nontranslated mode for the kbd interface if requested by an option.
970 * After this the kbd interface becomes a simple serial in/out, like the aux
971 * interface is. We don't do this by default, since it can confuse notebook
976 i8042_ctr &= ~I8042_CTR_XLATE;
982 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
983 pr_err("Can't write CTR while initializing i8042\n");
988 * Flush whatever accumulated while we were disabling keyboard port.
998 * Reset the controller and reset CRT to the original value set by BIOS.
1001 static void i8042_controller_reset(bool force_reset)
1006 * Disable both KBD and AUX interfaces so they don't get in the way
1009 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
1010 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
1012 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
1013 pr_warn("Can't write CTR while resetting\n");
1016 * Disable MUX mode if present.
1019 if (i8042_mux_present)
1020 i8042_set_mux_mode(false, NULL);
1023 * Reset the controller if requested.
1026 if (i8042_reset || force_reset)
1027 i8042_controller_selftest();
1030 * Restore the original control register setting.
1033 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1034 pr_warn("Can't restore CTR\n");
1039 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called
1040 * when kernel panics. Flashing LEDs is useful for users running X who may
1041 * not see the console and will help distinguishing panics from "real"
1044 * Note that DELAY has a limit of 10ms so we will not get stuck here
1045 * waiting for KBC to free up even if KBD interrupt is off
1048 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
1050 static long i8042_panic_blink(int state)
1055 led = (state) ? 0x01 | 0x04 : 0;
1056 while (i8042_read_status() & I8042_STR_IBF)
1058 dbg("%02x -> i8042 (panic blink)\n", 0xed);
1059 i8042_suppress_kbd_ack = 2;
1060 i8042_write_data(0xed); /* set leds */
1062 while (i8042_read_status() & I8042_STR_IBF)
1065 dbg("%02x -> i8042 (panic blink)\n", led);
1066 i8042_write_data(led);
1074 static void i8042_dritek_enable(void)
1076 unsigned char param = 0x90;
1079 error = i8042_command(¶m, 0x1059);
1081 pr_warn("Failed to enable DRITEK extension: %d\n", error);
1088 * Here we try to reset everything back to a state we had
1089 * before suspending.
1092 static int i8042_controller_resume(bool force_reset)
1096 error = i8042_controller_check();
1100 if (i8042_reset || force_reset) {
1101 error = i8042_controller_selftest();
1107 * Restore original CTR value and disable all ports
1110 i8042_ctr = i8042_initial_ctr;
1112 i8042_ctr &= ~I8042_CTR_XLATE;
1113 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
1114 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
1115 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1116 pr_warn("Can't write CTR to resume, retrying...\n");
1118 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1119 pr_err("CTR write retry failed\n");
1127 i8042_dritek_enable();
1130 if (i8042_mux_present) {
1131 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
1132 pr_warn("failed to resume active multiplexor, mouse won't work\n");
1133 } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
1134 i8042_enable_aux_port();
1136 if (i8042_ports[I8042_KBD_PORT_NO].serio)
1137 i8042_enable_kbd_port();
1139 i8042_interrupt(0, NULL);
1145 * Here we try to restore the original BIOS settings to avoid
1149 static int i8042_pm_suspend(struct device *dev)
1151 i8042_controller_reset(true);
1156 static int i8042_pm_resume(struct device *dev)
1159 * On resume from S2R we always try to reset the controller
1160 * to bring it in a sane state. (In case of S2D we expect
1161 * BIOS to reset the controller for us.)
1163 return i8042_controller_resume(true);
1166 static int i8042_pm_thaw(struct device *dev)
1168 i8042_interrupt(0, NULL);
1173 static int i8042_pm_reset(struct device *dev)
1175 i8042_controller_reset(false);
1180 static int i8042_pm_restore(struct device *dev)
1182 return i8042_controller_resume(false);
1185 static const struct dev_pm_ops i8042_pm_ops = {
1186 .suspend = i8042_pm_suspend,
1187 .resume = i8042_pm_resume,
1188 .thaw = i8042_pm_thaw,
1189 .poweroff = i8042_pm_reset,
1190 .restore = i8042_pm_restore,
1193 #endif /* CONFIG_PM */
1196 * We need to reset the 8042 back to original mode on system shutdown,
1197 * because otherwise BIOSes will be confused.
1200 static void i8042_shutdown(struct platform_device *dev)
1202 i8042_controller_reset(false);
1205 static int __init i8042_create_kbd_port(void)
1207 struct serio *serio;
1208 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
1210 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1214 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
1215 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
1216 serio->start = i8042_start;
1217 serio->stop = i8042_stop;
1218 serio->close = i8042_port_close;
1219 serio->port_data = port;
1220 serio->dev.parent = &i8042_platform_device->dev;
1221 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
1222 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1223 strlcpy(serio->firmware_id, i8042_kbd_firmware_id,
1224 sizeof(serio->firmware_id));
1226 port->serio = serio;
1227 port->irq = I8042_KBD_IRQ;
1232 static int __init i8042_create_aux_port(int idx)
1234 struct serio *serio;
1235 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
1236 struct i8042_port *port = &i8042_ports[port_no];
1238 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1242 serio->id.type = SERIO_8042;
1243 serio->write = i8042_aux_write;
1244 serio->start = i8042_start;
1245 serio->stop = i8042_stop;
1246 serio->port_data = port;
1247 serio->dev.parent = &i8042_platform_device->dev;
1249 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
1250 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1251 strlcpy(serio->firmware_id, i8042_aux_firmware_id,
1252 sizeof(serio->firmware_id));
1253 serio->close = i8042_port_close;
1255 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
1256 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
1257 strlcpy(serio->firmware_id, i8042_aux_firmware_id,
1258 sizeof(serio->firmware_id));
1261 port->serio = serio;
1263 port->irq = I8042_AUX_IRQ;
1268 static void __init i8042_free_kbd_port(void)
1270 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
1271 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
1274 static void __init i8042_free_aux_ports(void)
1278 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
1279 kfree(i8042_ports[i].serio);
1280 i8042_ports[i].serio = NULL;
1284 static void __init i8042_register_ports(void)
1288 for (i = 0; i < I8042_NUM_PORTS; i++) {
1289 if (i8042_ports[i].serio) {
1290 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1291 i8042_ports[i].serio->name,
1292 (unsigned long) I8042_DATA_REG,
1293 (unsigned long) I8042_COMMAND_REG,
1294 i8042_ports[i].irq);
1295 serio_register_port(i8042_ports[i].serio);
1300 static void i8042_unregister_ports(void)
1304 for (i = 0; i < I8042_NUM_PORTS; i++) {
1305 if (i8042_ports[i].serio) {
1306 serio_unregister_port(i8042_ports[i].serio);
1307 i8042_ports[i].serio = NULL;
1313 * Checks whether port belongs to i8042 controller.
1315 bool i8042_check_port_owner(const struct serio *port)
1319 for (i = 0; i < I8042_NUM_PORTS; i++)
1320 if (i8042_ports[i].serio == port)
1325 EXPORT_SYMBOL(i8042_check_port_owner);
1327 static void i8042_free_irqs(void)
1329 if (i8042_aux_irq_registered)
1330 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1331 if (i8042_kbd_irq_registered)
1332 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1334 i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
1337 static int __init i8042_setup_aux(void)
1339 int (*aux_enable)(void);
1343 if (i8042_check_aux())
1346 if (i8042_nomux || i8042_check_mux()) {
1347 error = i8042_create_aux_port(-1);
1349 goto err_free_ports;
1350 aux_enable = i8042_enable_aux_port;
1352 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1353 error = i8042_create_aux_port(i);
1355 goto err_free_ports;
1357 aux_enable = i8042_enable_mux_ports;
1360 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1361 "i8042", i8042_platform_device);
1363 goto err_free_ports;
1368 i8042_aux_irq_registered = true;
1372 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1374 i8042_free_aux_ports();
1378 static int __init i8042_setup_kbd(void)
1382 error = i8042_create_kbd_port();
1386 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1387 "i8042", i8042_platform_device);
1391 error = i8042_enable_kbd_port();
1395 i8042_kbd_irq_registered = true;
1399 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1401 i8042_free_kbd_port();
1405 static int __init i8042_probe(struct platform_device *dev)
1409 i8042_platform_device = dev;
1412 error = i8042_controller_selftest();
1417 error = i8042_controller_init();
1423 i8042_dritek_enable();
1427 error = i8042_setup_aux();
1428 if (error && error != -ENODEV && error != -EBUSY)
1433 error = i8042_setup_kbd();
1438 * Ok, everything is ready, let's register all serio ports
1440 i8042_register_ports();
1445 i8042_free_aux_ports(); /* in case KBD failed but AUX not */
1447 i8042_controller_reset(false);
1448 i8042_platform_device = NULL;
1453 static int i8042_remove(struct platform_device *dev)
1455 i8042_unregister_ports();
1457 i8042_controller_reset(false);
1458 i8042_platform_device = NULL;
1463 static struct platform_driver i8042_driver = {
1466 .owner = THIS_MODULE,
1468 .pm = &i8042_pm_ops,
1471 .remove = i8042_remove,
1472 .shutdown = i8042_shutdown,
1475 static int __init i8042_init(void)
1477 struct platform_device *pdev;
1482 err = i8042_platform_init();
1486 err = i8042_controller_check();
1488 goto err_platform_exit;
1490 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0);
1492 err = PTR_ERR(pdev);
1493 goto err_platform_exit;
1496 panic_blink = i8042_panic_blink;
1501 i8042_platform_exit();
1505 static void __exit i8042_exit(void)
1507 platform_device_unregister(i8042_platform_device);
1508 platform_driver_unregister(&i8042_driver);
1509 i8042_platform_exit();
1514 module_init(i8042_init);
1515 module_exit(i8042_exit);