2 * IOMMU API for ARM architected SMMU implementations.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 * Copyright (C) 2013 ARM Limited
19 * Author: Will Deacon <will.deacon@arm.com>
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - Context fault reporting
29 #define pr_fmt(fmt) "arm-smmu: " fmt
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/interrupt.h>
36 #include <linux/iommu.h>
37 #include <linux/iopoll.h>
38 #include <linux/module.h>
40 #include <linux/pci.h>
41 #include <linux/platform_device.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
45 #include <linux/amba/bus.h>
47 #include "io-pgtable.h"
49 /* Maximum number of stream IDs assigned to a single device */
50 #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
52 /* Maximum number of context banks per SMMU */
53 #define ARM_SMMU_MAX_CBS 128
55 /* Maximum number of mapping groups per SMMU */
56 #define ARM_SMMU_MAX_SMRS 128
58 /* SMMU global address space */
59 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
60 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
63 * SMMU global address space with conditional offset to access secure
64 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
67 #define ARM_SMMU_GR0_NS(smmu) \
69 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
72 /* Configuration registers */
73 #define ARM_SMMU_GR0_sCR0 0x0
74 #define sCR0_CLIENTPD (1 << 0)
75 #define sCR0_GFRE (1 << 1)
76 #define sCR0_GFIE (1 << 2)
77 #define sCR0_GCFGFRE (1 << 4)
78 #define sCR0_GCFGFIE (1 << 5)
79 #define sCR0_USFCFG (1 << 10)
80 #define sCR0_VMIDPNE (1 << 11)
81 #define sCR0_PTM (1 << 12)
82 #define sCR0_FB (1 << 13)
83 #define sCR0_BSU_SHIFT 14
84 #define sCR0_BSU_MASK 0x3
86 /* Identification registers */
87 #define ARM_SMMU_GR0_ID0 0x20
88 #define ARM_SMMU_GR0_ID1 0x24
89 #define ARM_SMMU_GR0_ID2 0x28
90 #define ARM_SMMU_GR0_ID3 0x2c
91 #define ARM_SMMU_GR0_ID4 0x30
92 #define ARM_SMMU_GR0_ID5 0x34
93 #define ARM_SMMU_GR0_ID6 0x38
94 #define ARM_SMMU_GR0_ID7 0x3c
95 #define ARM_SMMU_GR0_sGFSR 0x48
96 #define ARM_SMMU_GR0_sGFSYNR0 0x50
97 #define ARM_SMMU_GR0_sGFSYNR1 0x54
98 #define ARM_SMMU_GR0_sGFSYNR2 0x58
100 #define ID0_S1TS (1 << 30)
101 #define ID0_S2TS (1 << 29)
102 #define ID0_NTS (1 << 28)
103 #define ID0_SMS (1 << 27)
104 #define ID0_ATOSNS (1 << 26)
105 #define ID0_CTTW (1 << 14)
106 #define ID0_NUMIRPT_SHIFT 16
107 #define ID0_NUMIRPT_MASK 0xff
108 #define ID0_NUMSIDB_SHIFT 9
109 #define ID0_NUMSIDB_MASK 0xf
110 #define ID0_NUMSMRG_SHIFT 0
111 #define ID0_NUMSMRG_MASK 0xff
113 #define ID1_PAGESIZE (1 << 31)
114 #define ID1_NUMPAGENDXB_SHIFT 28
115 #define ID1_NUMPAGENDXB_MASK 7
116 #define ID1_NUMS2CB_SHIFT 16
117 #define ID1_NUMS2CB_MASK 0xff
118 #define ID1_NUMCB_SHIFT 0
119 #define ID1_NUMCB_MASK 0xff
121 #define ID2_OAS_SHIFT 4
122 #define ID2_OAS_MASK 0xf
123 #define ID2_IAS_SHIFT 0
124 #define ID2_IAS_MASK 0xf
125 #define ID2_UBS_SHIFT 8
126 #define ID2_UBS_MASK 0xf
127 #define ID2_PTFS_4K (1 << 12)
128 #define ID2_PTFS_16K (1 << 13)
129 #define ID2_PTFS_64K (1 << 14)
131 /* Global TLB invalidation */
132 #define ARM_SMMU_GR0_TLBIVMID 0x64
133 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
134 #define ARM_SMMU_GR0_TLBIALLH 0x6c
135 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
136 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
137 #define sTLBGSTATUS_GSACTIVE (1 << 0)
138 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
140 /* Stream mapping registers */
141 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
142 #define SMR_VALID (1 << 31)
143 #define SMR_MASK_SHIFT 16
144 #define SMR_MASK_MASK 0x7fff
145 #define SMR_ID_SHIFT 0
146 #define SMR_ID_MASK 0x7fff
148 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
149 #define S2CR_CBNDX_SHIFT 0
150 #define S2CR_CBNDX_MASK 0xff
151 #define S2CR_TYPE_SHIFT 16
152 #define S2CR_TYPE_MASK 0x3
153 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
154 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
155 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
157 /* Context bank attribute registers */
158 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
159 #define CBAR_VMID_SHIFT 0
160 #define CBAR_VMID_MASK 0xff
161 #define CBAR_S1_BPSHCFG_SHIFT 8
162 #define CBAR_S1_BPSHCFG_MASK 3
163 #define CBAR_S1_BPSHCFG_NSH 3
164 #define CBAR_S1_MEMATTR_SHIFT 12
165 #define CBAR_S1_MEMATTR_MASK 0xf
166 #define CBAR_S1_MEMATTR_WB 0xf
167 #define CBAR_TYPE_SHIFT 16
168 #define CBAR_TYPE_MASK 0x3
169 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
170 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
171 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
172 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
173 #define CBAR_IRPTNDX_SHIFT 24
174 #define CBAR_IRPTNDX_MASK 0xff
176 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
177 #define CBA2R_RW64_32BIT (0 << 0)
178 #define CBA2R_RW64_64BIT (1 << 0)
180 /* Translation context bank */
181 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
182 #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift))
184 #define ARM_SMMU_CB_SCTLR 0x0
185 #define ARM_SMMU_CB_RESUME 0x8
186 #define ARM_SMMU_CB_TTBCR2 0x10
187 #define ARM_SMMU_CB_TTBR0_LO 0x20
188 #define ARM_SMMU_CB_TTBR0_HI 0x24
189 #define ARM_SMMU_CB_TTBR1_LO 0x28
190 #define ARM_SMMU_CB_TTBR1_HI 0x2c
191 #define ARM_SMMU_CB_TTBCR 0x30
192 #define ARM_SMMU_CB_S1_MAIR0 0x38
193 #define ARM_SMMU_CB_S1_MAIR1 0x3c
194 #define ARM_SMMU_CB_PAR_LO 0x50
195 #define ARM_SMMU_CB_PAR_HI 0x54
196 #define ARM_SMMU_CB_FSR 0x58
197 #define ARM_SMMU_CB_FAR_LO 0x60
198 #define ARM_SMMU_CB_FAR_HI 0x64
199 #define ARM_SMMU_CB_FSYNR0 0x68
200 #define ARM_SMMU_CB_S1_TLBIVA 0x600
201 #define ARM_SMMU_CB_S1_TLBIASID 0x610
202 #define ARM_SMMU_CB_S1_TLBIVAL 0x620
203 #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
204 #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
205 #define ARM_SMMU_CB_ATS1PR 0x800
206 #define ARM_SMMU_CB_ATSR 0x8f0
208 #define SCTLR_S1_ASIDPNE (1 << 12)
209 #define SCTLR_CFCFG (1 << 7)
210 #define SCTLR_CFIE (1 << 6)
211 #define SCTLR_CFRE (1 << 5)
212 #define SCTLR_E (1 << 4)
213 #define SCTLR_AFE (1 << 2)
214 #define SCTLR_TRE (1 << 1)
215 #define SCTLR_M (1 << 0)
216 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
218 #define CB_PAR_F (1 << 0)
220 #define ATSR_ACTIVE (1 << 0)
222 #define RESUME_RETRY (0 << 0)
223 #define RESUME_TERMINATE (1 << 0)
225 #define TTBCR2_SEP_SHIFT 15
226 #define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
228 #define TTBRn_HI_ASID_SHIFT 16
230 #define FSR_MULTI (1 << 31)
231 #define FSR_SS (1 << 30)
232 #define FSR_UUT (1 << 8)
233 #define FSR_ASF (1 << 7)
234 #define FSR_TLBLKF (1 << 6)
235 #define FSR_TLBMCF (1 << 5)
236 #define FSR_EF (1 << 4)
237 #define FSR_PF (1 << 3)
238 #define FSR_AFF (1 << 2)
239 #define FSR_TF (1 << 1)
241 #define FSR_IGN (FSR_AFF | FSR_ASF | \
242 FSR_TLBMCF | FSR_TLBLKF)
243 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
244 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
246 #define FSYNR0_WNR (1 << 4)
248 static int force_stage;
249 module_param_named(force_stage, force_stage, int, S_IRUGO);
250 MODULE_PARM_DESC(force_stage,
251 "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
253 enum arm_smmu_arch_version {
258 struct arm_smmu_smr {
264 struct arm_smmu_master_cfg {
266 u16 streamids[MAX_MASTER_STREAMIDS];
267 struct arm_smmu_smr *smrs;
270 struct arm_smmu_master {
271 struct device_node *of_node;
273 struct arm_smmu_master_cfg cfg;
276 struct arm_smmu_device {
281 unsigned long pgshift;
283 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
284 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
285 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
286 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
287 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
288 #define ARM_SMMU_FEAT_TRANS_OPS (1 << 5)
291 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
293 enum arm_smmu_arch_version version;
295 u32 num_context_banks;
296 u32 num_s2_context_banks;
297 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
300 u32 num_mapping_groups;
301 DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
303 unsigned long va_size;
304 unsigned long ipa_size;
305 unsigned long pa_size;
308 u32 num_context_irqs;
311 struct list_head list;
312 struct rb_root masters;
315 struct arm_smmu_cfg {
320 #define INVALID_IRPTNDX 0xff
322 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
323 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
325 enum arm_smmu_domain_stage {
326 ARM_SMMU_DOMAIN_S1 = 0,
328 ARM_SMMU_DOMAIN_NESTED,
331 struct arm_smmu_domain {
332 struct arm_smmu_device *smmu;
333 struct io_pgtable_ops *pgtbl_ops;
334 spinlock_t pgtbl_lock;
335 struct arm_smmu_cfg cfg;
336 enum arm_smmu_domain_stage stage;
337 struct mutex init_mutex; /* Protects smmu pointer */
338 struct iommu_domain domain;
341 static struct iommu_ops arm_smmu_ops;
343 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
344 static LIST_HEAD(arm_smmu_devices);
346 struct arm_smmu_option_prop {
351 static struct arm_smmu_option_prop arm_smmu_options[] = {
352 { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
356 static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
358 return container_of(dom, struct arm_smmu_domain, domain);
361 static void parse_driver_options(struct arm_smmu_device *smmu)
366 if (of_property_read_bool(smmu->dev->of_node,
367 arm_smmu_options[i].prop)) {
368 smmu->options |= arm_smmu_options[i].opt;
369 dev_notice(smmu->dev, "option %s\n",
370 arm_smmu_options[i].prop);
372 } while (arm_smmu_options[++i].opt);
375 static struct device_node *dev_get_dev_node(struct device *dev)
377 if (dev_is_pci(dev)) {
378 struct pci_bus *bus = to_pci_dev(dev)->bus;
380 while (!pci_is_root_bus(bus))
382 return bus->bridge->parent->of_node;
388 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
389 struct device_node *dev_node)
391 struct rb_node *node = smmu->masters.rb_node;
394 struct arm_smmu_master *master;
396 master = container_of(node, struct arm_smmu_master, node);
398 if (dev_node < master->of_node)
399 node = node->rb_left;
400 else if (dev_node > master->of_node)
401 node = node->rb_right;
409 static struct arm_smmu_master_cfg *
410 find_smmu_master_cfg(struct device *dev)
412 struct arm_smmu_master_cfg *cfg = NULL;
413 struct iommu_group *group = iommu_group_get(dev);
416 cfg = iommu_group_get_iommudata(group);
417 iommu_group_put(group);
423 static int insert_smmu_master(struct arm_smmu_device *smmu,
424 struct arm_smmu_master *master)
426 struct rb_node **new, *parent;
428 new = &smmu->masters.rb_node;
431 struct arm_smmu_master *this
432 = container_of(*new, struct arm_smmu_master, node);
435 if (master->of_node < this->of_node)
436 new = &((*new)->rb_left);
437 else if (master->of_node > this->of_node)
438 new = &((*new)->rb_right);
443 rb_link_node(&master->node, parent, new);
444 rb_insert_color(&master->node, &smmu->masters);
448 static int register_smmu_master(struct arm_smmu_device *smmu,
450 struct of_phandle_args *masterspec)
453 struct arm_smmu_master *master;
455 master = find_smmu_master(smmu, masterspec->np);
458 "rejecting multiple registrations for master device %s\n",
459 masterspec->np->name);
463 if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
465 "reached maximum number (%d) of stream IDs for master device %s\n",
466 MAX_MASTER_STREAMIDS, masterspec->np->name);
470 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
474 master->of_node = masterspec->np;
475 master->cfg.num_streamids = masterspec->args_count;
477 for (i = 0; i < master->cfg.num_streamids; ++i) {
478 u16 streamid = masterspec->args[i];
480 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
481 (streamid >= smmu->num_mapping_groups)) {
483 "stream ID for master device %s greater than maximum allowed (%d)\n",
484 masterspec->np->name, smmu->num_mapping_groups);
487 master->cfg.streamids[i] = streamid;
489 return insert_smmu_master(smmu, master);
492 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
494 struct arm_smmu_device *smmu;
495 struct arm_smmu_master *master = NULL;
496 struct device_node *dev_node = dev_get_dev_node(dev);
498 spin_lock(&arm_smmu_devices_lock);
499 list_for_each_entry(smmu, &arm_smmu_devices, list) {
500 master = find_smmu_master(smmu, dev_node);
504 spin_unlock(&arm_smmu_devices_lock);
506 return master ? smmu : NULL;
509 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
514 idx = find_next_zero_bit(map, end, start);
517 } while (test_and_set_bit(idx, map));
522 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
527 /* Wait for any pending TLB invalidations to complete */
528 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
531 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
533 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
534 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
535 & sTLBGSTATUS_GSACTIVE) {
537 if (++count == TLB_LOOP_TIMEOUT) {
538 dev_err_ratelimited(smmu->dev,
539 "TLB sync timed out -- SMMU may be deadlocked\n");
546 static void arm_smmu_tlb_sync(void *cookie)
548 struct arm_smmu_domain *smmu_domain = cookie;
549 __arm_smmu_tlb_sync(smmu_domain->smmu);
552 static void arm_smmu_tlb_inv_context(void *cookie)
554 struct arm_smmu_domain *smmu_domain = cookie;
555 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
556 struct arm_smmu_device *smmu = smmu_domain->smmu;
557 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
561 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
562 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
563 base + ARM_SMMU_CB_S1_TLBIASID);
565 base = ARM_SMMU_GR0(smmu);
566 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
567 base + ARM_SMMU_GR0_TLBIVMID);
570 __arm_smmu_tlb_sync(smmu);
573 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
574 bool leaf, void *cookie)
576 struct arm_smmu_domain *smmu_domain = cookie;
577 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
578 struct arm_smmu_device *smmu = smmu_domain->smmu;
579 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
583 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
584 reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
586 if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
588 iova |= ARM_SMMU_CB_ASID(cfg);
589 writel_relaxed(iova, reg);
593 iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
594 writeq_relaxed(iova, reg);
598 } else if (smmu->version == ARM_SMMU_V2) {
599 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
600 reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
601 ARM_SMMU_CB_S2_TLBIIPAS2;
602 writeq_relaxed(iova >> 12, reg);
605 reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
606 writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);
610 static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie)
612 struct arm_smmu_domain *smmu_domain = cookie;
613 struct arm_smmu_device *smmu = smmu_domain->smmu;
614 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
617 /* Ensure new page tables are visible to the hardware walker */
618 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
622 * If the SMMU can't walk tables in the CPU caches, treat them
623 * like non-coherent DMA since we need to flush the new entries
624 * all the way out to memory. There's no possibility of
625 * recursion here as the SMMU table walker will not be wired
626 * through another SMMU.
628 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
633 static struct iommu_gather_ops arm_smmu_gather_ops = {
634 .tlb_flush_all = arm_smmu_tlb_inv_context,
635 .tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
636 .tlb_sync = arm_smmu_tlb_sync,
637 .flush_pgtable = arm_smmu_flush_pgtable,
640 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
643 u32 fsr, far, fsynr, resume;
645 struct iommu_domain *domain = dev;
646 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
647 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
648 struct arm_smmu_device *smmu = smmu_domain->smmu;
649 void __iomem *cb_base;
651 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
652 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
654 if (!(fsr & FSR_FAULT))
658 dev_err_ratelimited(smmu->dev,
659 "Unexpected context fault (fsr 0x%x)\n",
662 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
663 flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
665 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
668 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
669 iova |= ((unsigned long)far << 32);
672 if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
674 resume = RESUME_RETRY;
676 dev_err_ratelimited(smmu->dev,
677 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
678 iova, fsynr, cfg->cbndx);
680 resume = RESUME_TERMINATE;
683 /* Clear the faulting FSR */
684 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
686 /* Retry or terminate any stalled transactions */
688 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
693 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
695 u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
696 struct arm_smmu_device *smmu = dev;
697 void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
699 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
700 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
701 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
702 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
707 dev_err_ratelimited(smmu->dev,
708 "Unexpected global fault, this could be serious\n");
709 dev_err_ratelimited(smmu->dev,
710 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
711 gfsr, gfsynr0, gfsynr1, gfsynr2);
713 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
717 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
718 struct io_pgtable_cfg *pgtbl_cfg)
722 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
723 struct arm_smmu_device *smmu = smmu_domain->smmu;
724 void __iomem *cb_base, *gr0_base, *gr1_base;
726 gr0_base = ARM_SMMU_GR0(smmu);
727 gr1_base = ARM_SMMU_GR1(smmu);
728 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
729 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
731 if (smmu->version > ARM_SMMU_V1) {
734 * *Must* be initialised before CBAR thanks to VMID16
735 * architectural oversight affected some implementations.
738 reg = CBA2R_RW64_64BIT;
740 reg = CBA2R_RW64_32BIT;
742 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
747 if (smmu->version == ARM_SMMU_V1)
748 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
751 * Use the weakest shareability/memory types, so they are
752 * overridden by the ttbcr/pte.
755 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
756 (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
758 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
760 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
764 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
765 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
766 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0] >> 32;
767 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
768 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
770 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
771 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_LO);
772 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1] >> 32;
773 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
774 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_HI);
776 reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
777 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
778 reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr >> 32;
779 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
784 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
785 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
786 if (smmu->version > ARM_SMMU_V1) {
787 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
788 reg |= TTBCR2_SEP_UPSTREAM;
789 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
792 reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
793 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
796 /* MAIRs (stage-1 only) */
798 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
799 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
800 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
801 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);
805 reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
807 reg |= SCTLR_S1_ASIDPNE;
811 writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
814 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
815 struct arm_smmu_device *smmu)
817 int irq, start, ret = 0;
818 unsigned long ias, oas;
819 struct io_pgtable_ops *pgtbl_ops;
820 struct io_pgtable_cfg pgtbl_cfg;
821 enum io_pgtable_fmt fmt;
822 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
823 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
825 mutex_lock(&smmu_domain->init_mutex);
826 if (smmu_domain->smmu)
830 * Mapping the requested stage onto what we support is surprisingly
831 * complicated, mainly because the spec allows S1+S2 SMMUs without
832 * support for nested translation. That means we end up with the
835 * Requested Supported Actual
845 * Note that you can't actually request stage-2 mappings.
847 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
848 smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
849 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
850 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
852 switch (smmu_domain->stage) {
853 case ARM_SMMU_DOMAIN_S1:
854 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
855 start = smmu->num_s2_context_banks;
857 oas = smmu->ipa_size;
858 if (IS_ENABLED(CONFIG_64BIT))
859 fmt = ARM_64_LPAE_S1;
861 fmt = ARM_32_LPAE_S1;
863 case ARM_SMMU_DOMAIN_NESTED:
865 * We will likely want to change this if/when KVM gets
868 case ARM_SMMU_DOMAIN_S2:
869 cfg->cbar = CBAR_TYPE_S2_TRANS;
871 ias = smmu->ipa_size;
873 if (IS_ENABLED(CONFIG_64BIT))
874 fmt = ARM_64_LPAE_S2;
876 fmt = ARM_32_LPAE_S2;
883 ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
884 smmu->num_context_banks);
885 if (IS_ERR_VALUE(ret))
889 if (smmu->version == ARM_SMMU_V1) {
890 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
891 cfg->irptndx %= smmu->num_context_irqs;
893 cfg->irptndx = cfg->cbndx;
896 pgtbl_cfg = (struct io_pgtable_cfg) {
897 .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap,
900 .tlb = &arm_smmu_gather_ops,
903 smmu_domain->smmu = smmu;
904 pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
910 /* Update our support page sizes to reflect the page table format */
911 arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
913 /* Initialise the context bank with our page table cfg */
914 arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg);
917 * Request context fault interrupt. Do this last to avoid the
918 * handler seeing a half-initialised domain state.
920 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
921 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
922 "arm-smmu-context-fault", domain);
923 if (IS_ERR_VALUE(ret)) {
924 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
926 cfg->irptndx = INVALID_IRPTNDX;
929 mutex_unlock(&smmu_domain->init_mutex);
931 /* Publish page table ops for map/unmap */
932 smmu_domain->pgtbl_ops = pgtbl_ops;
936 smmu_domain->smmu = NULL;
938 mutex_unlock(&smmu_domain->init_mutex);
942 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
944 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
945 struct arm_smmu_device *smmu = smmu_domain->smmu;
946 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
947 void __iomem *cb_base;
954 * Disable the context bank and free the page tables before freeing
957 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
958 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
960 if (cfg->irptndx != INVALID_IRPTNDX) {
961 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
962 free_irq(irq, domain);
965 if (smmu_domain->pgtbl_ops)
966 free_io_pgtable_ops(smmu_domain->pgtbl_ops);
968 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
971 static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
973 struct arm_smmu_domain *smmu_domain;
975 if (type != IOMMU_DOMAIN_UNMANAGED)
978 * Allocate the domain and initialise some of its data structures.
979 * We can't really do anything meaningful until we've added a
982 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
986 mutex_init(&smmu_domain->init_mutex);
987 spin_lock_init(&smmu_domain->pgtbl_lock);
989 return &smmu_domain->domain;
992 static void arm_smmu_domain_free(struct iommu_domain *domain)
994 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
997 * Free the domain resources. We assume that all devices have
998 * already been detached.
1000 arm_smmu_destroy_domain_context(domain);
1004 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1005 struct arm_smmu_master_cfg *cfg)
1008 struct arm_smmu_smr *smrs;
1009 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1011 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1017 smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1019 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1020 cfg->num_streamids);
1024 /* Allocate the SMRs on the SMMU */
1025 for (i = 0; i < cfg->num_streamids; ++i) {
1026 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1027 smmu->num_mapping_groups);
1028 if (IS_ERR_VALUE(idx)) {
1029 dev_err(smmu->dev, "failed to allocate free SMR\n");
1033 smrs[i] = (struct arm_smmu_smr) {
1035 .mask = 0, /* We don't currently share SMRs */
1036 .id = cfg->streamids[i],
1040 /* It worked! Now, poke the actual hardware */
1041 for (i = 0; i < cfg->num_streamids; ++i) {
1042 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1043 smrs[i].mask << SMR_MASK_SHIFT;
1044 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1052 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1057 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1058 struct arm_smmu_master_cfg *cfg)
1061 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1062 struct arm_smmu_smr *smrs = cfg->smrs;
1067 /* Invalidate the SMRs before freeing back to the allocator */
1068 for (i = 0; i < cfg->num_streamids; ++i) {
1069 u8 idx = smrs[i].idx;
1071 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1072 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1079 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1080 struct arm_smmu_master_cfg *cfg)
1083 struct arm_smmu_device *smmu = smmu_domain->smmu;
1084 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1086 /* Devices in an IOMMU group may already be configured */
1087 ret = arm_smmu_master_configure_smrs(smmu, cfg);
1089 return ret == -EEXIST ? 0 : ret;
1091 for (i = 0; i < cfg->num_streamids; ++i) {
1094 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1095 s2cr = S2CR_TYPE_TRANS |
1096 (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1097 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1103 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1104 struct arm_smmu_master_cfg *cfg)
1107 struct arm_smmu_device *smmu = smmu_domain->smmu;
1108 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1110 /* An IOMMU group is torn down by the first device to be removed */
1111 if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)
1115 * We *must* clear the S2CR first, because freeing the SMR means
1116 * that it can be re-allocated immediately.
1118 for (i = 0; i < cfg->num_streamids; ++i) {
1119 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1121 writel_relaxed(S2CR_TYPE_BYPASS,
1122 gr0_base + ARM_SMMU_GR0_S2CR(idx));
1125 arm_smmu_master_free_smrs(smmu, cfg);
1128 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1131 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1132 struct arm_smmu_device *smmu;
1133 struct arm_smmu_master_cfg *cfg;
1135 smmu = find_smmu_for_device(dev);
1137 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1141 if (dev->archdata.iommu) {
1142 dev_err(dev, "already attached to IOMMU domain\n");
1146 /* Ensure that the domain is finalised */
1147 ret = arm_smmu_init_domain_context(domain, smmu);
1148 if (IS_ERR_VALUE(ret))
1152 * Sanity check the domain. We don't support domains across
1155 if (smmu_domain->smmu != smmu) {
1157 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1158 dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1162 /* Looks ok, so add the device to the domain */
1163 cfg = find_smmu_master_cfg(dev);
1167 ret = arm_smmu_domain_add_master(smmu_domain, cfg);
1169 dev->archdata.iommu = domain;
1173 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1175 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1176 struct arm_smmu_master_cfg *cfg;
1178 cfg = find_smmu_master_cfg(dev);
1182 dev->archdata.iommu = NULL;
1183 arm_smmu_domain_remove_master(smmu_domain, cfg);
1186 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1187 phys_addr_t paddr, size_t size, int prot)
1190 unsigned long flags;
1191 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1192 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1197 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1198 ret = ops->map(ops, iova, paddr, size, prot);
1199 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1203 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1207 unsigned long flags;
1208 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1209 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1214 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1215 ret = ops->unmap(ops, iova, size);
1216 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1220 static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
1223 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1224 struct arm_smmu_device *smmu = smmu_domain->smmu;
1225 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1226 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1227 struct device *dev = smmu->dev;
1228 void __iomem *cb_base;
1233 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
1235 /* ATS1 registers can only be written atomically */
1236 va = iova & ~0xfffUL;
1238 if (smmu->version == ARM_SMMU_V2)
1239 writeq_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);
1242 writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);
1244 if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,
1245 !(tmp & ATSR_ACTIVE), 5, 50)) {
1247 "iova to phys timed out on 0x%pad. Falling back to software table walk.\n",
1249 return ops->iova_to_phys(ops, iova);
1252 phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO);
1253 phys |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32;
1255 if (phys & CB_PAR_F) {
1256 dev_err(dev, "translation fault!\n");
1257 dev_err(dev, "PAR = 0x%llx\n", phys);
1261 return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff);
1264 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1268 unsigned long flags;
1269 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1270 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1275 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1276 if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS &&
1277 smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1278 ret = arm_smmu_iova_to_phys_hard(domain, iova);
1280 ret = ops->iova_to_phys(ops, iova);
1283 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1288 static bool arm_smmu_capable(enum iommu_cap cap)
1291 case IOMMU_CAP_CACHE_COHERENCY:
1293 * Return true here as the SMMU can always send out coherent
1297 case IOMMU_CAP_INTR_REMAP:
1298 return true; /* MSIs are just memory writes */
1299 case IOMMU_CAP_NOEXEC:
1306 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1308 *((u16 *)data) = alias;
1309 return 0; /* Continue walking */
1312 static void __arm_smmu_release_pci_iommudata(void *data)
1317 static int arm_smmu_add_pci_device(struct pci_dev *pdev)
1321 struct iommu_group *group;
1322 struct arm_smmu_master_cfg *cfg;
1324 group = iommu_group_get_for_dev(&pdev->dev);
1326 return PTR_ERR(group);
1328 cfg = iommu_group_get_iommudata(group);
1330 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1336 iommu_group_set_iommudata(group, cfg,
1337 __arm_smmu_release_pci_iommudata);
1340 if (cfg->num_streamids >= MAX_MASTER_STREAMIDS) {
1346 * Assume Stream ID == Requester ID for now.
1347 * We need a way to describe the ID mappings in FDT.
1349 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid);
1350 for (i = 0; i < cfg->num_streamids; ++i)
1351 if (cfg->streamids[i] == sid)
1354 /* Avoid duplicate SIDs, as this can lead to SMR conflicts */
1355 if (i == cfg->num_streamids)
1356 cfg->streamids[cfg->num_streamids++] = sid;
1360 iommu_group_put(group);
1364 static int arm_smmu_add_platform_device(struct device *dev)
1366 struct iommu_group *group;
1367 struct arm_smmu_master *master;
1368 struct arm_smmu_device *smmu = find_smmu_for_device(dev);
1373 master = find_smmu_master(smmu, dev->of_node);
1377 /* No automatic group creation for platform devices */
1378 group = iommu_group_alloc();
1380 return PTR_ERR(group);
1382 iommu_group_set_iommudata(group, &master->cfg, NULL);
1383 return iommu_group_add_device(group, dev);
1386 static int arm_smmu_add_device(struct device *dev)
1388 if (dev_is_pci(dev))
1389 return arm_smmu_add_pci_device(to_pci_dev(dev));
1391 return arm_smmu_add_platform_device(dev);
1394 static void arm_smmu_remove_device(struct device *dev)
1396 iommu_group_remove_device(dev);
1399 static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
1400 enum iommu_attr attr, void *data)
1402 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1405 case DOMAIN_ATTR_NESTING:
1406 *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
1413 static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
1414 enum iommu_attr attr, void *data)
1417 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1419 mutex_lock(&smmu_domain->init_mutex);
1422 case DOMAIN_ATTR_NESTING:
1423 if (smmu_domain->smmu) {
1429 smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
1431 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1439 mutex_unlock(&smmu_domain->init_mutex);
1443 static struct iommu_ops arm_smmu_ops = {
1444 .capable = arm_smmu_capable,
1445 .domain_alloc = arm_smmu_domain_alloc,
1446 .domain_free = arm_smmu_domain_free,
1447 .attach_dev = arm_smmu_attach_dev,
1448 .detach_dev = arm_smmu_detach_dev,
1449 .map = arm_smmu_map,
1450 .unmap = arm_smmu_unmap,
1451 .map_sg = default_iommu_map_sg,
1452 .iova_to_phys = arm_smmu_iova_to_phys,
1453 .add_device = arm_smmu_add_device,
1454 .remove_device = arm_smmu_remove_device,
1455 .domain_get_attr = arm_smmu_domain_get_attr,
1456 .domain_set_attr = arm_smmu_domain_set_attr,
1457 .pgsize_bitmap = -1UL, /* Restricted during device attach */
1460 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1462 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1463 void __iomem *cb_base;
1467 /* clear global FSR */
1468 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1469 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1471 /* Mark all SMRn as invalid and all S2CRn as bypass */
1472 for (i = 0; i < smmu->num_mapping_groups; ++i) {
1473 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
1474 writel_relaxed(S2CR_TYPE_BYPASS,
1475 gr0_base + ARM_SMMU_GR0_S2CR(i));
1478 /* Make sure all context banks are disabled and clear CB_FSR */
1479 for (i = 0; i < smmu->num_context_banks; ++i) {
1480 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1481 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1482 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1485 /* Invalidate the TLB, just in case */
1486 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1487 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1489 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1491 /* Enable fault reporting */
1492 reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1494 /* Disable TLB broadcasting. */
1495 reg |= (sCR0_VMIDPNE | sCR0_PTM);
1497 /* Enable client access, but bypass when no mapping is found */
1498 reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1500 /* Disable forced broadcasting */
1503 /* Don't upgrade barriers */
1504 reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1506 /* Push the button */
1507 __arm_smmu_tlb_sync(smmu);
1508 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1511 static int arm_smmu_id_size_to_bits(int size)
1530 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1533 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1536 dev_notice(smmu->dev, "probing hardware configuration...\n");
1537 dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1540 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1542 /* Restrict available stages based on module parameter */
1543 if (force_stage == 1)
1544 id &= ~(ID0_S2TS | ID0_NTS);
1545 else if (force_stage == 2)
1546 id &= ~(ID0_S1TS | ID0_NTS);
1548 if (id & ID0_S1TS) {
1549 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1550 dev_notice(smmu->dev, "\tstage 1 translation\n");
1553 if (id & ID0_S2TS) {
1554 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1555 dev_notice(smmu->dev, "\tstage 2 translation\n");
1559 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1560 dev_notice(smmu->dev, "\tnested translation\n");
1563 if (!(smmu->features &
1564 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
1565 dev_err(smmu->dev, "\tno translation support!\n");
1569 if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) {
1570 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
1571 dev_notice(smmu->dev, "\taddress translation ops\n");
1574 if (id & ID0_CTTW) {
1575 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1576 dev_notice(smmu->dev, "\tcoherent table walk\n");
1582 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1583 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1585 if (smmu->num_mapping_groups == 0) {
1587 "stream-matching supported, but no SMRs present!\n");
1591 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1592 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1593 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1594 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1596 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1597 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1598 if ((mask & sid) != sid) {
1600 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1605 dev_notice(smmu->dev,
1606 "\tstream matching with %u register groups, mask 0x%x",
1607 smmu->num_mapping_groups, mask);
1609 smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
1614 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1615 smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
1617 /* Check for size mismatch of SMMU address space from mapped region */
1618 size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1619 size *= 2 << smmu->pgshift;
1620 if (smmu->size != size)
1622 "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1625 smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK;
1626 smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1627 if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1628 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1631 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1632 smmu->num_context_banks, smmu->num_s2_context_banks);
1635 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1636 size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1637 smmu->ipa_size = size;
1639 /* The output mask is also applied for bypass */
1640 size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1641 smmu->pa_size = size;
1644 * What the page table walker can address actually depends on which
1645 * descriptor format is in use, but since a) we don't know that yet,
1646 * and b) it can vary per context bank, this will have to do...
1648 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size)))
1650 "failed to set DMA mask for table walker\n");
1652 if (smmu->version == ARM_SMMU_V1) {
1653 smmu->va_size = smmu->ipa_size;
1654 size = SZ_4K | SZ_2M | SZ_1G;
1656 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1657 smmu->va_size = arm_smmu_id_size_to_bits(size);
1658 #ifndef CONFIG_64BIT
1659 smmu->va_size = min(32UL, smmu->va_size);
1662 if (id & ID2_PTFS_4K)
1663 size |= SZ_4K | SZ_2M | SZ_1G;
1664 if (id & ID2_PTFS_16K)
1665 size |= SZ_16K | SZ_32M;
1666 if (id & ID2_PTFS_64K)
1667 size |= SZ_64K | SZ_512M;
1670 arm_smmu_ops.pgsize_bitmap &= size;
1671 dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size);
1673 if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
1674 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1675 smmu->va_size, smmu->ipa_size);
1677 if (smmu->features & ARM_SMMU_FEAT_TRANS_S2)
1678 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1679 smmu->ipa_size, smmu->pa_size);
1684 static const struct of_device_id arm_smmu_of_match[] = {
1685 { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 },
1686 { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 },
1687 { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
1688 { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
1689 { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
1692 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1694 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1696 const struct of_device_id *of_id;
1697 struct resource *res;
1698 struct arm_smmu_device *smmu;
1699 struct device *dev = &pdev->dev;
1700 struct rb_node *node;
1701 struct of_phandle_args masterspec;
1702 int num_irqs, i, err;
1704 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1706 dev_err(dev, "failed to allocate arm_smmu_device\n");
1711 of_id = of_match_node(arm_smmu_of_match, dev->of_node);
1712 smmu->version = (enum arm_smmu_arch_version)of_id->data;
1714 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1715 smmu->base = devm_ioremap_resource(dev, res);
1716 if (IS_ERR(smmu->base))
1717 return PTR_ERR(smmu->base);
1718 smmu->size = resource_size(res);
1720 if (of_property_read_u32(dev->of_node, "#global-interrupts",
1721 &smmu->num_global_irqs)) {
1722 dev_err(dev, "missing #global-interrupts property\n");
1727 while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1729 if (num_irqs > smmu->num_global_irqs)
1730 smmu->num_context_irqs++;
1733 if (!smmu->num_context_irqs) {
1734 dev_err(dev, "found %d interrupts but expected at least %d\n",
1735 num_irqs, smmu->num_global_irqs + 1);
1739 smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1742 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1746 for (i = 0; i < num_irqs; ++i) {
1747 int irq = platform_get_irq(pdev, i);
1750 dev_err(dev, "failed to get irq index %d\n", i);
1753 smmu->irqs[i] = irq;
1756 err = arm_smmu_device_cfg_probe(smmu);
1761 smmu->masters = RB_ROOT;
1762 while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1763 "#stream-id-cells", i,
1765 err = register_smmu_master(smmu, dev, &masterspec);
1767 dev_err(dev, "failed to add master %s\n",
1768 masterspec.np->name);
1769 goto out_put_masters;
1774 dev_notice(dev, "registered %d master devices\n", i);
1776 parse_driver_options(smmu);
1778 if (smmu->version > ARM_SMMU_V1 &&
1779 smmu->num_context_banks != smmu->num_context_irqs) {
1781 "found only %d context interrupt(s) but %d required\n",
1782 smmu->num_context_irqs, smmu->num_context_banks);
1784 goto out_put_masters;
1787 for (i = 0; i < smmu->num_global_irqs; ++i) {
1788 err = request_irq(smmu->irqs[i],
1789 arm_smmu_global_fault,
1791 "arm-smmu global fault",
1794 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1800 INIT_LIST_HEAD(&smmu->list);
1801 spin_lock(&arm_smmu_devices_lock);
1802 list_add(&smmu->list, &arm_smmu_devices);
1803 spin_unlock(&arm_smmu_devices_lock);
1805 arm_smmu_device_reset(smmu);
1810 free_irq(smmu->irqs[i], smmu);
1813 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1814 struct arm_smmu_master *master
1815 = container_of(node, struct arm_smmu_master, node);
1816 of_node_put(master->of_node);
1822 static int arm_smmu_device_remove(struct platform_device *pdev)
1825 struct device *dev = &pdev->dev;
1826 struct arm_smmu_device *curr, *smmu = NULL;
1827 struct rb_node *node;
1829 spin_lock(&arm_smmu_devices_lock);
1830 list_for_each_entry(curr, &arm_smmu_devices, list) {
1831 if (curr->dev == dev) {
1833 list_del(&smmu->list);
1837 spin_unlock(&arm_smmu_devices_lock);
1842 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1843 struct arm_smmu_master *master
1844 = container_of(node, struct arm_smmu_master, node);
1845 of_node_put(master->of_node);
1848 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1849 dev_err(dev, "removing device with active domains!\n");
1851 for (i = 0; i < smmu->num_global_irqs; ++i)
1852 free_irq(smmu->irqs[i], smmu);
1854 /* Turn the thing off */
1855 writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1859 static struct platform_driver arm_smmu_driver = {
1862 .of_match_table = of_match_ptr(arm_smmu_of_match),
1864 .probe = arm_smmu_device_dt_probe,
1865 .remove = arm_smmu_device_remove,
1868 static int __init arm_smmu_init(void)
1870 struct device_node *np;
1874 * Play nice with systems that don't have an ARM SMMU by checking that
1875 * an ARM SMMU exists in the system before proceeding with the driver
1876 * and IOMMU bus operation registration.
1878 np = of_find_matching_node(NULL, arm_smmu_of_match);
1884 ret = platform_driver_register(&arm_smmu_driver);
1888 /* Oh, for a proper bus abstraction */
1889 if (!iommu_present(&platform_bus_type))
1890 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
1892 #ifdef CONFIG_ARM_AMBA
1893 if (!iommu_present(&amba_bustype))
1894 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
1898 if (!iommu_present(&pci_bus_type))
1899 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
1905 static void __exit arm_smmu_exit(void)
1907 return platform_driver_unregister(&arm_smmu_driver);
1910 subsys_initcall(arm_smmu_init);
1911 module_exit(arm_smmu_exit);
1913 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1914 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1915 MODULE_LICENSE("GPL v2");