drivers/iommu/arm-smmu.c

   1 /*
   2  * IOMMU API for ARM architected SMMU implementations.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16  *
  17  * Copyright (C) 2013 ARM Limited
  18  *
  19  * Author: Will Deacon <will.deacon@arm.com>
  20  *
  21  * This driver currently supports:
  22  *      - SMMUv1 and v2 implementations
  23  *      - Stream-matching and stream-indexing
  24  *      - v7/v8 long-descriptor format
  25  *      - Non-secure access to the SMMU
  26  *      - 4k and 64k pages, with contiguous pte hints.
  27  *      - Up to 42-bit addressing (dependent on VA_BITS)
  28  *      - Context fault reporting
  29  */
  30
  31 #define pr_fmt(fmt) "arm-smmu: " fmt
  32
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/err.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/io.h>
  38 #include <linux/iommu.h>
  39 #include <linux/mm.h>
  40 #include <linux/module.h>
  41 #include <linux/of.h>
  42 #include <linux/pci.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/slab.h>
  45 #include <linux/spinlock.h>
  46
  47 #include <linux/amba/bus.h>
  48
  49 #include <asm/pgalloc.h>
  50
  51 /* Maximum number of stream IDs assigned to a single device */
  52 #define MAX_MASTER_STREAMIDS            MAX_PHANDLE_ARGS
  53
  54 /* Maximum number of context banks per SMMU */
  55 #define ARM_SMMU_MAX_CBS                128
  56
  57 /* Maximum number of mapping groups per SMMU */
  58 #define ARM_SMMU_MAX_SMRS               128
  59
  60 /* SMMU global address space */
  61 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
  62 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (smmu)->pagesize)
  63
  64 /*
  65  * SMMU global address space with conditional offset to access secure
  66  * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
  67  * nsGFSYNR0: 0x450)
  68  */
  69 #define ARM_SMMU_GR0_NS(smmu)                                           \
  70         ((smmu)->base +                                                 \
  71                 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)       \
  72                         ? 0x400 : 0))
  73
  74 /* Page table bits */
  75 #define ARM_SMMU_PTE_XN                 (((pteval_t)3) << 53)
  76 #define ARM_SMMU_PTE_CONT               (((pteval_t)1) << 52)
  77 #define ARM_SMMU_PTE_AF                 (((pteval_t)1) << 10)
  78 #define ARM_SMMU_PTE_SH_NS              (((pteval_t)0) << 8)
  79 #define ARM_SMMU_PTE_SH_OS              (((pteval_t)2) << 8)
  80 #define ARM_SMMU_PTE_SH_IS              (((pteval_t)3) << 8)
  81 #define ARM_SMMU_PTE_PAGE               (((pteval_t)3) << 0)
  82
  83 #if PAGE_SIZE == SZ_4K
  84 #define ARM_SMMU_PTE_CONT_ENTRIES       16
  85 #elif PAGE_SIZE == SZ_64K
  86 #define ARM_SMMU_PTE_CONT_ENTRIES       32
  87 #else
  88 #define ARM_SMMU_PTE_CONT_ENTRIES       1
  89 #endif
  90
  91 #define ARM_SMMU_PTE_CONT_SIZE          (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
  92 #define ARM_SMMU_PTE_CONT_MASK          (~(ARM_SMMU_PTE_CONT_SIZE - 1))
  93
  94 /* Stage-1 PTE */
  95 #define ARM_SMMU_PTE_AP_UNPRIV          (((pteval_t)1) << 6)
  96 #define ARM_SMMU_PTE_AP_RDONLY          (((pteval_t)2) << 6)
  97 #define ARM_SMMU_PTE_ATTRINDX_SHIFT     2
  98 #define ARM_SMMU_PTE_nG                 (((pteval_t)1) << 11)
  99
 100 /* Stage-2 PTE */
 101 #define ARM_SMMU_PTE_HAP_FAULT          (((pteval_t)0) << 6)
 102 #define ARM_SMMU_PTE_HAP_READ           (((pteval_t)1) << 6)
 103 #define ARM_SMMU_PTE_HAP_WRITE          (((pteval_t)2) << 6)
 104 #define ARM_SMMU_PTE_MEMATTR_OIWB       (((pteval_t)0xf) << 2)
 105 #define ARM_SMMU_PTE_MEMATTR_NC         (((pteval_t)0x5) << 2)
 106 #define ARM_SMMU_PTE_MEMATTR_DEV        (((pteval_t)0x1) << 2)
 107
 108 /* Configuration registers */
 109 #define ARM_SMMU_GR0_sCR0               0x0
 110 #define sCR0_CLIENTPD                   (1 << 0)
 111 #define sCR0_GFRE                       (1 << 1)
 112 #define sCR0_GFIE                       (1 << 2)
 113 #define sCR0_GCFGFRE                    (1 << 4)
 114 #define sCR0_GCFGFIE                    (1 << 5)
 115 #define sCR0_USFCFG                     (1 << 10)
 116 #define sCR0_VMIDPNE                    (1 << 11)
 117 #define sCR0_PTM                        (1 << 12)
 118 #define sCR0_FB                         (1 << 13)
 119 #define sCR0_BSU_SHIFT                  14
 120 #define sCR0_BSU_MASK                   0x3
 121
 122 /* Identification registers */
 123 #define ARM_SMMU_GR0_ID0                0x20
 124 #define ARM_SMMU_GR0_ID1                0x24
 125 #define ARM_SMMU_GR0_ID2                0x28
 126 #define ARM_SMMU_GR0_ID3                0x2c
 127 #define ARM_SMMU_GR0_ID4                0x30
 128 #define ARM_SMMU_GR0_ID5                0x34
 129 #define ARM_SMMU_GR0_ID6                0x38
 130 #define ARM_SMMU_GR0_ID7                0x3c
 131 #define ARM_SMMU_GR0_sGFSR              0x48
 132 #define ARM_SMMU_GR0_sGFSYNR0           0x50
 133 #define ARM_SMMU_GR0_sGFSYNR1           0x54
 134 #define ARM_SMMU_GR0_sGFSYNR2           0x58
 135 #define ARM_SMMU_GR0_PIDR0              0xfe0
 136 #define ARM_SMMU_GR0_PIDR1              0xfe4
 137 #define ARM_SMMU_GR0_PIDR2              0xfe8
 138
 139 #define ID0_S1TS                        (1 << 30)
 140 #define ID0_S2TS                        (1 << 29)
 141 #define ID0_NTS                         (1 << 28)
 142 #define ID0_SMS                         (1 << 27)
 143 #define ID0_PTFS_SHIFT                  24
 144 #define ID0_PTFS_MASK                   0x2
 145 #define ID0_PTFS_V8_ONLY                0x2
 146 #define ID0_CTTW                        (1 << 14)
 147 #define ID0_NUMIRPT_SHIFT               16
 148 #define ID0_NUMIRPT_MASK                0xff
 149 #define ID0_NUMSMRG_SHIFT               0
 150 #define ID0_NUMSMRG_MASK                0xff
 151
 152 #define ID1_PAGESIZE                    (1 << 31)
 153 #define ID1_NUMPAGENDXB_SHIFT           28
 154 #define ID1_NUMPAGENDXB_MASK            7
 155 #define ID1_NUMS2CB_SHIFT               16
 156 #define ID1_NUMS2CB_MASK                0xff
 157 #define ID1_NUMCB_SHIFT                 0
 158 #define ID1_NUMCB_MASK                  0xff
 159
 160 #define ID2_OAS_SHIFT                   4
 161 #define ID2_OAS_MASK                    0xf
 162 #define ID2_IAS_SHIFT                   0
 163 #define ID2_IAS_MASK                    0xf
 164 #define ID2_UBS_SHIFT                   8
 165 #define ID2_UBS_MASK                    0xf
 166 #define ID2_PTFS_4K                     (1 << 12)
 167 #define ID2_PTFS_16K                    (1 << 13)
 168 #define ID2_PTFS_64K                    (1 << 14)
 169
 170 #define PIDR2_ARCH_SHIFT                4
 171 #define PIDR2_ARCH_MASK                 0xf
 172
 173 /* Global TLB invalidation */
 174 #define ARM_SMMU_GR0_STLBIALL           0x60
 175 #define ARM_SMMU_GR0_TLBIVMID           0x64
 176 #define ARM_SMMU_GR0_TLBIALLNSNH        0x68
 177 #define ARM_SMMU_GR0_TLBIALLH           0x6c
 178 #define ARM_SMMU_GR0_sTLBGSYNC          0x70
 179 #define ARM_SMMU_GR0_sTLBGSTATUS        0x74
 180 #define sTLBGSTATUS_GSACTIVE            (1 << 0)
 181 #define TLB_LOOP_TIMEOUT                1000000 /* 1s! */
 182
 183 /* Stream mapping registers */
 184 #define ARM_SMMU_GR0_SMR(n)             (0x800 + ((n) << 2))
 185 #define SMR_VALID                       (1 << 31)
 186 #define SMR_MASK_SHIFT                  16
 187 #define SMR_MASK_MASK                   0x7fff
 188 #define SMR_ID_SHIFT                    0
 189 #define SMR_ID_MASK                     0x7fff
 190
 191 #define ARM_SMMU_GR0_S2CR(n)            (0xc00 + ((n) << 2))
 192 #define S2CR_CBNDX_SHIFT                0
 193 #define S2CR_CBNDX_MASK                 0xff
 194 #define S2CR_TYPE_SHIFT                 16
 195 #define S2CR_TYPE_MASK                  0x3
 196 #define S2CR_TYPE_TRANS                 (0 << S2CR_TYPE_SHIFT)
 197 #define S2CR_TYPE_BYPASS                (1 << S2CR_TYPE_SHIFT)
 198 #define S2CR_TYPE_FAULT                 (2 << S2CR_TYPE_SHIFT)
 199
 200 /* Context bank attribute registers */
 201 #define ARM_SMMU_GR1_CBAR(n)            (0x0 + ((n) << 2))
 202 #define CBAR_VMID_SHIFT                 0
 203 #define CBAR_VMID_MASK                  0xff
 204 #define CBAR_S1_BPSHCFG_SHIFT           8
 205 #define CBAR_S1_BPSHCFG_MASK            3
 206 #define CBAR_S1_BPSHCFG_NSH             3
 207 #define CBAR_S1_MEMATTR_SHIFT           12
 208 #define CBAR_S1_MEMATTR_MASK            0xf
 209 #define CBAR_S1_MEMATTR_WB              0xf
 210 #define CBAR_TYPE_SHIFT                 16
 211 #define CBAR_TYPE_MASK                  0x3
 212 #define CBAR_TYPE_S2_TRANS              (0 << CBAR_TYPE_SHIFT)
 213 #define CBAR_TYPE_S1_TRANS_S2_BYPASS    (1 << CBAR_TYPE_SHIFT)
 214 #define CBAR_TYPE_S1_TRANS_S2_FAULT     (2 << CBAR_TYPE_SHIFT)
 215 #define CBAR_TYPE_S1_TRANS_S2_TRANS     (3 << CBAR_TYPE_SHIFT)
 216 #define CBAR_IRPTNDX_SHIFT              24
 217 #define CBAR_IRPTNDX_MASK               0xff
 218
 219 #define ARM_SMMU_GR1_CBA2R(n)           (0x800 + ((n) << 2))
 220 #define CBA2R_RW64_32BIT                (0 << 0)
 221 #define CBA2R_RW64_64BIT                (1 << 0)
 222
 223 /* Translation context bank */
 224 #define ARM_SMMU_CB_BASE(smmu)          ((smmu)->base + ((smmu)->size >> 1))
 225 #define ARM_SMMU_CB(smmu, n)            ((n) * (smmu)->pagesize)
 226
 227 #define ARM_SMMU_CB_SCTLR               0x0
 228 #define ARM_SMMU_CB_RESUME              0x8
 229 #define ARM_SMMU_CB_TTBCR2              0x10
 230 #define ARM_SMMU_CB_TTBR0_LO            0x20
 231 #define ARM_SMMU_CB_TTBR0_HI            0x24
 232 #define ARM_SMMU_CB_TTBCR               0x30
 233 #define ARM_SMMU_CB_S1_MAIR0            0x38
 234 #define ARM_SMMU_CB_FSR                 0x58
 235 #define ARM_SMMU_CB_FAR_LO              0x60
 236 #define ARM_SMMU_CB_FAR_HI              0x64
 237 #define ARM_SMMU_CB_FSYNR0              0x68
 238 #define ARM_SMMU_CB_S1_TLBIASID         0x610
 239
 240 #define SCTLR_S1_ASIDPNE                (1 << 12)
 241 #define SCTLR_CFCFG                     (1 << 7)
 242 #define SCTLR_CFIE                      (1 << 6)
 243 #define SCTLR_CFRE                      (1 << 5)
 244 #define SCTLR_E                         (1 << 4)
 245 #define SCTLR_AFE                       (1 << 2)
 246 #define SCTLR_TRE                       (1 << 1)
 247 #define SCTLR_M                         (1 << 0)
 248 #define SCTLR_EAE_SBOP                  (SCTLR_AFE | SCTLR_TRE)
 249
 250 #define RESUME_RETRY                    (0 << 0)
 251 #define RESUME_TERMINATE                (1 << 0)
 252
 253 #define TTBCR_EAE                       (1 << 31)
 254
 255 #define TTBCR_PASIZE_SHIFT              16
 256 #define TTBCR_PASIZE_MASK               0x7
 257
 258 #define TTBCR_TG0_4K                    (0 << 14)
 259 #define TTBCR_TG0_64K                   (1 << 14)
 260
 261 #define TTBCR_SH0_SHIFT                 12
 262 #define TTBCR_SH0_MASK                  0x3
 263 #define TTBCR_SH_NS                     0
 264 #define TTBCR_SH_OS                     2
 265 #define TTBCR_SH_IS                     3
 266
 267 #define TTBCR_ORGN0_SHIFT               10
 268 #define TTBCR_IRGN0_SHIFT               8
 269 #define TTBCR_RGN_MASK                  0x3
 270 #define TTBCR_RGN_NC                    0
 271 #define TTBCR_RGN_WBWA                  1
 272 #define TTBCR_RGN_WT                    2
 273 #define TTBCR_RGN_WB                    3
 274
 275 #define TTBCR_SL0_SHIFT                 6
 276 #define TTBCR_SL0_MASK                  0x3
 277 #define TTBCR_SL0_LVL_2                 0
 278 #define TTBCR_SL0_LVL_1                 1
 279
 280 #define TTBCR_T1SZ_SHIFT                16
 281 #define TTBCR_T0SZ_SHIFT                0
 282 #define TTBCR_SZ_MASK                   0xf
 283
 284 #define TTBCR2_SEP_SHIFT                15
 285 #define TTBCR2_SEP_MASK                 0x7
 286
 287 #define TTBCR2_PASIZE_SHIFT             0
 288 #define TTBCR2_PASIZE_MASK              0x7
 289
 290 /* Common definitions for PASize and SEP fields */
 291 #define TTBCR2_ADDR_32                  0
 292 #define TTBCR2_ADDR_36                  1
 293 #define TTBCR2_ADDR_40                  2
 294 #define TTBCR2_ADDR_42                  3
 295 #define TTBCR2_ADDR_44                  4
 296 #define TTBCR2_ADDR_48                  5
 297
 298 #define TTBRn_HI_ASID_SHIFT             16
 299
 300 #define MAIR_ATTR_SHIFT(n)              ((n) << 3)
 301 #define MAIR_ATTR_MASK                  0xff
 302 #define MAIR_ATTR_DEVICE                0x04
 303 #define MAIR_ATTR_NC                    0x44
 304 #define MAIR_ATTR_WBRWA                 0xff
 305 #define MAIR_ATTR_IDX_NC                0
 306 #define MAIR_ATTR_IDX_CACHE             1
 307 #define MAIR_ATTR_IDX_DEV               2
 308
 309 #define FSR_MULTI                       (1 << 31)
 310 #define FSR_SS                          (1 << 30)
 311 #define FSR_UUT                         (1 << 8)
 312 #define FSR_ASF                         (1 << 7)
 313 #define FSR_TLBLKF                      (1 << 6)
 314 #define FSR_TLBMCF                      (1 << 5)
 315 #define FSR_EF                          (1 << 4)
 316 #define FSR_PF                          (1 << 3)
 317 #define FSR_AFF                         (1 << 2)
 318 #define FSR_TF                          (1 << 1)
 319
 320 #define FSR_IGN                         (FSR_AFF | FSR_ASF | \
 321                                          FSR_TLBMCF | FSR_TLBLKF)
 322 #define FSR_FAULT                       (FSR_MULTI | FSR_SS | FSR_UUT | \
 323                                          FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
 324
 325 #define FSYNR0_WNR                      (1 << 4)
 326
 327 struct arm_smmu_smr {
 328         u8                              idx;
 329         u16                             mask;
 330         u16                             id;
 331 };
 332
 333 struct arm_smmu_master_cfg {
 334         int                             num_streamids;
 335         u16                             streamids[MAX_MASTER_STREAMIDS];
 336         struct arm_smmu_smr             *smrs;
 337 };
 338
 339 struct arm_smmu_master {
 340         struct device_node              *of_node;
 341         struct rb_node                  node;
 342         struct arm_smmu_master_cfg      cfg;
 343 };
 344
 345 struct arm_smmu_device {
 346         struct device                   *dev;
 347
 348         void __iomem                    *base;
 349         unsigned long                   size;
 350         unsigned long                   pagesize;
 351
 352 #define ARM_SMMU_FEAT_COHERENT_WALK     (1 << 0)
 353 #define ARM_SMMU_FEAT_STREAM_MATCH      (1 << 1)
 354 #define ARM_SMMU_FEAT_TRANS_S1          (1 << 2)
 355 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
 356 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
 357         u32                             features;
 358
 359 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
 360         u32                             options;
 361         int                             version;
 362
 363         u32                             num_context_banks;
 364         u32                             num_s2_context_banks;
 365         DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
 366         atomic_t                        irptndx;
 367
 368         u32                             num_mapping_groups;
 369         DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
 370
 371         unsigned long                   input_size;
 372         unsigned long                   s1_output_size;
 373         unsigned long                   s2_output_size;
 374
 375         u32                             num_global_irqs;
 376         u32                             num_context_irqs;
 377         unsigned int                    *irqs;
 378
 379         struct list_head                list;
 380         struct rb_root                  masters;
 381 };
 382
 383 struct arm_smmu_cfg {
 384         u8                              cbndx;
 385         u8                              irptndx;
 386         u32                             cbar;
 387         pgd_t                           *pgd;
 388 };
 389 #define INVALID_IRPTNDX                 0xff
 390
 391 #define ARM_SMMU_CB_ASID(cfg)           ((cfg)->cbndx)
 392 #define ARM_SMMU_CB_VMID(cfg)           ((cfg)->cbndx + 1)
 393
 394 struct arm_smmu_domain {
 395         struct arm_smmu_device          *smmu;
 396         struct arm_smmu_cfg             cfg;
 397         spinlock_t                      lock;
 398 };
 399
 400 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
 401 static LIST_HEAD(arm_smmu_devices);
 402
 403 struct arm_smmu_option_prop {
 404         u32 opt;
 405         const char *prop;
 406 };
 407
 408 static struct arm_smmu_option_prop arm_smmu_options[] = {
 409         { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
 410         { 0, NULL},
 411 };
 412
 413 static void parse_driver_options(struct arm_smmu_device *smmu)
 414 {
 415         int i = 0;
 416
 417         do {
 418                 if (of_property_read_bool(smmu->dev->of_node,
 419                                                 arm_smmu_options[i].prop)) {
 420                         smmu->options |= arm_smmu_options[i].opt;
 421                         dev_notice(smmu->dev, "option %s\n",
 422                                 arm_smmu_options[i].prop);
 423                 }
 424         } while (arm_smmu_options[++i].opt);
 425 }
 426
 427 static struct device *dev_get_master_dev(struct device *dev)
 428 {
 429         if (dev_is_pci(dev)) {
 430                 struct pci_bus *bus = to_pci_dev(dev)->bus;
 431
 432                 while (!pci_is_root_bus(bus))
 433                         bus = bus->parent;
 434                 return bus->bridge->parent;
 435         }
 436
 437         return dev;
 438 }
 439
 440 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
 441                                                 struct device_node *dev_node)
 442 {
 443         struct rb_node *node = smmu->masters.rb_node;
 444
 445         while (node) {
 446                 struct arm_smmu_master *master;
 447
 448                 master = container_of(node, struct arm_smmu_master, node);
 449
 450                 if (dev_node < master->of_node)
 451                         node = node->rb_left;
 452                 else if (dev_node > master->of_node)
 453                         node = node->rb_right;
 454                 else
 455                         return master;
 456         }
 457
 458         return NULL;
 459 }
 460
 461 static struct arm_smmu_master_cfg *
 462 find_smmu_master_cfg(struct arm_smmu_device *smmu, struct device *dev)
 463 {
 464         struct arm_smmu_master *master;
 465
 466         if (dev_is_pci(dev))
 467                 return dev->archdata.iommu;
 468
 469         master = find_smmu_master(smmu, dev->of_node);
 470         return master ? &master->cfg : NULL;
 471 }
 472
 473 static int insert_smmu_master(struct arm_smmu_device *smmu,
 474                               struct arm_smmu_master *master)
 475 {
 476         struct rb_node **new, *parent;
 477
 478         new = &smmu->masters.rb_node;
 479         parent = NULL;
 480         while (*new) {
 481                 struct arm_smmu_master *this
 482                         = container_of(*new, struct arm_smmu_master, node);
 483
 484                 parent = *new;
 485                 if (master->of_node < this->of_node)
 486                         new = &((*new)->rb_left);
 487                 else if (master->of_node > this->of_node)
 488                         new = &((*new)->rb_right);
 489                 else
 490                         return -EEXIST;
 491         }
 492
 493         rb_link_node(&master->node, parent, new);
 494         rb_insert_color(&master->node, &smmu->masters);
 495         return 0;
 496 }
 497
 498 static int register_smmu_master(struct arm_smmu_device *smmu,
 499                                 struct device *dev,
 500                                 struct of_phandle_args *masterspec)
 501 {
 502         int i;
 503         struct arm_smmu_master *master;
 504
 505         master = find_smmu_master(smmu, masterspec->np);
 506         if (master) {
 507                 dev_err(dev,
 508                         "rejecting multiple registrations for master device %s\n",
 509                         masterspec->np->name);
 510                 return -EBUSY;
 511         }
 512
 513         if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
 514                 dev_err(dev,
 515                         "reached maximum number (%d) of stream IDs for master device %s\n",
 516                         MAX_MASTER_STREAMIDS, masterspec->np->name);
 517                 return -ENOSPC;
 518         }
 519
 520         master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
 521         if (!master)
 522                 return -ENOMEM;
 523
 524         master->of_node                 = masterspec->np;
 525         master->cfg.num_streamids       = masterspec->args_count;
 526
 527         for (i = 0; i < master->cfg.num_streamids; ++i)
 528                 master->cfg.streamids[i] = masterspec->args[i];
 529
 530         return insert_smmu_master(smmu, master);
 531 }
 532
 533 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
 534 {
 535         struct arm_smmu_device *smmu;
 536         struct arm_smmu_master *master = NULL;
 537         struct device_node *dev_node = dev_get_master_dev(dev)->of_node;
 538
 539         spin_lock(&arm_smmu_devices_lock);
 540         list_for_each_entry(smmu, &arm_smmu_devices, list) {
 541                 master = find_smmu_master(smmu, dev_node);
 542                 if (master)
 543                         break;
 544         }
 545         spin_unlock(&arm_smmu_devices_lock);
 546
 547         return master ? smmu : NULL;
 548 }
 549
 550 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
 551 {
 552         int idx;
 553
 554         do {
 555                 idx = find_next_zero_bit(map, end, start);
 556                 if (idx == end)
 557                         return -ENOSPC;
 558         } while (test_and_set_bit(idx, map));
 559
 560         return idx;
 561 }
 562
 563 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
 564 {
 565         clear_bit(idx, map);
 566 }
 567
 568 /* Wait for any pending TLB invalidations to complete */
 569 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
 570 {
 571         int count = 0;
 572         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 573
 574         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
 575         while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
 576                & sTLBGSTATUS_GSACTIVE) {
 577                 cpu_relax();
 578                 if (++count == TLB_LOOP_TIMEOUT) {
 579                         dev_err_ratelimited(smmu->dev,
 580                         "TLB sync timed out -- SMMU may be deadlocked\n");
 581                         return;
 582                 }
 583                 udelay(1);
 584         }
 585 }
 586
 587 static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain)
 588 {
 589         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 590         struct arm_smmu_device *smmu = smmu_domain->smmu;
 591         void __iomem *base = ARM_SMMU_GR0(smmu);
 592         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 593
 594         if (stage1) {
 595                 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 596                 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
 597                                base + ARM_SMMU_CB_S1_TLBIASID);
 598         } else {
 599                 base = ARM_SMMU_GR0(smmu);
 600                 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
 601                                base + ARM_SMMU_GR0_TLBIVMID);
 602         }
 603
 604         arm_smmu_tlb_sync(smmu);
 605 }
 606
 607 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 608 {
 609         int flags, ret;
 610         u32 fsr, far, fsynr, resume;
 611         unsigned long iova;
 612         struct iommu_domain *domain = dev;
 613         struct arm_smmu_domain *smmu_domain = domain->priv;
 614         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 615         struct arm_smmu_device *smmu = smmu_domain->smmu;
 616         void __iomem *cb_base;
 617
 618         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 619         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
 620
 621         if (!(fsr & FSR_FAULT))
 622                 return IRQ_NONE;
 623
 624         if (fsr & FSR_IGN)
 625                 dev_err_ratelimited(smmu->dev,
 626                                     "Unexpected context fault (fsr 0x%u)\n",
 627                                     fsr);
 628
 629         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
 630         flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
 631
 632         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
 633         iova = far;
 634 #ifdef CONFIG_64BIT
 635         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
 636         iova |= ((unsigned long)far << 32);
 637 #endif
 638
 639         if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
 640                 ret = IRQ_HANDLED;
 641                 resume = RESUME_RETRY;
 642         } else {
 643                 dev_err_ratelimited(smmu->dev,
 644                     "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
 645                     iova, fsynr, cfg->cbndx);
 646                 ret = IRQ_NONE;
 647                 resume = RESUME_TERMINATE;
 648         }
 649
 650         /* Clear the faulting FSR */
 651         writel(fsr, cb_base + ARM_SMMU_CB_FSR);
 652
 653         /* Retry or terminate any stalled transactions */
 654         if (fsr & FSR_SS)
 655                 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
 656
 657         return ret;
 658 }
 659
 660 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
 661 {
 662         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
 663         struct arm_smmu_device *smmu = dev;
 664         void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
 665
 666         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
 667         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
 668         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
 669         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
 670
 671         if (!gfsr)
 672                 return IRQ_NONE;
 673
 674         dev_err_ratelimited(smmu->dev,
 675                 "Unexpected global fault, this could be serious\n");
 676         dev_err_ratelimited(smmu->dev,
 677                 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
 678                 gfsr, gfsynr0, gfsynr1, gfsynr2);
 679
 680         writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
 681         return IRQ_HANDLED;
 682 }
 683
 684 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
 685                                    size_t size)
 686 {
 687         unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
 688
 689
 690         /* Ensure new page tables are visible to the hardware walker */
 691         if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
 692                 dsb(ishst);
 693         } else {
 694                 /*
 695                  * If the SMMU can't walk tables in the CPU caches, treat them
 696                  * like non-coherent DMA since we need to flush the new entries
 697                  * all the way out to memory. There's no possibility of
 698                  * recursion here as the SMMU table walker will not be wired
 699                  * through another SMMU.
 700                  */
 701                 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
 702                                 DMA_TO_DEVICE);
 703         }
 704 }
 705
 706 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 707 {
 708         u32 reg;
 709         bool stage1;
 710         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 711         struct arm_smmu_device *smmu = smmu_domain->smmu;
 712         void __iomem *cb_base, *gr0_base, *gr1_base;
 713
 714         gr0_base = ARM_SMMU_GR0(smmu);
 715         gr1_base = ARM_SMMU_GR1(smmu);
 716         stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 717         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 718
 719         /* CBAR */
 720         reg = cfg->cbar;
 721         if (smmu->version == 1)
 722                 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
 723
 724         /*
 725          * Use the weakest shareability/memory types, so they are
 726          * overridden by the ttbcr/pte.
 727          */
 728         if (stage1) {
 729                 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
 730                         (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 731         } else {
 732                 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
 733         }
 734         writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
 735
 736         if (smmu->version > 1) {
 737                 /* CBA2R */
 738 #ifdef CONFIG_64BIT
 739                 reg = CBA2R_RW64_64BIT;
 740 #else
 741                 reg = CBA2R_RW64_32BIT;
 742 #endif
 743                 writel_relaxed(reg,
 744                                gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
 745
 746                 /* TTBCR2 */
 747                 switch (smmu->input_size) {
 748                 case 32:
 749                         reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
 750                         break;
 751                 case 36:
 752                         reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
 753                         break;
 754                 case 39:
 755                         reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
 756                         break;
 757                 case 42:
 758                         reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
 759                         break;
 760                 case 44:
 761                         reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
 762                         break;
 763                 case 48:
 764                         reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
 765                         break;
 766                 }
 767
 768                 switch (smmu->s1_output_size) {
 769                 case 32:
 770                         reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
 771                         break;
 772                 case 36:
 773                         reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
 774                         break;
 775                 case 39:
 776                         reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
 777                         break;
 778                 case 42:
 779                         reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
 780                         break;
 781                 case 44:
 782                         reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
 783                         break;
 784                 case 48:
 785                         reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
 786                         break;
 787                 }
 788
 789                 if (stage1)
 790                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
 791         }
 792
 793         /* TTBR0 */
 794         arm_smmu_flush_pgtable(smmu, cfg->pgd,
 795                                PTRS_PER_PGD * sizeof(pgd_t));
 796         reg = __pa(cfg->pgd);
 797         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
 798         reg = (phys_addr_t)__pa(cfg->pgd) >> 32;
 799         if (stage1)
 800                 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
 801         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
 802
 803         /*
 804          * TTBCR
 805          * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
 806          */
 807         if (smmu->version > 1) {
 808                 if (PAGE_SIZE == SZ_4K)
 809                         reg = TTBCR_TG0_4K;
 810                 else
 811                         reg = TTBCR_TG0_64K;
 812
 813                 if (!stage1) {
 814                         reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
 815
 816                         switch (smmu->s2_output_size) {
 817                         case 32:
 818                                 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
 819                                 break;
 820                         case 36:
 821                                 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
 822                                 break;
 823                         case 40:
 824                                 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
 825                                 break;
 826                         case 42:
 827                                 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
 828                                 break;
 829                         case 44:
 830                                 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
 831                                 break;
 832                         case 48:
 833                                 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
 834                                 break;
 835                         }
 836                 } else {
 837                         reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT;
 838                 }
 839         } else {
 840                 reg = 0;
 841         }
 842
 843         reg |= TTBCR_EAE |
 844               (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
 845               (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
 846               (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
 847
 848         if (!stage1)
 849                 reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
 850
 851         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 852
 853         /* MAIR0 (stage-1 only) */
 854         if (stage1) {
 855                 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
 856                       (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
 857                       (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
 858                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
 859         }
 860
 861         /* SCTLR */
 862         reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
 863         if (stage1)
 864                 reg |= SCTLR_S1_ASIDPNE;
 865 #ifdef __BIG_ENDIAN
 866         reg |= SCTLR_E;
 867 #endif
 868         writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
 869 }
 870
 871 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 872                                         struct arm_smmu_device *smmu)
 873 {
 874         int irq, start, ret = 0;
 875         unsigned long flags;
 876         struct arm_smmu_domain *smmu_domain = domain->priv;
 877         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 878
 879         spin_lock_irqsave(&smmu_domain->lock, flags);
 880         if (smmu_domain->smmu)
 881                 goto out_unlock;
 882
 883         if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
 884                 /*
 885                  * We will likely want to change this if/when KVM gets
 886                  * involved.
 887                  */
 888                 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 889                 start = smmu->num_s2_context_banks;
 890         } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) {
 891                 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 892                 start = smmu->num_s2_context_banks;
 893         } else {
 894                 cfg->cbar = CBAR_TYPE_S2_TRANS;
 895                 start = 0;
 896         }
 897
 898         ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
 899                                       smmu->num_context_banks);
 900         if (IS_ERR_VALUE(ret))
 901                 goto out_unlock;
 902
 903         cfg->cbndx = ret;
 904         if (smmu->version == 1) {
 905                 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
 906                 cfg->irptndx %= smmu->num_context_irqs;
 907         } else {
 908                 cfg->irptndx = cfg->cbndx;
 909         }
 910
 911         ACCESS_ONCE(smmu_domain->smmu) = smmu;
 912         arm_smmu_init_context_bank(smmu_domain);
 913         spin_unlock_irqrestore(&smmu_domain->lock, flags);
 914
 915         irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
 916         ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
 917                           "arm-smmu-context-fault", domain);
 918         if (IS_ERR_VALUE(ret)) {
 919                 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
 920                         cfg->irptndx, irq);
 921                 cfg->irptndx = INVALID_IRPTNDX;
 922         }
 923
 924         return 0;
 925
 926 out_unlock:
 927         spin_unlock_irqrestore(&smmu_domain->lock, flags);
 928         return ret;
 929 }
 930
 931 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
 932 {
 933         struct arm_smmu_domain *smmu_domain = domain->priv;
 934         struct arm_smmu_device *smmu = smmu_domain->smmu;
 935         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 936         void __iomem *cb_base;
 937         int irq;
 938
 939         if (!smmu)
 940                 return;
 941
 942         /* Disable the context bank and nuke the TLB before freeing it. */
 943         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 944         writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
 945         arm_smmu_tlb_inv_context(smmu_domain);
 946
 947         if (cfg->irptndx != INVALID_IRPTNDX) {
 948                 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
 949                 free_irq(irq, domain);
 950         }
 951
 952         __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
 953 }
 954
 955 static int arm_smmu_domain_init(struct iommu_domain *domain)
 956 {
 957         struct arm_smmu_domain *smmu_domain;
 958         pgd_t *pgd;
 959
 960         /*
 961          * Allocate the domain and initialise some of its data structures.
 962          * We can't really do anything meaningful until we've added a
 963          * master.
 964          */
 965         smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
 966         if (!smmu_domain)
 967                 return -ENOMEM;
 968
 969         pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
 970         if (!pgd)
 971                 goto out_free_domain;
 972         smmu_domain->cfg.pgd = pgd;
 973
 974         spin_lock_init(&smmu_domain->lock);
 975         domain->priv = smmu_domain;
 976         return 0;
 977
 978 out_free_domain:
 979         kfree(smmu_domain);
 980         return -ENOMEM;
 981 }
 982
 983 static void arm_smmu_free_ptes(pmd_t *pmd)
 984 {
 985         pgtable_t table = pmd_pgtable(*pmd);
 986
 987         __free_page(table);
 988 }
 989
 990 static void arm_smmu_free_pmds(pud_t *pud)
 991 {
 992         int i;
 993         pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
 994
 995         pmd = pmd_base;
 996         for (i = 0; i < PTRS_PER_PMD; ++i) {
 997                 if (pmd_none(*pmd))
 998                         continue;
 999
1000                 arm_smmu_free_ptes(pmd);
1001                 pmd++;
1002         }
1003
1004         pmd_free(NULL, pmd_base);
1005 }
1006
1007 static void arm_smmu_free_puds(pgd_t *pgd)
1008 {
1009         int i;
1010         pud_t *pud, *pud_base = pud_offset(pgd, 0);
1011
1012         pud = pud_base;
1013         for (i = 0; i < PTRS_PER_PUD; ++i) {
1014                 if (pud_none(*pud))
1015                         continue;
1016
1017                 arm_smmu_free_pmds(pud);
1018                 pud++;
1019         }
1020
1021         pud_free(NULL, pud_base);
1022 }
1023
1024 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
1025 {
1026         int i;
1027         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1028         pgd_t *pgd, *pgd_base = cfg->pgd;
1029
1030         /*
1031          * Recursively free the page tables for this domain. We don't
1032          * care about speculative TLB filling because the tables should
1033          * not be active in any context bank at this point (SCTLR.M is 0).
1034          */
1035         pgd = pgd_base;
1036         for (i = 0; i < PTRS_PER_PGD; ++i) {
1037                 if (pgd_none(*pgd))
1038                         continue;
1039                 arm_smmu_free_puds(pgd);
1040                 pgd++;
1041         }
1042
1043         kfree(pgd_base);
1044 }
1045
1046 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1047 {
1048         struct arm_smmu_domain *smmu_domain = domain->priv;
1049
1050         /*
1051          * Free the domain resources. We assume that all devices have
1052          * already been detached.
1053          */
1054         arm_smmu_destroy_domain_context(domain);
1055         arm_smmu_free_pgtables(smmu_domain);
1056         kfree(smmu_domain);
1057 }
1058
1059 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1060                                           struct arm_smmu_master_cfg *cfg)
1061 {
1062         int i;
1063         struct arm_smmu_smr *smrs;
1064         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1065
1066         if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1067                 return 0;
1068
1069         if (cfg->smrs)
1070                 return -EEXIST;
1071
1072         smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1073         if (!smrs) {
1074                 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1075                         cfg->num_streamids);
1076                 return -ENOMEM;
1077         }
1078
1079         /* Allocate the SMRs on the SMMU */
1080         for (i = 0; i < cfg->num_streamids; ++i) {
1081                 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1082                                                   smmu->num_mapping_groups);
1083                 if (IS_ERR_VALUE(idx)) {
1084                         dev_err(smmu->dev, "failed to allocate free SMR\n");
1085                         goto err_free_smrs;
1086                 }
1087
1088                 smrs[i] = (struct arm_smmu_smr) {
1089                         .idx    = idx,
1090                         .mask   = 0, /* We don't currently share SMRs */
1091                         .id     = cfg->streamids[i],
1092                 };
1093         }
1094
1095         /* It worked! Now, poke the actual hardware */
1096         for (i = 0; i < cfg->num_streamids; ++i) {
1097                 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1098                           smrs[i].mask << SMR_MASK_SHIFT;
1099                 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1100         }
1101
1102         cfg->smrs = smrs;
1103         return 0;
1104
1105 err_free_smrs:
1106         while (--i >= 0)
1107                 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1108         kfree(smrs);
1109         return -ENOSPC;
1110 }
1111
1112 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1113                                       struct arm_smmu_master_cfg *cfg)
1114 {
1115         int i;
1116         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1117         struct arm_smmu_smr *smrs = cfg->smrs;
1118
1119         if (!smrs)
1120                 return;
1121
1122         /* Invalidate the SMRs before freeing back to the allocator */
1123         for (i = 0; i < cfg->num_streamids; ++i) {
1124                 u8 idx = smrs[i].idx;
1125
1126                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1127                 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1128         }
1129
1130         cfg->smrs = NULL;
1131         kfree(smrs);
1132 }
1133
1134 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1135                                       struct arm_smmu_master_cfg *cfg)
1136 {
1137         int i, ret;
1138         struct arm_smmu_device *smmu = smmu_domain->smmu;
1139         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1140
1141         ret = arm_smmu_master_configure_smrs(smmu, cfg);
1142         if (ret)
1143                 return ret;
1144
1145         for (i = 0; i < cfg->num_streamids; ++i) {
1146                 u32 idx, s2cr;
1147
1148                 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1149                 s2cr = S2CR_TYPE_TRANS |
1150                        (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1151                 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1152         }
1153
1154         return 0;
1155 }
1156
1157 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1158                                           struct arm_smmu_master_cfg *cfg)
1159 {
1160         int i;
1161         struct arm_smmu_device *smmu = smmu_domain->smmu;
1162         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1163
1164         /*
1165          * We *must* clear the S2CR first, because freeing the SMR means
1166          * that it can be re-allocated immediately.
1167          */
1168         for (i = 0; i < cfg->num_streamids; ++i) {
1169                 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1170
1171                 writel_relaxed(S2CR_TYPE_BYPASS,
1172                                gr0_base + ARM_SMMU_GR0_S2CR(idx));
1173         }
1174
1175         arm_smmu_master_free_smrs(smmu, cfg);
1176 }
1177
1178 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1179 {
1180         int ret;
1181         struct arm_smmu_domain *smmu_domain = domain->priv;
1182         struct arm_smmu_device *smmu, *dom_smmu;
1183         struct arm_smmu_master_cfg *cfg;
1184
1185         smmu = dev_get_master_dev(dev)->archdata.iommu;
1186         if (!smmu) {
1187                 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1188                 return -ENXIO;
1189         }
1190
1191         /*
1192          * Sanity check the domain. We don't support domains across
1193          * different SMMUs.
1194          */
1195         dom_smmu = ACCESS_ONCE(smmu_domain->smmu);
1196         if (!dom_smmu) {
1197                 /* Now that we have a master, we can finalise the domain */
1198                 ret = arm_smmu_init_domain_context(domain, smmu);
1199                 if (IS_ERR_VALUE(ret))
1200                         return ret;
1201
1202                 dom_smmu = smmu_domain->smmu;
1203         }
1204
1205         if (dom_smmu != smmu) {
1206                 dev_err(dev,
1207                         "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1208                         dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1209                 return -EINVAL;
1210         }
1211
1212         /* Looks ok, so add the device to the domain */
1213         cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
1214         if (!cfg)
1215                 return -ENODEV;
1216
1217         return arm_smmu_domain_add_master(smmu_domain, cfg);
1218 }
1219
1220 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1221 {
1222         struct arm_smmu_domain *smmu_domain = domain->priv;
1223         struct arm_smmu_master_cfg *cfg;
1224
1225         cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
1226         if (cfg)
1227                 arm_smmu_domain_remove_master(smmu_domain, cfg);
1228 }
1229
1230 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1231                                              unsigned long end)
1232 {
1233         return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1234                 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1235 }
1236
1237 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1238                                    unsigned long addr, unsigned long end,
1239                                    unsigned long pfn, int prot, int stage)
1240 {
1241         pte_t *pte, *start;
1242         pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
1243
1244         if (pmd_none(*pmd)) {
1245                 /* Allocate a new set of tables */
1246                 pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
1247
1248                 if (!table)
1249                         return -ENOMEM;
1250
1251                 arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
1252                 pmd_populate(NULL, pmd, table);
1253                 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1254         }
1255
1256         if (stage == 1) {
1257                 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1258                 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
1259                         pteval |= ARM_SMMU_PTE_AP_RDONLY;
1260
1261                 if (prot & IOMMU_CACHE)
1262                         pteval |= (MAIR_ATTR_IDX_CACHE <<
1263                                    ARM_SMMU_PTE_ATTRINDX_SHIFT);
1264         } else {
1265                 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1266                 if (prot & IOMMU_READ)
1267                         pteval |= ARM_SMMU_PTE_HAP_READ;
1268                 if (prot & IOMMU_WRITE)
1269                         pteval |= ARM_SMMU_PTE_HAP_WRITE;
1270                 if (prot & IOMMU_CACHE)
1271                         pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1272                 else
1273                         pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1274         }
1275
1276         /* If no access, create a faulting entry to avoid TLB fills */
1277         if (prot & IOMMU_EXEC)
1278                 pteval &= ~ARM_SMMU_PTE_XN;
1279         else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
1280                 pteval &= ~ARM_SMMU_PTE_PAGE;
1281
1282         pteval |= ARM_SMMU_PTE_SH_IS;
1283         start = pmd_page_vaddr(*pmd) + pte_index(addr);
1284         pte = start;
1285
1286         /*
1287          * Install the page table entries. This is fairly complicated
1288          * since we attempt to make use of the contiguous hint in the
1289          * ptes where possible. The contiguous hint indicates a series
1290          * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1291          * contiguous region with the following constraints:
1292          *
1293          *   - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1294          *   - Each pte in the region has the contiguous hint bit set
1295          *
1296          * This complicates unmapping (also handled by this code, when
1297          * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1298          * possible, yet highly unlikely, that a client may unmap only
1299          * part of a contiguous range. This requires clearing of the
1300          * contiguous hint bits in the range before installing the new
1301          * faulting entries.
1302          *
1303          * Note that re-mapping an address range without first unmapping
1304          * it is not supported, so TLB invalidation is not required here
1305          * and is instead performed at unmap and domain-init time.
1306          */
1307         do {
1308                 int i = 1;
1309
1310                 pteval &= ~ARM_SMMU_PTE_CONT;
1311
1312                 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1313                         i = ARM_SMMU_PTE_CONT_ENTRIES;
1314                         pteval |= ARM_SMMU_PTE_CONT;
1315                 } else if (pte_val(*pte) &
1316                            (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1317                         int j;
1318                         pte_t *cont_start;
1319                         unsigned long idx = pte_index(addr);
1320
1321                         idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1322                         cont_start = pmd_page_vaddr(*pmd) + idx;
1323                         for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1324                                 pte_val(*(cont_start + j)) &=
1325                                         ~ARM_SMMU_PTE_CONT;
1326
1327                         arm_smmu_flush_pgtable(smmu, cont_start,
1328                                                sizeof(*pte) *
1329                                                ARM_SMMU_PTE_CONT_ENTRIES);
1330                 }
1331
1332                 do {
1333                         *pte = pfn_pte(pfn, __pgprot(pteval));
1334                 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1335         } while (addr != end);
1336
1337         arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1338         return 0;
1339 }
1340
1341 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1342                                    unsigned long addr, unsigned long end,
1343                                    phys_addr_t phys, int prot, int stage)
1344 {
1345         int ret;
1346         pmd_t *pmd;
1347         unsigned long next, pfn = __phys_to_pfn(phys);
1348
1349 #ifndef __PAGETABLE_PMD_FOLDED
1350         if (pud_none(*pud)) {
1351                 pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
1352                 if (!pmd)
1353                         return -ENOMEM;
1354
1355                 arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE);
1356                 pud_populate(NULL, pud, pmd);
1357                 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1358
1359                 pmd += pmd_index(addr);
1360         } else
1361 #endif
1362                 pmd = pmd_offset(pud, addr);
1363
1364         do {
1365                 next = pmd_addr_end(addr, end);
1366                 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn,
1367                                               prot, stage);
1368                 phys += next - addr;
1369         } while (pmd++, addr = next, addr < end);
1370
1371         return ret;
1372 }
1373
1374 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1375                                    unsigned long addr, unsigned long end,
1376                                    phys_addr_t phys, int prot, int stage)
1377 {
1378         int ret = 0;
1379         pud_t *pud;
1380         unsigned long next;
1381
1382 #ifndef __PAGETABLE_PUD_FOLDED
1383         if (pgd_none(*pgd)) {
1384                 pud = (pud_t *)get_zeroed_page(GFP_ATOMIC);
1385                 if (!pud)
1386                         return -ENOMEM;
1387
1388                 arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE);
1389                 pgd_populate(NULL, pgd, pud);
1390                 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1391
1392                 pud += pud_index(addr);
1393         } else
1394 #endif
1395                 pud = pud_offset(pgd, addr);
1396
1397         do {
1398                 next = pud_addr_end(addr, end);
1399                 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1400                                               prot, stage);
1401                 phys += next - addr;
1402         } while (pud++, addr = next, addr < end);
1403
1404         return ret;
1405 }
1406
1407 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1408                                    unsigned long iova, phys_addr_t paddr,
1409                                    size_t size, int prot)
1410 {
1411         int ret, stage;
1412         unsigned long end;
1413         phys_addr_t input_mask, output_mask;
1414         struct arm_smmu_device *smmu = smmu_domain->smmu;
1415         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1416         pgd_t *pgd = cfg->pgd;
1417         unsigned long flags;
1418
1419         if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
1420                 stage = 2;
1421                 output_mask = (1ULL << smmu->s2_output_size) - 1;
1422         } else {
1423                 stage = 1;
1424                 output_mask = (1ULL << smmu->s1_output_size) - 1;
1425         }
1426
1427         if (!pgd)
1428                 return -EINVAL;
1429
1430         if (size & ~PAGE_MASK)
1431                 return -EINVAL;
1432
1433         input_mask = (1ULL << smmu->input_size) - 1;
1434         if ((phys_addr_t)iova & ~input_mask)
1435                 return -ERANGE;
1436
1437         if (paddr & ~output_mask)
1438                 return -ERANGE;
1439
1440         spin_lock_irqsave(&smmu_domain->lock, flags);
1441         pgd += pgd_index(iova);
1442         end = iova + size;
1443         do {
1444                 unsigned long next = pgd_addr_end(iova, end);
1445
1446                 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1447                                               prot, stage);
1448                 if (ret)
1449                         goto out_unlock;
1450
1451                 paddr += next - iova;
1452                 iova = next;
1453         } while (pgd++, iova != end);
1454
1455 out_unlock:
1456         spin_unlock_irqrestore(&smmu_domain->lock, flags);
1457
1458         return ret;
1459 }
1460
1461 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1462                         phys_addr_t paddr, size_t size, int prot)
1463 {
1464         struct arm_smmu_domain *smmu_domain = domain->priv;
1465
1466         if (!smmu_domain)
1467                 return -ENODEV;
1468
1469         return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
1470 }
1471
1472 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1473                              size_t size)
1474 {
1475         int ret;
1476         struct arm_smmu_domain *smmu_domain = domain->priv;
1477
1478         ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1479         arm_smmu_tlb_inv_context(smmu_domain);
1480         return ret ? 0 : size;
1481 }
1482
1483 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1484                                          dma_addr_t iova)
1485 {
1486         pgd_t *pgdp, pgd;
1487         pud_t pud;
1488         pmd_t pmd;
1489         pte_t pte;
1490         struct arm_smmu_domain *smmu_domain = domain->priv;
1491         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1492
1493         pgdp = cfg->pgd;
1494         if (!pgdp)
1495                 return 0;
1496
1497         pgd = *(pgdp + pgd_index(iova));
1498         if (pgd_none(pgd))
1499                 return 0;
1500
1501         pud = *pud_offset(&pgd, iova);
1502         if (pud_none(pud))
1503                 return 0;
1504
1505         pmd = *pmd_offset(&pud, iova);
1506         if (pmd_none(pmd))
1507                 return 0;
1508
1509         pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1510         if (pte_none(pte))
1511                 return 0;
1512
1513         return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1514 }
1515
1516 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1517                                    unsigned long cap)
1518 {
1519         struct arm_smmu_domain *smmu_domain = domain->priv;
1520         struct arm_smmu_device *smmu = smmu_domain->smmu;
1521         u32 features = smmu ? smmu->features : 0;
1522
1523         switch (cap) {
1524         case IOMMU_CAP_CACHE_COHERENCY:
1525                 return features & ARM_SMMU_FEAT_COHERENT_WALK;
1526         case IOMMU_CAP_INTR_REMAP:
1527                 return 1; /* MSIs are just memory writes */
1528         default:
1529                 return 0;
1530         }
1531 }
1532
1533 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1534 {
1535         *((u16 *)data) = alias;
1536         return 0; /* Continue walking */
1537 }
1538
1539 static int arm_smmu_add_device(struct device *dev)
1540 {
1541         struct arm_smmu_device *smmu;
1542         struct iommu_group *group;
1543         int ret;
1544
1545         if (dev->archdata.iommu) {
1546                 dev_warn(dev, "IOMMU driver already assigned to device\n");
1547                 return -EINVAL;
1548         }
1549
1550         smmu = find_smmu_for_device(dev);
1551         if (!smmu)
1552                 return -ENODEV;
1553
1554         group = iommu_group_alloc();
1555         if (IS_ERR(group)) {
1556                 dev_err(dev, "Failed to allocate IOMMU group\n");
1557                 return PTR_ERR(group);
1558         }
1559
1560         if (dev_is_pci(dev)) {
1561                 struct arm_smmu_master_cfg *cfg;
1562                 struct pci_dev *pdev = to_pci_dev(dev);
1563
1564                 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1565                 if (!cfg) {
1566                         ret = -ENOMEM;
1567                         goto out_put_group;
1568                 }
1569
1570                 cfg->num_streamids = 1;
1571                 /*
1572                  * Assume Stream ID == Requester ID for now.
1573                  * We need a way to describe the ID mappings in FDT.
1574                  */
1575                 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid,
1576                                        &cfg->streamids[0]);
1577                 dev->archdata.iommu = cfg;
1578         } else {
1579                 dev->archdata.iommu = smmu;
1580         }
1581
1582         ret = iommu_group_add_device(group, dev);
1583
1584 out_put_group:
1585         iommu_group_put(group);
1586         return ret;
1587 }
1588
1589 static void arm_smmu_remove_device(struct device *dev)
1590 {
1591         if (dev_is_pci(dev))
1592                 kfree(dev->archdata.iommu);
1593
1594         dev->archdata.iommu = NULL;
1595         iommu_group_remove_device(dev);
1596 }
1597
1598 static const struct iommu_ops arm_smmu_ops = {
1599         .domain_init    = arm_smmu_domain_init,
1600         .domain_destroy = arm_smmu_domain_destroy,
1601         .attach_dev     = arm_smmu_attach_dev,
1602         .detach_dev     = arm_smmu_detach_dev,
1603         .map            = arm_smmu_map,
1604         .unmap          = arm_smmu_unmap,
1605         .iova_to_phys   = arm_smmu_iova_to_phys,
1606         .domain_has_cap = arm_smmu_domain_has_cap,
1607         .add_device     = arm_smmu_add_device,
1608         .remove_device  = arm_smmu_remove_device,
1609         .pgsize_bitmap  = (SECTION_SIZE |
1610                            ARM_SMMU_PTE_CONT_SIZE |
1611                            PAGE_SIZE),
1612 };
1613
1614 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1615 {
1616         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1617         void __iomem *cb_base;
1618         int i = 0;
1619         u32 reg;
1620
1621         /* clear global FSR */
1622         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1623         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1624
1625         /* Mark all SMRn as invalid and all S2CRn as bypass */
1626         for (i = 0; i < smmu->num_mapping_groups; ++i) {
1627                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
1628                 writel_relaxed(S2CR_TYPE_BYPASS,
1629                         gr0_base + ARM_SMMU_GR0_S2CR(i));
1630         }
1631
1632         /* Make sure all context banks are disabled and clear CB_FSR  */
1633         for (i = 0; i < smmu->num_context_banks; ++i) {
1634                 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1635                 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1636                 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1637         }
1638
1639         /* Invalidate the TLB, just in case */
1640         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1641         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1642         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1643
1644         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1645
1646         /* Enable fault reporting */
1647         reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1648
1649         /* Disable TLB broadcasting. */
1650         reg |= (sCR0_VMIDPNE | sCR0_PTM);
1651
1652         /* Enable client access, but bypass when no mapping is found */
1653         reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1654
1655         /* Disable forced broadcasting */
1656         reg &= ~sCR0_FB;
1657
1658         /* Don't upgrade barriers */
1659         reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1660
1661         /* Push the button */
1662         arm_smmu_tlb_sync(smmu);
1663         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1664 }
1665
1666 static int arm_smmu_id_size_to_bits(int size)
1667 {
1668         switch (size) {
1669         case 0:
1670                 return 32;
1671         case 1:
1672                 return 36;
1673         case 2:
1674                 return 40;
1675         case 3:
1676                 return 42;
1677         case 4:
1678                 return 44;
1679         case 5:
1680         default:
1681                 return 48;
1682         }
1683 }
1684
1685 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1686 {
1687         unsigned long size;
1688         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1689         u32 id;
1690
1691         dev_notice(smmu->dev, "probing hardware configuration...\n");
1692
1693         /* Primecell ID */
1694         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1695         smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1696         dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1697
1698         /* ID0 */
1699         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1700 #ifndef CONFIG_64BIT
1701         if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1702                 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1703                 return -ENODEV;
1704         }
1705 #endif
1706         if (id & ID0_S1TS) {
1707                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1708                 dev_notice(smmu->dev, "\tstage 1 translation\n");
1709         }
1710
1711         if (id & ID0_S2TS) {
1712                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1713                 dev_notice(smmu->dev, "\tstage 2 translation\n");
1714         }
1715
1716         if (id & ID0_NTS) {
1717                 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1718                 dev_notice(smmu->dev, "\tnested translation\n");
1719         }
1720
1721         if (!(smmu->features &
1722                 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1723                  ARM_SMMU_FEAT_TRANS_NESTED))) {
1724                 dev_err(smmu->dev, "\tno translation support!\n");
1725                 return -ENODEV;
1726         }
1727
1728         if (id & ID0_CTTW) {
1729                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1730                 dev_notice(smmu->dev, "\tcoherent table walk\n");
1731         }
1732
1733         if (id & ID0_SMS) {
1734                 u32 smr, sid, mask;
1735
1736                 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1737                 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1738                                            ID0_NUMSMRG_MASK;
1739                 if (smmu->num_mapping_groups == 0) {
1740                         dev_err(smmu->dev,
1741                                 "stream-matching supported, but no SMRs present!\n");
1742                         return -ENODEV;
1743                 }
1744
1745                 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1746                 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1747                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1748                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1749
1750                 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1751                 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1752                 if ((mask & sid) != sid) {
1753                         dev_err(smmu->dev,
1754                                 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1755                                 mask, sid);
1756                         return -ENODEV;
1757                 }
1758
1759                 dev_notice(smmu->dev,
1760                            "\tstream matching with %u register groups, mask 0x%x",
1761                            smmu->num_mapping_groups, mask);
1762         }
1763
1764         /* ID1 */
1765         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1766         smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1767
1768         /* Check for size mismatch of SMMU address space from mapped region */
1769         size = 1 <<
1770                 (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1771         size *= (smmu->pagesize << 1);
1772         if (smmu->size != size)
1773                 dev_warn(smmu->dev,
1774                         "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1775                         size, smmu->size);
1776
1777         smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1778                                       ID1_NUMS2CB_MASK;
1779         smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1780         if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1781                 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1782                 return -ENODEV;
1783         }
1784         dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1785                    smmu->num_context_banks, smmu->num_s2_context_banks);
1786
1787         /* ID2 */
1788         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1789         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1790
1791         /*
1792          * Stage-1 output limited by stage-2 input size due to pgd
1793          * allocation (PTRS_PER_PGD).
1794          */
1795 #ifdef CONFIG_64BIT
1796         smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
1797 #else
1798         smmu->s1_output_size = min(32UL, size);
1799 #endif
1800
1801         /* The stage-2 output mask is also applied for bypass */
1802         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1803         smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
1804
1805         if (smmu->version == 1) {
1806                 smmu->input_size = 32;
1807         } else {
1808 #ifdef CONFIG_64BIT
1809                 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1810                 size = min(VA_BITS, arm_smmu_id_size_to_bits(size));
1811 #else
1812                 size = 32;
1813 #endif
1814                 smmu->input_size = size;
1815
1816                 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1817                     (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1818                     (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1819                         dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1820                                 PAGE_SIZE);
1821                         return -ENODEV;
1822                 }
1823         }
1824
1825         dev_notice(smmu->dev,
1826                    "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1827                    smmu->input_size, smmu->s1_output_size,
1828                    smmu->s2_output_size);
1829         return 0;
1830 }
1831
1832 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1833 {
1834         struct resource *res;
1835         struct arm_smmu_device *smmu;
1836         struct device *dev = &pdev->dev;
1837         struct rb_node *node;
1838         struct of_phandle_args masterspec;
1839         int num_irqs, i, err;
1840
1841         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1842         if (!smmu) {
1843                 dev_err(dev, "failed to allocate arm_smmu_device\n");
1844                 return -ENOMEM;
1845         }
1846         smmu->dev = dev;
1847
1848         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1849         smmu->base = devm_ioremap_resource(dev, res);
1850         if (IS_ERR(smmu->base))
1851                 return PTR_ERR(smmu->base);
1852         smmu->size = resource_size(res);
1853
1854         if (of_property_read_u32(dev->of_node, "#global-interrupts",
1855                                  &smmu->num_global_irqs)) {
1856                 dev_err(dev, "missing #global-interrupts property\n");
1857                 return -ENODEV;
1858         }
1859
1860         num_irqs = 0;
1861         while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1862                 num_irqs++;
1863                 if (num_irqs > smmu->num_global_irqs)
1864                         smmu->num_context_irqs++;
1865         }
1866
1867         if (!smmu->num_context_irqs) {
1868                 dev_err(dev, "found %d interrupts but expected at least %d\n",
1869                         num_irqs, smmu->num_global_irqs + 1);
1870                 return -ENODEV;
1871         }
1872
1873         smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1874                                   GFP_KERNEL);
1875         if (!smmu->irqs) {
1876                 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1877                 return -ENOMEM;
1878         }
1879
1880         for (i = 0; i < num_irqs; ++i) {
1881                 int irq = platform_get_irq(pdev, i);
1882
1883                 if (irq < 0) {
1884                         dev_err(dev, "failed to get irq index %d\n", i);
1885                         return -ENODEV;
1886                 }
1887                 smmu->irqs[i] = irq;
1888         }
1889
1890         i = 0;
1891         smmu->masters = RB_ROOT;
1892         while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1893                                            "#stream-id-cells", i,
1894                                            &masterspec)) {
1895                 err = register_smmu_master(smmu, dev, &masterspec);
1896                 if (err) {
1897                         dev_err(dev, "failed to add master %s\n",
1898                                 masterspec.np->name);
1899                         goto out_put_masters;
1900                 }
1901
1902                 i++;
1903         }
1904         dev_notice(dev, "registered %d master devices\n", i);
1905
1906         err = arm_smmu_device_cfg_probe(smmu);
1907         if (err)
1908                 goto out_put_masters;
1909
1910         parse_driver_options(smmu);
1911
1912         if (smmu->version > 1 &&
1913             smmu->num_context_banks != smmu->num_context_irqs) {
1914                 dev_err(dev,
1915                         "found only %d context interrupt(s) but %d required\n",
1916                         smmu->num_context_irqs, smmu->num_context_banks);
1917                 err = -ENODEV;
1918                 goto out_put_masters;
1919         }
1920
1921         for (i = 0; i < smmu->num_global_irqs; ++i) {
1922                 err = request_irq(smmu->irqs[i],
1923                                   arm_smmu_global_fault,
1924                                   IRQF_SHARED,
1925                                   "arm-smmu global fault",
1926                                   smmu);
1927                 if (err) {
1928                         dev_err(dev, "failed to request global IRQ %d (%u)\n",
1929                                 i, smmu->irqs[i]);
1930                         goto out_free_irqs;
1931                 }
1932         }
1933
1934         INIT_LIST_HEAD(&smmu->list);
1935         spin_lock(&arm_smmu_devices_lock);
1936         list_add(&smmu->list, &arm_smmu_devices);
1937         spin_unlock(&arm_smmu_devices_lock);
1938
1939         arm_smmu_device_reset(smmu);
1940         return 0;
1941
1942 out_free_irqs:
1943         while (i--)
1944                 free_irq(smmu->irqs[i], smmu);
1945
1946 out_put_masters:
1947         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1948                 struct arm_smmu_master *master
1949                         = container_of(node, struct arm_smmu_master, node);
1950                 of_node_put(master->of_node);
1951         }
1952
1953         return err;
1954 }
1955
1956 static int arm_smmu_device_remove(struct platform_device *pdev)
1957 {
1958         int i;
1959         struct device *dev = &pdev->dev;
1960         struct arm_smmu_device *curr, *smmu = NULL;
1961         struct rb_node *node;
1962
1963         spin_lock(&arm_smmu_devices_lock);
1964         list_for_each_entry(curr, &arm_smmu_devices, list) {
1965                 if (curr->dev == dev) {
1966                         smmu = curr;
1967                         list_del(&smmu->list);
1968                         break;
1969                 }
1970         }
1971         spin_unlock(&arm_smmu_devices_lock);
1972
1973         if (!smmu)
1974                 return -ENODEV;
1975
1976         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1977                 struct arm_smmu_master *master
1978                         = container_of(node, struct arm_smmu_master, node);
1979                 of_node_put(master->of_node);
1980         }
1981
1982         if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1983                 dev_err(dev, "removing device with active domains!\n");
1984
1985         for (i = 0; i < smmu->num_global_irqs; ++i)
1986                 free_irq(smmu->irqs[i], smmu);
1987
1988         /* Turn the thing off */
1989         writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1990         return 0;
1991 }
1992
1993 #ifdef CONFIG_OF
1994 static struct of_device_id arm_smmu_of_match[] = {
1995         { .compatible = "arm,smmu-v1", },
1996         { .compatible = "arm,smmu-v2", },
1997         { .compatible = "arm,mmu-400", },
1998         { .compatible = "arm,mmu-500", },
1999         { },
2000 };
2001 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
2002 #endif
2003
2004 static struct platform_driver arm_smmu_driver = {
2005         .driver = {
2006                 .owner          = THIS_MODULE,
2007                 .name           = "arm-smmu",
2008                 .of_match_table = of_match_ptr(arm_smmu_of_match),
2009         },
2010         .probe  = arm_smmu_device_dt_probe,
2011         .remove = arm_smmu_device_remove,
2012 };
2013
2014 static int __init arm_smmu_init(void)
2015 {
2016         int ret;
2017
2018         ret = platform_driver_register(&arm_smmu_driver);
2019         if (ret)
2020                 return ret;
2021
2022         /* Oh, for a proper bus abstraction */
2023         if (!iommu_present(&platform_bus_type))
2024                 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2025
2026 #ifdef CONFIG_ARM_AMBA
2027         if (!iommu_present(&amba_bustype))
2028                 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2029 #endif
2030
2031 #ifdef CONFIG_PCI
2032         if (!iommu_present(&pci_bus_type))
2033                 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2034 #endif
2035
2036         return 0;
2037 }
2038
2039 static void __exit arm_smmu_exit(void)
2040 {
2041         return platform_driver_unregister(&arm_smmu_driver);
2042 }
2043
2044 subsys_initcall(arm_smmu_init);
2045 module_exit(arm_smmu_exit);
2046
2047 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2048 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2049 MODULE_LICENSE("GPL v2");