drivers/iommu/arm-smmu.c

   1 /*
   2  * IOMMU API for ARM architected SMMU implementations.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16  *
  17  * Copyright (C) 2013 ARM Limited
  18  *
  19  * Author: Will Deacon <will.deacon@arm.com>
  20  *
  21  * This driver currently supports:
  22  *      - SMMUv1 and v2 implementations
  23  *      - Stream-matching and stream-indexing
  24  *      - v7/v8 long-descriptor format
  25  *      - Non-secure access to the SMMU
  26  *      - 4k and 64k pages, with contiguous pte hints.
  27  *      - Up to 42-bit addressing (dependent on VA_BITS)
  28  *      - Context fault reporting
  29  */
  30
  31 #define pr_fmt(fmt) "arm-smmu: " fmt
  32
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/err.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/io.h>
  38 #include <linux/iommu.h>
  39 #include <linux/mm.h>
  40 #include <linux/module.h>
  41 #include <linux/of.h>
  42 #include <linux/pci.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/slab.h>
  45 #include <linux/spinlock.h>
  46
  47 #include <linux/amba/bus.h>
  48
  49 #include <asm/pgalloc.h>
  50
  51 /* Maximum number of stream IDs assigned to a single device */
  52 #define MAX_MASTER_STREAMIDS            MAX_PHANDLE_ARGS
  53
  54 /* Maximum number of context banks per SMMU */
  55 #define ARM_SMMU_MAX_CBS                128
  56
  57 /* Maximum number of mapping groups per SMMU */
  58 #define ARM_SMMU_MAX_SMRS               128
  59
  60 /* SMMU global address space */
  61 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
  62 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (smmu)->pagesize)
  63
  64 /*
  65  * SMMU global address space with conditional offset to access secure
  66  * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
  67  * nsGFSYNR0: 0x450)
  68  */
  69 #define ARM_SMMU_GR0_NS(smmu)                                           \
  70         ((smmu)->base +                                                 \
  71                 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)       \
  72                         ? 0x400 : 0))
  73
  74 /* Page table bits */
  75 #define ARM_SMMU_PTE_XN                 (((pteval_t)3) << 53)
  76 #define ARM_SMMU_PTE_CONT               (((pteval_t)1) << 52)
  77 #define ARM_SMMU_PTE_AF                 (((pteval_t)1) << 10)
  78 #define ARM_SMMU_PTE_SH_NS              (((pteval_t)0) << 8)
  79 #define ARM_SMMU_PTE_SH_OS              (((pteval_t)2) << 8)
  80 #define ARM_SMMU_PTE_SH_IS              (((pteval_t)3) << 8)
  81 #define ARM_SMMU_PTE_PAGE               (((pteval_t)3) << 0)
  82
  83 #if PAGE_SIZE == SZ_4K
  84 #define ARM_SMMU_PTE_CONT_ENTRIES       16
  85 #elif PAGE_SIZE == SZ_64K
  86 #define ARM_SMMU_PTE_CONT_ENTRIES       32
  87 #else
  88 #define ARM_SMMU_PTE_CONT_ENTRIES       1
  89 #endif
  90
  91 #define ARM_SMMU_PTE_CONT_SIZE          (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
  92 #define ARM_SMMU_PTE_CONT_MASK          (~(ARM_SMMU_PTE_CONT_SIZE - 1))
  93
  94 /* Stage-1 PTE */
  95 #define ARM_SMMU_PTE_AP_UNPRIV          (((pteval_t)1) << 6)
  96 #define ARM_SMMU_PTE_AP_RDONLY          (((pteval_t)2) << 6)
  97 #define ARM_SMMU_PTE_ATTRINDX_SHIFT     2
  98 #define ARM_SMMU_PTE_nG                 (((pteval_t)1) << 11)
  99
 100 /* Stage-2 PTE */
 101 #define ARM_SMMU_PTE_HAP_FAULT          (((pteval_t)0) << 6)
 102 #define ARM_SMMU_PTE_HAP_READ           (((pteval_t)1) << 6)
 103 #define ARM_SMMU_PTE_HAP_WRITE          (((pteval_t)2) << 6)
 104 #define ARM_SMMU_PTE_MEMATTR_OIWB       (((pteval_t)0xf) << 2)
 105 #define ARM_SMMU_PTE_MEMATTR_NC         (((pteval_t)0x5) << 2)
 106 #define ARM_SMMU_PTE_MEMATTR_DEV        (((pteval_t)0x1) << 2)
 107
 108 /* Configuration registers */
 109 #define ARM_SMMU_GR0_sCR0               0x0
 110 #define sCR0_CLIENTPD                   (1 << 0)
 111 #define sCR0_GFRE                       (1 << 1)
 112 #define sCR0_GFIE                       (1 << 2)
 113 #define sCR0_GCFGFRE                    (1 << 4)
 114 #define sCR0_GCFGFIE                    (1 << 5)
 115 #define sCR0_USFCFG                     (1 << 10)
 116 #define sCR0_VMIDPNE                    (1 << 11)
 117 #define sCR0_PTM                        (1 << 12)
 118 #define sCR0_FB                         (1 << 13)
 119 #define sCR0_BSU_SHIFT                  14
 120 #define sCR0_BSU_MASK                   0x3
 121
 122 /* Identification registers */
 123 #define ARM_SMMU_GR0_ID0                0x20
 124 #define ARM_SMMU_GR0_ID1                0x24
 125 #define ARM_SMMU_GR0_ID2                0x28
 126 #define ARM_SMMU_GR0_ID3                0x2c
 127 #define ARM_SMMU_GR0_ID4                0x30
 128 #define ARM_SMMU_GR0_ID5                0x34
 129 #define ARM_SMMU_GR0_ID6                0x38
 130 #define ARM_SMMU_GR0_ID7                0x3c
 131 #define ARM_SMMU_GR0_sGFSR              0x48
 132 #define ARM_SMMU_GR0_sGFSYNR0           0x50
 133 #define ARM_SMMU_GR0_sGFSYNR1           0x54
 134 #define ARM_SMMU_GR0_sGFSYNR2           0x58
 135 #define ARM_SMMU_GR0_PIDR0              0xfe0
 136 #define ARM_SMMU_GR0_PIDR1              0xfe4
 137 #define ARM_SMMU_GR0_PIDR2              0xfe8
 138
 139 #define ID0_S1TS                        (1 << 30)
 140 #define ID0_S2TS                        (1 << 29)
 141 #define ID0_NTS                         (1 << 28)
 142 #define ID0_SMS                         (1 << 27)
 143 #define ID0_PTFS_SHIFT                  24
 144 #define ID0_PTFS_MASK                   0x2
 145 #define ID0_PTFS_V8_ONLY                0x2
 146 #define ID0_CTTW                        (1 << 14)
 147 #define ID0_NUMIRPT_SHIFT               16
 148 #define ID0_NUMIRPT_MASK                0xff
 149 #define ID0_NUMSIDB_SHIFT               9
 150 #define ID0_NUMSIDB_MASK                0xf
 151 #define ID0_NUMSMRG_SHIFT               0
 152 #define ID0_NUMSMRG_MASK                0xff
 153
 154 #define ID1_PAGESIZE                    (1 << 31)
 155 #define ID1_NUMPAGENDXB_SHIFT           28
 156 #define ID1_NUMPAGENDXB_MASK            7
 157 #define ID1_NUMS2CB_SHIFT               16
 158 #define ID1_NUMS2CB_MASK                0xff
 159 #define ID1_NUMCB_SHIFT                 0
 160 #define ID1_NUMCB_MASK                  0xff
 161
 162 #define ID2_OAS_SHIFT                   4
 163 #define ID2_OAS_MASK                    0xf
 164 #define ID2_IAS_SHIFT                   0
 165 #define ID2_IAS_MASK                    0xf
 166 #define ID2_UBS_SHIFT                   8
 167 #define ID2_UBS_MASK                    0xf
 168 #define ID2_PTFS_4K                     (1 << 12)
 169 #define ID2_PTFS_16K                    (1 << 13)
 170 #define ID2_PTFS_64K                    (1 << 14)
 171
 172 #define PIDR2_ARCH_SHIFT                4
 173 #define PIDR2_ARCH_MASK                 0xf
 174
 175 /* Global TLB invalidation */
 176 #define ARM_SMMU_GR0_STLBIALL           0x60
 177 #define ARM_SMMU_GR0_TLBIVMID           0x64
 178 #define ARM_SMMU_GR0_TLBIALLNSNH        0x68
 179 #define ARM_SMMU_GR0_TLBIALLH           0x6c
 180 #define ARM_SMMU_GR0_sTLBGSYNC          0x70
 181 #define ARM_SMMU_GR0_sTLBGSTATUS        0x74
 182 #define sTLBGSTATUS_GSACTIVE            (1 << 0)
 183 #define TLB_LOOP_TIMEOUT                1000000 /* 1s! */
 184
 185 /* Stream mapping registers */
 186 #define ARM_SMMU_GR0_SMR(n)             (0x800 + ((n) << 2))
 187 #define SMR_VALID                       (1 << 31)
 188 #define SMR_MASK_SHIFT                  16
 189 #define SMR_MASK_MASK                   0x7fff
 190 #define SMR_ID_SHIFT                    0
 191 #define SMR_ID_MASK                     0x7fff
 192
 193 #define ARM_SMMU_GR0_S2CR(n)            (0xc00 + ((n) << 2))
 194 #define S2CR_CBNDX_SHIFT                0
 195 #define S2CR_CBNDX_MASK                 0xff
 196 #define S2CR_TYPE_SHIFT                 16
 197 #define S2CR_TYPE_MASK                  0x3
 198 #define S2CR_TYPE_TRANS                 (0 << S2CR_TYPE_SHIFT)
 199 #define S2CR_TYPE_BYPASS                (1 << S2CR_TYPE_SHIFT)
 200 #define S2CR_TYPE_FAULT                 (2 << S2CR_TYPE_SHIFT)
 201
 202 /* Context bank attribute registers */
 203 #define ARM_SMMU_GR1_CBAR(n)            (0x0 + ((n) << 2))
 204 #define CBAR_VMID_SHIFT                 0
 205 #define CBAR_VMID_MASK                  0xff
 206 #define CBAR_S1_BPSHCFG_SHIFT           8
 207 #define CBAR_S1_BPSHCFG_MASK            3
 208 #define CBAR_S1_BPSHCFG_NSH             3
 209 #define CBAR_S1_MEMATTR_SHIFT           12
 210 #define CBAR_S1_MEMATTR_MASK            0xf
 211 #define CBAR_S1_MEMATTR_WB              0xf
 212 #define CBAR_TYPE_SHIFT                 16
 213 #define CBAR_TYPE_MASK                  0x3
 214 #define CBAR_TYPE_S2_TRANS              (0 << CBAR_TYPE_SHIFT)
 215 #define CBAR_TYPE_S1_TRANS_S2_BYPASS    (1 << CBAR_TYPE_SHIFT)
 216 #define CBAR_TYPE_S1_TRANS_S2_FAULT     (2 << CBAR_TYPE_SHIFT)
 217 #define CBAR_TYPE_S1_TRANS_S2_TRANS     (3 << CBAR_TYPE_SHIFT)
 218 #define CBAR_IRPTNDX_SHIFT              24
 219 #define CBAR_IRPTNDX_MASK               0xff
 220
 221 #define ARM_SMMU_GR1_CBA2R(n)           (0x800 + ((n) << 2))
 222 #define CBA2R_RW64_32BIT                (0 << 0)
 223 #define CBA2R_RW64_64BIT                (1 << 0)
 224
 225 /* Translation context bank */
 226 #define ARM_SMMU_CB_BASE(smmu)          ((smmu)->base + ((smmu)->size >> 1))
 227 #define ARM_SMMU_CB(smmu, n)            ((n) * (smmu)->pagesize)
 228
 229 #define ARM_SMMU_CB_SCTLR               0x0
 230 #define ARM_SMMU_CB_RESUME              0x8
 231 #define ARM_SMMU_CB_TTBCR2              0x10
 232 #define ARM_SMMU_CB_TTBR0_LO            0x20
 233 #define ARM_SMMU_CB_TTBR0_HI            0x24
 234 #define ARM_SMMU_CB_TTBCR               0x30
 235 #define ARM_SMMU_CB_S1_MAIR0            0x38
 236 #define ARM_SMMU_CB_FSR                 0x58
 237 #define ARM_SMMU_CB_FAR_LO              0x60
 238 #define ARM_SMMU_CB_FAR_HI              0x64
 239 #define ARM_SMMU_CB_FSYNR0              0x68
 240 #define ARM_SMMU_CB_S1_TLBIASID         0x610
 241
 242 #define SCTLR_S1_ASIDPNE                (1 << 12)
 243 #define SCTLR_CFCFG                     (1 << 7)
 244 #define SCTLR_CFIE                      (1 << 6)
 245 #define SCTLR_CFRE                      (1 << 5)
 246 #define SCTLR_E                         (1 << 4)
 247 #define SCTLR_AFE                       (1 << 2)
 248 #define SCTLR_TRE                       (1 << 1)
 249 #define SCTLR_M                         (1 << 0)
 250 #define SCTLR_EAE_SBOP                  (SCTLR_AFE | SCTLR_TRE)
 251
 252 #define RESUME_RETRY                    (0 << 0)
 253 #define RESUME_TERMINATE                (1 << 0)
 254
 255 #define TTBCR_EAE                       (1 << 31)
 256
 257 #define TTBCR_PASIZE_SHIFT              16
 258 #define TTBCR_PASIZE_MASK               0x7
 259
 260 #define TTBCR_TG0_4K                    (0 << 14)
 261 #define TTBCR_TG0_64K                   (1 << 14)
 262
 263 #define TTBCR_SH0_SHIFT                 12
 264 #define TTBCR_SH0_MASK                  0x3
 265 #define TTBCR_SH_NS                     0
 266 #define TTBCR_SH_OS                     2
 267 #define TTBCR_SH_IS                     3
 268
 269 #define TTBCR_ORGN0_SHIFT               10
 270 #define TTBCR_IRGN0_SHIFT               8
 271 #define TTBCR_RGN_MASK                  0x3
 272 #define TTBCR_RGN_NC                    0
 273 #define TTBCR_RGN_WBWA                  1
 274 #define TTBCR_RGN_WT                    2
 275 #define TTBCR_RGN_WB                    3
 276
 277 #define TTBCR_SL0_SHIFT                 6
 278 #define TTBCR_SL0_MASK                  0x3
 279 #define TTBCR_SL0_LVL_2                 0
 280 #define TTBCR_SL0_LVL_1                 1
 281
 282 #define TTBCR_T1SZ_SHIFT                16
 283 #define TTBCR_T0SZ_SHIFT                0
 284 #define TTBCR_SZ_MASK                   0xf
 285
 286 #define TTBCR2_SEP_SHIFT                15
 287 #define TTBCR2_SEP_MASK                 0x7
 288
 289 #define TTBCR2_PASIZE_SHIFT             0
 290 #define TTBCR2_PASIZE_MASK              0x7
 291
 292 /* Common definitions for PASize and SEP fields */
 293 #define TTBCR2_ADDR_32                  0
 294 #define TTBCR2_ADDR_36                  1
 295 #define TTBCR2_ADDR_40                  2
 296 #define TTBCR2_ADDR_42                  3
 297 #define TTBCR2_ADDR_44                  4
 298 #define TTBCR2_ADDR_48                  5
 299
 300 #define TTBRn_HI_ASID_SHIFT             16
 301
 302 #define MAIR_ATTR_SHIFT(n)              ((n) << 3)
 303 #define MAIR_ATTR_MASK                  0xff
 304 #define MAIR_ATTR_DEVICE                0x04
 305 #define MAIR_ATTR_NC                    0x44
 306 #define MAIR_ATTR_WBRWA                 0xff
 307 #define MAIR_ATTR_IDX_NC                0
 308 #define MAIR_ATTR_IDX_CACHE             1
 309 #define MAIR_ATTR_IDX_DEV               2
 310
 311 #define FSR_MULTI                       (1 << 31)
 312 #define FSR_SS                          (1 << 30)
 313 #define FSR_UUT                         (1 << 8)
 314 #define FSR_ASF                         (1 << 7)
 315 #define FSR_TLBLKF                      (1 << 6)
 316 #define FSR_TLBMCF                      (1 << 5)
 317 #define FSR_EF                          (1 << 4)
 318 #define FSR_PF                          (1 << 3)
 319 #define FSR_AFF                         (1 << 2)
 320 #define FSR_TF                          (1 << 1)
 321
 322 #define FSR_IGN                         (FSR_AFF | FSR_ASF | \
 323                                          FSR_TLBMCF | FSR_TLBLKF)
 324 #define FSR_FAULT                       (FSR_MULTI | FSR_SS | FSR_UUT | \
 325                                          FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
 326
 327 #define FSYNR0_WNR                      (1 << 4)
 328
 329 struct arm_smmu_smr {
 330         u8                              idx;
 331         u16                             mask;
 332         u16                             id;
 333 };
 334
 335 struct arm_smmu_master_cfg {
 336         int                             num_streamids;
 337         u16                             streamids[MAX_MASTER_STREAMIDS];
 338         struct arm_smmu_smr             *smrs;
 339 };
 340
 341 struct arm_smmu_master {
 342         struct device_node              *of_node;
 343         struct rb_node                  node;
 344         struct arm_smmu_master_cfg      cfg;
 345 };
 346
 347 struct arm_smmu_device {
 348         struct device                   *dev;
 349
 350         void __iomem                    *base;
 351         unsigned long                   size;
 352         unsigned long                   pagesize;
 353
 354 #define ARM_SMMU_FEAT_COHERENT_WALK     (1 << 0)
 355 #define ARM_SMMU_FEAT_STREAM_MATCH      (1 << 1)
 356 #define ARM_SMMU_FEAT_TRANS_S1          (1 << 2)
 357 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
 358 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
 359         u32                             features;
 360
 361 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
 362         u32                             options;
 363         int                             version;
 364
 365         u32                             num_context_banks;
 366         u32                             num_s2_context_banks;
 367         DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
 368         atomic_t                        irptndx;
 369
 370         u32                             num_mapping_groups;
 371         DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
 372
 373         unsigned long                   input_size;
 374         unsigned long                   s1_output_size;
 375         unsigned long                   s2_output_size;
 376
 377         u32                             num_global_irqs;
 378         u32                             num_context_irqs;
 379         unsigned int                    *irqs;
 380
 381         struct list_head                list;
 382         struct rb_root                  masters;
 383 };
 384
 385 struct arm_smmu_cfg {
 386         u8                              cbndx;
 387         u8                              irptndx;
 388         u32                             cbar;
 389         pgd_t                           *pgd;
 390 };
 391 #define INVALID_IRPTNDX                 0xff
 392
 393 #define ARM_SMMU_CB_ASID(cfg)           ((cfg)->cbndx)
 394 #define ARM_SMMU_CB_VMID(cfg)           ((cfg)->cbndx + 1)
 395
 396 struct arm_smmu_domain {
 397         struct arm_smmu_device          *smmu;
 398         struct arm_smmu_cfg             cfg;
 399         spinlock_t                      lock;
 400 };
 401
 402 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
 403 static LIST_HEAD(arm_smmu_devices);
 404
 405 struct arm_smmu_option_prop {
 406         u32 opt;
 407         const char *prop;
 408 };
 409
 410 static struct arm_smmu_option_prop arm_smmu_options[] = {
 411         { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
 412         { 0, NULL},
 413 };
 414
 415 static void parse_driver_options(struct arm_smmu_device *smmu)
 416 {
 417         int i = 0;
 418
 419         do {
 420                 if (of_property_read_bool(smmu->dev->of_node,
 421                                                 arm_smmu_options[i].prop)) {
 422                         smmu->options |= arm_smmu_options[i].opt;
 423                         dev_notice(smmu->dev, "option %s\n",
 424                                 arm_smmu_options[i].prop);
 425                 }
 426         } while (arm_smmu_options[++i].opt);
 427 }
 428
 429 static struct device *dev_get_master_dev(struct device *dev)
 430 {
 431         if (dev_is_pci(dev)) {
 432                 struct pci_bus *bus = to_pci_dev(dev)->bus;
 433
 434                 while (!pci_is_root_bus(bus))
 435                         bus = bus->parent;
 436                 return bus->bridge->parent;
 437         }
 438
 439         return dev;
 440 }
 441
 442 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
 443                                                 struct device_node *dev_node)
 444 {
 445         struct rb_node *node = smmu->masters.rb_node;
 446
 447         while (node) {
 448                 struct arm_smmu_master *master;
 449
 450                 master = container_of(node, struct arm_smmu_master, node);
 451
 452                 if (dev_node < master->of_node)
 453                         node = node->rb_left;
 454                 else if (dev_node > master->of_node)
 455                         node = node->rb_right;
 456                 else
 457                         return master;
 458         }
 459
 460         return NULL;
 461 }
 462
 463 static struct arm_smmu_master_cfg *
 464 find_smmu_master_cfg(struct arm_smmu_device *smmu, struct device *dev)
 465 {
 466         struct arm_smmu_master *master;
 467
 468         if (dev_is_pci(dev))
 469                 return dev->archdata.iommu;
 470
 471         master = find_smmu_master(smmu, dev->of_node);
 472         return master ? &master->cfg : NULL;
 473 }
 474
 475 static int insert_smmu_master(struct arm_smmu_device *smmu,
 476                               struct arm_smmu_master *master)
 477 {
 478         struct rb_node **new, *parent;
 479
 480         new = &smmu->masters.rb_node;
 481         parent = NULL;
 482         while (*new) {
 483                 struct arm_smmu_master *this
 484                         = container_of(*new, struct arm_smmu_master, node);
 485
 486                 parent = *new;
 487                 if (master->of_node < this->of_node)
 488                         new = &((*new)->rb_left);
 489                 else if (master->of_node > this->of_node)
 490                         new = &((*new)->rb_right);
 491                 else
 492                         return -EEXIST;
 493         }
 494
 495         rb_link_node(&master->node, parent, new);
 496         rb_insert_color(&master->node, &smmu->masters);
 497         return 0;
 498 }
 499
 500 static int register_smmu_master(struct arm_smmu_device *smmu,
 501                                 struct device *dev,
 502                                 struct of_phandle_args *masterspec)
 503 {
 504         int i;
 505         struct arm_smmu_master *master;
 506
 507         master = find_smmu_master(smmu, masterspec->np);
 508         if (master) {
 509                 dev_err(dev,
 510                         "rejecting multiple registrations for master device %s\n",
 511                         masterspec->np->name);
 512                 return -EBUSY;
 513         }
 514
 515         if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
 516                 dev_err(dev,
 517                         "reached maximum number (%d) of stream IDs for master device %s\n",
 518                         MAX_MASTER_STREAMIDS, masterspec->np->name);
 519                 return -ENOSPC;
 520         }
 521
 522         master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
 523         if (!master)
 524                 return -ENOMEM;
 525
 526         master->of_node                 = masterspec->np;
 527         master->cfg.num_streamids       = masterspec->args_count;
 528
 529         for (i = 0; i < master->cfg.num_streamids; ++i) {
 530                 u16 streamid = masterspec->args[i];
 531
 532                 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
 533                      (streamid >= smmu->num_mapping_groups)) {
 534                         dev_err(dev,
 535                                 "stream ID for master device %s greater than maximum allowed (%d)\n",
 536                                 masterspec->np->name, smmu->num_mapping_groups);
 537                         return -ERANGE;
 538                 }
 539                 master->cfg.streamids[i] = streamid;
 540         }
 541         return insert_smmu_master(smmu, master);
 542 }
 543
 544 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
 545 {
 546         struct arm_smmu_device *smmu;
 547         struct arm_smmu_master *master = NULL;
 548         struct device_node *dev_node = dev_get_master_dev(dev)->of_node;
 549
 550         spin_lock(&arm_smmu_devices_lock);
 551         list_for_each_entry(smmu, &arm_smmu_devices, list) {
 552                 master = find_smmu_master(smmu, dev_node);
 553                 if (master)
 554                         break;
 555         }
 556         spin_unlock(&arm_smmu_devices_lock);
 557
 558         return master ? smmu : NULL;
 559 }
 560
 561 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
 562 {
 563         int idx;
 564
 565         do {
 566                 idx = find_next_zero_bit(map, end, start);
 567                 if (idx == end)
 568                         return -ENOSPC;
 569         } while (test_and_set_bit(idx, map));
 570
 571         return idx;
 572 }
 573
 574 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
 575 {
 576         clear_bit(idx, map);
 577 }
 578
 579 /* Wait for any pending TLB invalidations to complete */
 580 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
 581 {
 582         int count = 0;
 583         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 584
 585         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
 586         while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
 587                & sTLBGSTATUS_GSACTIVE) {
 588                 cpu_relax();
 589                 if (++count == TLB_LOOP_TIMEOUT) {
 590                         dev_err_ratelimited(smmu->dev,
 591                         "TLB sync timed out -- SMMU may be deadlocked\n");
 592                         return;
 593                 }
 594                 udelay(1);
 595         }
 596 }
 597
 598 static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain)
 599 {
 600         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 601         struct arm_smmu_device *smmu = smmu_domain->smmu;
 602         void __iomem *base = ARM_SMMU_GR0(smmu);
 603         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 604
 605         if (stage1) {
 606                 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 607                 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
 608                                base + ARM_SMMU_CB_S1_TLBIASID);
 609         } else {
 610                 base = ARM_SMMU_GR0(smmu);
 611                 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
 612                                base + ARM_SMMU_GR0_TLBIVMID);
 613         }
 614
 615         arm_smmu_tlb_sync(smmu);
 616 }
 617
 618 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 619 {
 620         int flags, ret;
 621         u32 fsr, far, fsynr, resume;
 622         unsigned long iova;
 623         struct iommu_domain *domain = dev;
 624         struct arm_smmu_domain *smmu_domain = domain->priv;
 625         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 626         struct arm_smmu_device *smmu = smmu_domain->smmu;
 627         void __iomem *cb_base;
 628
 629         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 630         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
 631
 632         if (!(fsr & FSR_FAULT))
 633                 return IRQ_NONE;
 634
 635         if (fsr & FSR_IGN)
 636                 dev_err_ratelimited(smmu->dev,
 637                                     "Unexpected context fault (fsr 0x%x)\n",
 638                                     fsr);
 639
 640         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
 641         flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
 642
 643         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
 644         iova = far;
 645 #ifdef CONFIG_64BIT
 646         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
 647         iova |= ((unsigned long)far << 32);
 648 #endif
 649
 650         if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
 651                 ret = IRQ_HANDLED;
 652                 resume = RESUME_RETRY;
 653         } else {
 654                 dev_err_ratelimited(smmu->dev,
 655                     "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
 656                     iova, fsynr, cfg->cbndx);
 657                 ret = IRQ_NONE;
 658                 resume = RESUME_TERMINATE;
 659         }
 660
 661         /* Clear the faulting FSR */
 662         writel(fsr, cb_base + ARM_SMMU_CB_FSR);
 663
 664         /* Retry or terminate any stalled transactions */
 665         if (fsr & FSR_SS)
 666                 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
 667
 668         return ret;
 669 }
 670
 671 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
 672 {
 673         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
 674         struct arm_smmu_device *smmu = dev;
 675         void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
 676
 677         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
 678         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
 679         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
 680         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
 681
 682         if (!gfsr)
 683                 return IRQ_NONE;
 684
 685         dev_err_ratelimited(smmu->dev,
 686                 "Unexpected global fault, this could be serious\n");
 687         dev_err_ratelimited(smmu->dev,
 688                 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
 689                 gfsr, gfsynr0, gfsynr1, gfsynr2);
 690
 691         writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
 692         return IRQ_HANDLED;
 693 }
 694
 695 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
 696                                    size_t size)
 697 {
 698         unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
 699
 700
 701         /* Ensure new page tables are visible to the hardware walker */
 702         if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
 703                 dsb(ishst);
 704         } else {
 705                 /*
 706                  * If the SMMU can't walk tables in the CPU caches, treat them
 707                  * like non-coherent DMA since we need to flush the new entries
 708                  * all the way out to memory. There's no possibility of
 709                  * recursion here as the SMMU table walker will not be wired
 710                  * through another SMMU.
 711                  */
 712                 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
 713                                 DMA_TO_DEVICE);
 714         }
 715 }
 716
 717 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 718 {
 719         u32 reg;
 720         bool stage1;
 721         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 722         struct arm_smmu_device *smmu = smmu_domain->smmu;
 723         void __iomem *cb_base, *gr0_base, *gr1_base;
 724
 725         gr0_base = ARM_SMMU_GR0(smmu);
 726         gr1_base = ARM_SMMU_GR1(smmu);
 727         stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 728         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 729
 730         /* CBAR */
 731         reg = cfg->cbar;
 732         if (smmu->version == 1)
 733                 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
 734
 735         /*
 736          * Use the weakest shareability/memory types, so they are
 737          * overridden by the ttbcr/pte.
 738          */
 739         if (stage1) {
 740                 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
 741                         (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 742         } else {
 743                 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
 744         }
 745         writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
 746
 747         if (smmu->version > 1) {
 748                 /* CBA2R */
 749 #ifdef CONFIG_64BIT
 750                 reg = CBA2R_RW64_64BIT;
 751 #else
 752                 reg = CBA2R_RW64_32BIT;
 753 #endif
 754                 writel_relaxed(reg,
 755                                gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
 756
 757                 /* TTBCR2 */
 758                 switch (smmu->input_size) {
 759                 case 32:
 760                         reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
 761                         break;
 762                 case 36:
 763                         reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
 764                         break;
 765                 case 39:
 766                         reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
 767                         break;
 768                 case 42:
 769                         reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
 770                         break;
 771                 case 44:
 772                         reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
 773                         break;
 774                 case 48:
 775                         reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
 776                         break;
 777                 }
 778
 779                 switch (smmu->s1_output_size) {
 780                 case 32:
 781                         reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
 782                         break;
 783                 case 36:
 784                         reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
 785                         break;
 786                 case 39:
 787                         reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
 788                         break;
 789                 case 42:
 790                         reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
 791                         break;
 792                 case 44:
 793                         reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
 794                         break;
 795                 case 48:
 796                         reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
 797                         break;
 798                 }
 799
 800                 if (stage1)
 801                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
 802         }
 803
 804         /* TTBR0 */
 805         arm_smmu_flush_pgtable(smmu, cfg->pgd,
 806                                PTRS_PER_PGD * sizeof(pgd_t));
 807         reg = __pa(cfg->pgd);
 808         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
 809         reg = (phys_addr_t)__pa(cfg->pgd) >> 32;
 810         if (stage1)
 811                 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
 812         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
 813
 814         /*
 815          * TTBCR
 816          * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
 817          */
 818         if (smmu->version > 1) {
 819                 if (PAGE_SIZE == SZ_4K)
 820                         reg = TTBCR_TG0_4K;
 821                 else
 822                         reg = TTBCR_TG0_64K;
 823
 824                 if (!stage1) {
 825                         reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
 826
 827                         switch (smmu->s2_output_size) {
 828                         case 32:
 829                                 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
 830                                 break;
 831                         case 36:
 832                                 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
 833                                 break;
 834                         case 40:
 835                                 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
 836                                 break;
 837                         case 42:
 838                                 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
 839                                 break;
 840                         case 44:
 841                                 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
 842                                 break;
 843                         case 48:
 844                                 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
 845                                 break;
 846                         }
 847                 } else {
 848                         reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT;
 849                 }
 850         } else {
 851                 reg = 0;
 852         }
 853
 854         reg |= TTBCR_EAE |
 855               (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
 856               (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
 857               (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
 858
 859         if (!stage1)
 860                 reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
 861
 862         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 863
 864         /* MAIR0 (stage-1 only) */
 865         if (stage1) {
 866                 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
 867                       (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
 868                       (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
 869                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
 870         }
 871
 872         /* SCTLR */
 873         reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
 874         if (stage1)
 875                 reg |= SCTLR_S1_ASIDPNE;
 876 #ifdef __BIG_ENDIAN
 877         reg |= SCTLR_E;
 878 #endif
 879         writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
 880 }
 881
 882 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 883                                         struct arm_smmu_device *smmu)
 884 {
 885         int irq, start, ret = 0;
 886         unsigned long flags;
 887         struct arm_smmu_domain *smmu_domain = domain->priv;
 888         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 889
 890         spin_lock_irqsave(&smmu_domain->lock, flags);
 891         if (smmu_domain->smmu)
 892                 goto out_unlock;
 893
 894         if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
 895                 /*
 896                  * We will likely want to change this if/when KVM gets
 897                  * involved.
 898                  */
 899                 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 900                 start = smmu->num_s2_context_banks;
 901         } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) {
 902                 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 903                 start = smmu->num_s2_context_banks;
 904         } else {
 905                 cfg->cbar = CBAR_TYPE_S2_TRANS;
 906                 start = 0;
 907         }
 908
 909         ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
 910                                       smmu->num_context_banks);
 911         if (IS_ERR_VALUE(ret))
 912                 goto out_unlock;
 913
 914         cfg->cbndx = ret;
 915         if (smmu->version == 1) {
 916                 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
 917                 cfg->irptndx %= smmu->num_context_irqs;
 918         } else {
 919                 cfg->irptndx = cfg->cbndx;
 920         }
 921
 922         ACCESS_ONCE(smmu_domain->smmu) = smmu;
 923         arm_smmu_init_context_bank(smmu_domain);
 924         spin_unlock_irqrestore(&smmu_domain->lock, flags);
 925
 926         irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
 927         ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
 928                           "arm-smmu-context-fault", domain);
 929         if (IS_ERR_VALUE(ret)) {
 930                 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
 931                         cfg->irptndx, irq);
 932                 cfg->irptndx = INVALID_IRPTNDX;
 933         }
 934
 935         return 0;
 936
 937 out_unlock:
 938         spin_unlock_irqrestore(&smmu_domain->lock, flags);
 939         return ret;
 940 }
 941
 942 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
 943 {
 944         struct arm_smmu_domain *smmu_domain = domain->priv;
 945         struct arm_smmu_device *smmu = smmu_domain->smmu;
 946         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 947         void __iomem *cb_base;
 948         int irq;
 949
 950         if (!smmu)
 951                 return;
 952
 953         /* Disable the context bank and nuke the TLB before freeing it. */
 954         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 955         writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
 956         arm_smmu_tlb_inv_context(smmu_domain);
 957
 958         if (cfg->irptndx != INVALID_IRPTNDX) {
 959                 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
 960                 free_irq(irq, domain);
 961         }
 962
 963         __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
 964 }
 965
 966 static int arm_smmu_domain_init(struct iommu_domain *domain)
 967 {
 968         struct arm_smmu_domain *smmu_domain;
 969         pgd_t *pgd;
 970
 971         /*
 972          * Allocate the domain and initialise some of its data structures.
 973          * We can't really do anything meaningful until we've added a
 974          * master.
 975          */
 976         smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
 977         if (!smmu_domain)
 978                 return -ENOMEM;
 979
 980         pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
 981         if (!pgd)
 982                 goto out_free_domain;
 983         smmu_domain->cfg.pgd = pgd;
 984
 985         spin_lock_init(&smmu_domain->lock);
 986         domain->priv = smmu_domain;
 987         return 0;
 988
 989 out_free_domain:
 990         kfree(smmu_domain);
 991         return -ENOMEM;
 992 }
 993
 994 static void arm_smmu_free_ptes(pmd_t *pmd)
 995 {
 996         pgtable_t table = pmd_pgtable(*pmd);
 997
 998         __free_page(table);
 999 }
1000
1001 static void arm_smmu_free_pmds(pud_t *pud)
1002 {
1003         int i;
1004         pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
1005
1006         pmd = pmd_base;
1007         for (i = 0; i < PTRS_PER_PMD; ++i) {
1008                 if (pmd_none(*pmd))
1009                         continue;
1010
1011                 arm_smmu_free_ptes(pmd);
1012                 pmd++;
1013         }
1014
1015         pmd_free(NULL, pmd_base);
1016 }
1017
1018 static void arm_smmu_free_puds(pgd_t *pgd)
1019 {
1020         int i;
1021         pud_t *pud, *pud_base = pud_offset(pgd, 0);
1022
1023         pud = pud_base;
1024         for (i = 0; i < PTRS_PER_PUD; ++i) {
1025                 if (pud_none(*pud))
1026                         continue;
1027
1028                 arm_smmu_free_pmds(pud);
1029                 pud++;
1030         }
1031
1032         pud_free(NULL, pud_base);
1033 }
1034
1035 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
1036 {
1037         int i;
1038         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1039         pgd_t *pgd, *pgd_base = cfg->pgd;
1040
1041         /*
1042          * Recursively free the page tables for this domain. We don't
1043          * care about speculative TLB filling because the tables should
1044          * not be active in any context bank at this point (SCTLR.M is 0).
1045          */
1046         pgd = pgd_base;
1047         for (i = 0; i < PTRS_PER_PGD; ++i) {
1048                 if (pgd_none(*pgd))
1049                         continue;
1050                 arm_smmu_free_puds(pgd);
1051                 pgd++;
1052         }
1053
1054         kfree(pgd_base);
1055 }
1056
1057 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1058 {
1059         struct arm_smmu_domain *smmu_domain = domain->priv;
1060
1061         /*
1062          * Free the domain resources. We assume that all devices have
1063          * already been detached.
1064          */
1065         arm_smmu_destroy_domain_context(domain);
1066         arm_smmu_free_pgtables(smmu_domain);
1067         kfree(smmu_domain);
1068 }
1069
1070 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1071                                           struct arm_smmu_master_cfg *cfg)
1072 {
1073         int i;
1074         struct arm_smmu_smr *smrs;
1075         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1076
1077         if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1078                 return 0;
1079
1080         if (cfg->smrs)
1081                 return -EEXIST;
1082
1083         smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1084         if (!smrs) {
1085                 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1086                         cfg->num_streamids);
1087                 return -ENOMEM;
1088         }
1089
1090         /* Allocate the SMRs on the SMMU */
1091         for (i = 0; i < cfg->num_streamids; ++i) {
1092                 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1093                                                   smmu->num_mapping_groups);
1094                 if (IS_ERR_VALUE(idx)) {
1095                         dev_err(smmu->dev, "failed to allocate free SMR\n");
1096                         goto err_free_smrs;
1097                 }
1098
1099                 smrs[i] = (struct arm_smmu_smr) {
1100                         .idx    = idx,
1101                         .mask   = 0, /* We don't currently share SMRs */
1102                         .id     = cfg->streamids[i],
1103                 };
1104         }
1105
1106         /* It worked! Now, poke the actual hardware */
1107         for (i = 0; i < cfg->num_streamids; ++i) {
1108                 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1109                           smrs[i].mask << SMR_MASK_SHIFT;
1110                 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1111         }
1112
1113         cfg->smrs = smrs;
1114         return 0;
1115
1116 err_free_smrs:
1117         while (--i >= 0)
1118                 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1119         kfree(smrs);
1120         return -ENOSPC;
1121 }
1122
1123 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1124                                       struct arm_smmu_master_cfg *cfg)
1125 {
1126         int i;
1127         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1128         struct arm_smmu_smr *smrs = cfg->smrs;
1129
1130         if (!smrs)
1131                 return;
1132
1133         /* Invalidate the SMRs before freeing back to the allocator */
1134         for (i = 0; i < cfg->num_streamids; ++i) {
1135                 u8 idx = smrs[i].idx;
1136
1137                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1138                 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1139         }
1140
1141         cfg->smrs = NULL;
1142         kfree(smrs);
1143 }
1144
1145 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1146                                       struct arm_smmu_master_cfg *cfg)
1147 {
1148         int i, ret;
1149         struct arm_smmu_device *smmu = smmu_domain->smmu;
1150         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1151
1152         ret = arm_smmu_master_configure_smrs(smmu, cfg);
1153         if (ret)
1154                 return ret;
1155
1156         for (i = 0; i < cfg->num_streamids; ++i) {
1157                 u32 idx, s2cr;
1158
1159                 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1160                 s2cr = S2CR_TYPE_TRANS |
1161                        (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1162                 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1163         }
1164
1165         return 0;
1166 }
1167
1168 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1169                                           struct arm_smmu_master_cfg *cfg)
1170 {
1171         int i;
1172         struct arm_smmu_device *smmu = smmu_domain->smmu;
1173         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1174
1175         /*
1176          * We *must* clear the S2CR first, because freeing the SMR means
1177          * that it can be re-allocated immediately.
1178          */
1179         for (i = 0; i < cfg->num_streamids; ++i) {
1180                 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1181
1182                 writel_relaxed(S2CR_TYPE_BYPASS,
1183                                gr0_base + ARM_SMMU_GR0_S2CR(idx));
1184         }
1185
1186         arm_smmu_master_free_smrs(smmu, cfg);
1187 }
1188
1189 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1190 {
1191         int ret;
1192         struct arm_smmu_domain *smmu_domain = domain->priv;
1193         struct arm_smmu_device *smmu, *dom_smmu;
1194         struct arm_smmu_master_cfg *cfg;
1195
1196         smmu = dev_get_master_dev(dev)->archdata.iommu;
1197         if (!smmu) {
1198                 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1199                 return -ENXIO;
1200         }
1201
1202         /*
1203          * Sanity check the domain. We don't support domains across
1204          * different SMMUs.
1205          */
1206         dom_smmu = ACCESS_ONCE(smmu_domain->smmu);
1207         if (!dom_smmu) {
1208                 /* Now that we have a master, we can finalise the domain */
1209                 ret = arm_smmu_init_domain_context(domain, smmu);
1210                 if (IS_ERR_VALUE(ret))
1211                         return ret;
1212
1213                 dom_smmu = smmu_domain->smmu;
1214         }
1215
1216         if (dom_smmu != smmu) {
1217                 dev_err(dev,
1218                         "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1219                         dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1220                 return -EINVAL;
1221         }
1222
1223         /* Looks ok, so add the device to the domain */
1224         cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
1225         if (!cfg)
1226                 return -ENODEV;
1227
1228         return arm_smmu_domain_add_master(smmu_domain, cfg);
1229 }
1230
1231 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1232 {
1233         struct arm_smmu_domain *smmu_domain = domain->priv;
1234         struct arm_smmu_master_cfg *cfg;
1235
1236         cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
1237         if (cfg)
1238                 arm_smmu_domain_remove_master(smmu_domain, cfg);
1239 }
1240
1241 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1242                                              unsigned long end)
1243 {
1244         return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1245                 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1246 }
1247
1248 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1249                                    unsigned long addr, unsigned long end,
1250                                    unsigned long pfn, int prot, int stage)
1251 {
1252         pte_t *pte, *start;
1253         pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
1254
1255         if (pmd_none(*pmd)) {
1256                 /* Allocate a new set of tables */
1257                 pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
1258
1259                 if (!table)
1260                         return -ENOMEM;
1261
1262                 arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
1263                 pmd_populate(NULL, pmd, table);
1264                 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1265         }
1266
1267         if (stage == 1) {
1268                 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1269                 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
1270                         pteval |= ARM_SMMU_PTE_AP_RDONLY;
1271
1272                 if (prot & IOMMU_CACHE)
1273                         pteval |= (MAIR_ATTR_IDX_CACHE <<
1274                                    ARM_SMMU_PTE_ATTRINDX_SHIFT);
1275         } else {
1276                 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1277                 if (prot & IOMMU_READ)
1278                         pteval |= ARM_SMMU_PTE_HAP_READ;
1279                 if (prot & IOMMU_WRITE)
1280                         pteval |= ARM_SMMU_PTE_HAP_WRITE;
1281                 if (prot & IOMMU_CACHE)
1282                         pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1283                 else
1284                         pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1285         }
1286
1287         /* If no access, create a faulting entry to avoid TLB fills */
1288         if (prot & IOMMU_EXEC)
1289                 pteval &= ~ARM_SMMU_PTE_XN;
1290         else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
1291                 pteval &= ~ARM_SMMU_PTE_PAGE;
1292
1293         pteval |= ARM_SMMU_PTE_SH_IS;
1294         start = pmd_page_vaddr(*pmd) + pte_index(addr);
1295         pte = start;
1296
1297         /*
1298          * Install the page table entries. This is fairly complicated
1299          * since we attempt to make use of the contiguous hint in the
1300          * ptes where possible. The contiguous hint indicates a series
1301          * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1302          * contiguous region with the following constraints:
1303          *
1304          *   - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1305          *   - Each pte in the region has the contiguous hint bit set
1306          *
1307          * This complicates unmapping (also handled by this code, when
1308          * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1309          * possible, yet highly unlikely, that a client may unmap only
1310          * part of a contiguous range. This requires clearing of the
1311          * contiguous hint bits in the range before installing the new
1312          * faulting entries.
1313          *
1314          * Note that re-mapping an address range without first unmapping
1315          * it is not supported, so TLB invalidation is not required here
1316          * and is instead performed at unmap and domain-init time.
1317          */
1318         do {
1319                 int i = 1;
1320
1321                 pteval &= ~ARM_SMMU_PTE_CONT;
1322
1323                 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1324                         i = ARM_SMMU_PTE_CONT_ENTRIES;
1325                         pteval |= ARM_SMMU_PTE_CONT;
1326                 } else if (pte_val(*pte) &
1327                            (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1328                         int j;
1329                         pte_t *cont_start;
1330                         unsigned long idx = pte_index(addr);
1331
1332                         idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1333                         cont_start = pmd_page_vaddr(*pmd) + idx;
1334                         for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1335                                 pte_val(*(cont_start + j)) &=
1336                                         ~ARM_SMMU_PTE_CONT;
1337
1338                         arm_smmu_flush_pgtable(smmu, cont_start,
1339                                                sizeof(*pte) *
1340                                                ARM_SMMU_PTE_CONT_ENTRIES);
1341                 }
1342
1343                 do {
1344                         *pte = pfn_pte(pfn, __pgprot(pteval));
1345                 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1346         } while (addr != end);
1347
1348         arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1349         return 0;
1350 }
1351
1352 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1353                                    unsigned long addr, unsigned long end,
1354                                    phys_addr_t phys, int prot, int stage)
1355 {
1356         int ret;
1357         pmd_t *pmd;
1358         unsigned long next, pfn = __phys_to_pfn(phys);
1359
1360 #ifndef __PAGETABLE_PMD_FOLDED
1361         if (pud_none(*pud)) {
1362                 pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
1363                 if (!pmd)
1364                         return -ENOMEM;
1365
1366                 arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE);
1367                 pud_populate(NULL, pud, pmd);
1368                 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1369
1370                 pmd += pmd_index(addr);
1371         } else
1372 #endif
1373                 pmd = pmd_offset(pud, addr);
1374
1375         do {
1376                 next = pmd_addr_end(addr, end);
1377                 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn,
1378                                               prot, stage);
1379                 phys += next - addr;
1380         } while (pmd++, addr = next, addr < end);
1381
1382         return ret;
1383 }
1384
1385 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1386                                    unsigned long addr, unsigned long end,
1387                                    phys_addr_t phys, int prot, int stage)
1388 {
1389         int ret = 0;
1390         pud_t *pud;
1391         unsigned long next;
1392
1393 #ifndef __PAGETABLE_PUD_FOLDED
1394         if (pgd_none(*pgd)) {
1395                 pud = (pud_t *)get_zeroed_page(GFP_ATOMIC);
1396                 if (!pud)
1397                         return -ENOMEM;
1398
1399                 arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE);
1400                 pgd_populate(NULL, pgd, pud);
1401                 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1402
1403                 pud += pud_index(addr);
1404         } else
1405 #endif
1406                 pud = pud_offset(pgd, addr);
1407
1408         do {
1409                 next = pud_addr_end(addr, end);
1410                 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1411                                               prot, stage);
1412                 phys += next - addr;
1413         } while (pud++, addr = next, addr < end);
1414
1415         return ret;
1416 }
1417
1418 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1419                                    unsigned long iova, phys_addr_t paddr,
1420                                    size_t size, int prot)
1421 {
1422         int ret, stage;
1423         unsigned long end;
1424         phys_addr_t input_mask, output_mask;
1425         struct arm_smmu_device *smmu = smmu_domain->smmu;
1426         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1427         pgd_t *pgd = cfg->pgd;
1428         unsigned long flags;
1429
1430         if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
1431                 stage = 2;
1432                 output_mask = (1ULL << smmu->s2_output_size) - 1;
1433         } else {
1434                 stage = 1;
1435                 output_mask = (1ULL << smmu->s1_output_size) - 1;
1436         }
1437
1438         if (!pgd)
1439                 return -EINVAL;
1440
1441         if (size & ~PAGE_MASK)
1442                 return -EINVAL;
1443
1444         input_mask = (1ULL << smmu->input_size) - 1;
1445         if ((phys_addr_t)iova & ~input_mask)
1446                 return -ERANGE;
1447
1448         if (paddr & ~output_mask)
1449                 return -ERANGE;
1450
1451         spin_lock_irqsave(&smmu_domain->lock, flags);
1452         pgd += pgd_index(iova);
1453         end = iova + size;
1454         do {
1455                 unsigned long next = pgd_addr_end(iova, end);
1456
1457                 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1458                                               prot, stage);
1459                 if (ret)
1460                         goto out_unlock;
1461
1462                 paddr += next - iova;
1463                 iova = next;
1464         } while (pgd++, iova != end);
1465
1466 out_unlock:
1467         spin_unlock_irqrestore(&smmu_domain->lock, flags);
1468
1469         return ret;
1470 }
1471
1472 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1473                         phys_addr_t paddr, size_t size, int prot)
1474 {
1475         struct arm_smmu_domain *smmu_domain = domain->priv;
1476
1477         if (!smmu_domain)
1478                 return -ENODEV;
1479
1480         return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
1481 }
1482
1483 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1484                              size_t size)
1485 {
1486         int ret;
1487         struct arm_smmu_domain *smmu_domain = domain->priv;
1488
1489         ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1490         arm_smmu_tlb_inv_context(smmu_domain);
1491         return ret ? 0 : size;
1492 }
1493
1494 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1495                                          dma_addr_t iova)
1496 {
1497         pgd_t *pgdp, pgd;
1498         pud_t pud;
1499         pmd_t pmd;
1500         pte_t pte;
1501         struct arm_smmu_domain *smmu_domain = domain->priv;
1502         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1503
1504         pgdp = cfg->pgd;
1505         if (!pgdp)
1506                 return 0;
1507
1508         pgd = *(pgdp + pgd_index(iova));
1509         if (pgd_none(pgd))
1510                 return 0;
1511
1512         pud = *pud_offset(&pgd, iova);
1513         if (pud_none(pud))
1514                 return 0;
1515
1516         pmd = *pmd_offset(&pud, iova);
1517         if (pmd_none(pmd))
1518                 return 0;
1519
1520         pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1521         if (pte_none(pte))
1522                 return 0;
1523
1524         return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1525 }
1526
1527 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1528                                    unsigned long cap)
1529 {
1530         struct arm_smmu_domain *smmu_domain = domain->priv;
1531         struct arm_smmu_device *smmu = smmu_domain->smmu;
1532         u32 features = smmu ? smmu->features : 0;
1533
1534         switch (cap) {
1535         case IOMMU_CAP_CACHE_COHERENCY:
1536                 return features & ARM_SMMU_FEAT_COHERENT_WALK;
1537         case IOMMU_CAP_INTR_REMAP:
1538                 return 1; /* MSIs are just memory writes */
1539         default:
1540                 return 0;
1541         }
1542 }
1543
1544 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1545 {
1546         *((u16 *)data) = alias;
1547         return 0; /* Continue walking */
1548 }
1549
1550 static int arm_smmu_add_device(struct device *dev)
1551 {
1552         struct arm_smmu_device *smmu;
1553         struct iommu_group *group;
1554         int ret;
1555
1556         if (dev->archdata.iommu) {
1557                 dev_warn(dev, "IOMMU driver already assigned to device\n");
1558                 return -EINVAL;
1559         }
1560
1561         smmu = find_smmu_for_device(dev);
1562         if (!smmu)
1563                 return -ENODEV;
1564
1565         group = iommu_group_alloc();
1566         if (IS_ERR(group)) {
1567                 dev_err(dev, "Failed to allocate IOMMU group\n");
1568                 return PTR_ERR(group);
1569         }
1570
1571         if (dev_is_pci(dev)) {
1572                 struct arm_smmu_master_cfg *cfg;
1573                 struct pci_dev *pdev = to_pci_dev(dev);
1574
1575                 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1576                 if (!cfg) {
1577                         ret = -ENOMEM;
1578                         goto out_put_group;
1579                 }
1580
1581                 cfg->num_streamids = 1;
1582                 /*
1583                  * Assume Stream ID == Requester ID for now.
1584                  * We need a way to describe the ID mappings in FDT.
1585                  */
1586                 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid,
1587                                        &cfg->streamids[0]);
1588                 dev->archdata.iommu = cfg;
1589         } else {
1590                 dev->archdata.iommu = smmu;
1591         }
1592
1593         ret = iommu_group_add_device(group, dev);
1594
1595 out_put_group:
1596         iommu_group_put(group);
1597         return ret;
1598 }
1599
1600 static void arm_smmu_remove_device(struct device *dev)
1601 {
1602         if (dev_is_pci(dev))
1603                 kfree(dev->archdata.iommu);
1604
1605         dev->archdata.iommu = NULL;
1606         iommu_group_remove_device(dev);
1607 }
1608
1609 static const struct iommu_ops arm_smmu_ops = {
1610         .domain_init    = arm_smmu_domain_init,
1611         .domain_destroy = arm_smmu_domain_destroy,
1612         .attach_dev     = arm_smmu_attach_dev,
1613         .detach_dev     = arm_smmu_detach_dev,
1614         .map            = arm_smmu_map,
1615         .unmap          = arm_smmu_unmap,
1616         .iova_to_phys   = arm_smmu_iova_to_phys,
1617         .domain_has_cap = arm_smmu_domain_has_cap,
1618         .add_device     = arm_smmu_add_device,
1619         .remove_device  = arm_smmu_remove_device,
1620         .pgsize_bitmap  = (SECTION_SIZE |
1621                            ARM_SMMU_PTE_CONT_SIZE |
1622                            PAGE_SIZE),
1623 };
1624
1625 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1626 {
1627         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1628         void __iomem *cb_base;
1629         int i = 0;
1630         u32 reg;
1631
1632         /* clear global FSR */
1633         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1634         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1635
1636         /* Mark all SMRn as invalid and all S2CRn as bypass */
1637         for (i = 0; i < smmu->num_mapping_groups; ++i) {
1638                 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
1639                 writel_relaxed(S2CR_TYPE_BYPASS,
1640                         gr0_base + ARM_SMMU_GR0_S2CR(i));
1641         }
1642
1643         /* Make sure all context banks are disabled and clear CB_FSR  */
1644         for (i = 0; i < smmu->num_context_banks; ++i) {
1645                 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1646                 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1647                 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1648         }
1649
1650         /* Invalidate the TLB, just in case */
1651         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1652         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1653         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1654
1655         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1656
1657         /* Enable fault reporting */
1658         reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1659
1660         /* Disable TLB broadcasting. */
1661         reg |= (sCR0_VMIDPNE | sCR0_PTM);
1662
1663         /* Enable client access, but bypass when no mapping is found */
1664         reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1665
1666         /* Disable forced broadcasting */
1667         reg &= ~sCR0_FB;
1668
1669         /* Don't upgrade barriers */
1670         reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1671
1672         /* Push the button */
1673         arm_smmu_tlb_sync(smmu);
1674         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1675 }
1676
1677 static int arm_smmu_id_size_to_bits(int size)
1678 {
1679         switch (size) {
1680         case 0:
1681                 return 32;
1682         case 1:
1683                 return 36;
1684         case 2:
1685                 return 40;
1686         case 3:
1687                 return 42;
1688         case 4:
1689                 return 44;
1690         case 5:
1691         default:
1692                 return 48;
1693         }
1694 }
1695
1696 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1697 {
1698         unsigned long size;
1699         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1700         u32 id;
1701
1702         dev_notice(smmu->dev, "probing hardware configuration...\n");
1703
1704         /* Primecell ID */
1705         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1706         smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1707         dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1708
1709         /* ID0 */
1710         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1711 #ifndef CONFIG_64BIT
1712         if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1713                 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1714                 return -ENODEV;
1715         }
1716 #endif
1717         if (id & ID0_S1TS) {
1718                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1719                 dev_notice(smmu->dev, "\tstage 1 translation\n");
1720         }
1721
1722         if (id & ID0_S2TS) {
1723                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1724                 dev_notice(smmu->dev, "\tstage 2 translation\n");
1725         }
1726
1727         if (id & ID0_NTS) {
1728                 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1729                 dev_notice(smmu->dev, "\tnested translation\n");
1730         }
1731
1732         if (!(smmu->features &
1733                 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1734                  ARM_SMMU_FEAT_TRANS_NESTED))) {
1735                 dev_err(smmu->dev, "\tno translation support!\n");
1736                 return -ENODEV;
1737         }
1738
1739         if (id & ID0_CTTW) {
1740                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1741                 dev_notice(smmu->dev, "\tcoherent table walk\n");
1742         }
1743
1744         if (id & ID0_SMS) {
1745                 u32 smr, sid, mask;
1746
1747                 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1748                 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1749                                            ID0_NUMSMRG_MASK;
1750                 if (smmu->num_mapping_groups == 0) {
1751                         dev_err(smmu->dev,
1752                                 "stream-matching supported, but no SMRs present!\n");
1753                         return -ENODEV;
1754                 }
1755
1756                 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1757                 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1758                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1759                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1760
1761                 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1762                 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1763                 if ((mask & sid) != sid) {
1764                         dev_err(smmu->dev,
1765                                 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1766                                 mask, sid);
1767                         return -ENODEV;
1768                 }
1769
1770                 dev_notice(smmu->dev,
1771                            "\tstream matching with %u register groups, mask 0x%x",
1772                            smmu->num_mapping_groups, mask);
1773         } else {
1774                 smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
1775                                            ID0_NUMSIDB_MASK;
1776         }
1777
1778         /* ID1 */
1779         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1780         smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1781
1782         /* Check for size mismatch of SMMU address space from mapped region */
1783         size = 1 <<
1784                 (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1785         size *= (smmu->pagesize << 1);
1786         if (smmu->size != size)
1787                 dev_warn(smmu->dev,
1788                         "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1789                         size, smmu->size);
1790
1791         smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1792                                       ID1_NUMS2CB_MASK;
1793         smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1794         if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1795                 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1796                 return -ENODEV;
1797         }
1798         dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1799                    smmu->num_context_banks, smmu->num_s2_context_banks);
1800
1801         /* ID2 */
1802         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1803         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1804
1805         /*
1806          * Stage-1 output limited by stage-2 input size due to pgd
1807          * allocation (PTRS_PER_PGD).
1808          */
1809 #ifdef CONFIG_64BIT
1810         smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
1811 #else
1812         smmu->s1_output_size = min(32UL, size);
1813 #endif
1814
1815         /* The stage-2 output mask is also applied for bypass */
1816         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1817         smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
1818
1819         if (smmu->version == 1) {
1820                 smmu->input_size = 32;
1821         } else {
1822 #ifdef CONFIG_64BIT
1823                 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1824                 size = min(VA_BITS, arm_smmu_id_size_to_bits(size));
1825 #else
1826                 size = 32;
1827 #endif
1828                 smmu->input_size = size;
1829
1830                 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1831                     (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1832                     (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1833                         dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1834                                 PAGE_SIZE);
1835                         return -ENODEV;
1836                 }
1837         }
1838
1839         dev_notice(smmu->dev,
1840                    "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1841                    smmu->input_size, smmu->s1_output_size,
1842                    smmu->s2_output_size);
1843         return 0;
1844 }
1845
1846 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1847 {
1848         struct resource *res;
1849         struct arm_smmu_device *smmu;
1850         struct device *dev = &pdev->dev;
1851         struct rb_node *node;
1852         struct of_phandle_args masterspec;
1853         int num_irqs, i, err;
1854
1855         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1856         if (!smmu) {
1857                 dev_err(dev, "failed to allocate arm_smmu_device\n");
1858                 return -ENOMEM;
1859         }
1860         smmu->dev = dev;
1861
1862         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1863         smmu->base = devm_ioremap_resource(dev, res);
1864         if (IS_ERR(smmu->base))
1865                 return PTR_ERR(smmu->base);
1866         smmu->size = resource_size(res);
1867
1868         if (of_property_read_u32(dev->of_node, "#global-interrupts",
1869                                  &smmu->num_global_irqs)) {
1870                 dev_err(dev, "missing #global-interrupts property\n");
1871                 return -ENODEV;
1872         }
1873
1874         num_irqs = 0;
1875         while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1876                 num_irqs++;
1877                 if (num_irqs > smmu->num_global_irqs)
1878                         smmu->num_context_irqs++;
1879         }
1880
1881         if (!smmu->num_context_irqs) {
1882                 dev_err(dev, "found %d interrupts but expected at least %d\n",
1883                         num_irqs, smmu->num_global_irqs + 1);
1884                 return -ENODEV;
1885         }
1886
1887         smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1888                                   GFP_KERNEL);
1889         if (!smmu->irqs) {
1890                 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1891                 return -ENOMEM;
1892         }
1893
1894         for (i = 0; i < num_irqs; ++i) {
1895                 int irq = platform_get_irq(pdev, i);
1896
1897                 if (irq < 0) {
1898                         dev_err(dev, "failed to get irq index %d\n", i);
1899                         return -ENODEV;
1900                 }
1901                 smmu->irqs[i] = irq;
1902         }
1903
1904         err = arm_smmu_device_cfg_probe(smmu);
1905         if (err)
1906                 return err;
1907
1908         i = 0;
1909         smmu->masters = RB_ROOT;
1910         while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1911                                            "#stream-id-cells", i,
1912                                            &masterspec)) {
1913                 err = register_smmu_master(smmu, dev, &masterspec);
1914                 if (err) {
1915                         dev_err(dev, "failed to add master %s\n",
1916                                 masterspec.np->name);
1917                         goto out_put_masters;
1918                 }
1919
1920                 i++;
1921         }
1922         dev_notice(dev, "registered %d master devices\n", i);
1923
1924         parse_driver_options(smmu);
1925
1926         if (smmu->version > 1 &&
1927             smmu->num_context_banks != smmu->num_context_irqs) {
1928                 dev_err(dev,
1929                         "found only %d context interrupt(s) but %d required\n",
1930                         smmu->num_context_irqs, smmu->num_context_banks);
1931                 err = -ENODEV;
1932                 goto out_put_masters;
1933         }
1934
1935         for (i = 0; i < smmu->num_global_irqs; ++i) {
1936                 err = request_irq(smmu->irqs[i],
1937                                   arm_smmu_global_fault,
1938                                   IRQF_SHARED,
1939                                   "arm-smmu global fault",
1940                                   smmu);
1941                 if (err) {
1942                         dev_err(dev, "failed to request global IRQ %d (%u)\n",
1943                                 i, smmu->irqs[i]);
1944                         goto out_free_irqs;
1945                 }
1946         }
1947
1948         INIT_LIST_HEAD(&smmu->list);
1949         spin_lock(&arm_smmu_devices_lock);
1950         list_add(&smmu->list, &arm_smmu_devices);
1951         spin_unlock(&arm_smmu_devices_lock);
1952
1953         arm_smmu_device_reset(smmu);
1954         return 0;
1955
1956 out_free_irqs:
1957         while (i--)
1958                 free_irq(smmu->irqs[i], smmu);
1959
1960 out_put_masters:
1961         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1962                 struct arm_smmu_master *master
1963                         = container_of(node, struct arm_smmu_master, node);
1964                 of_node_put(master->of_node);
1965         }
1966
1967         return err;
1968 }
1969
1970 static int arm_smmu_device_remove(struct platform_device *pdev)
1971 {
1972         int i;
1973         struct device *dev = &pdev->dev;
1974         struct arm_smmu_device *curr, *smmu = NULL;
1975         struct rb_node *node;
1976
1977         spin_lock(&arm_smmu_devices_lock);
1978         list_for_each_entry(curr, &arm_smmu_devices, list) {
1979                 if (curr->dev == dev) {
1980                         smmu = curr;
1981                         list_del(&smmu->list);
1982                         break;
1983                 }
1984         }
1985         spin_unlock(&arm_smmu_devices_lock);
1986
1987         if (!smmu)
1988                 return -ENODEV;
1989
1990         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1991                 struct arm_smmu_master *master
1992                         = container_of(node, struct arm_smmu_master, node);
1993                 of_node_put(master->of_node);
1994         }
1995
1996         if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1997                 dev_err(dev, "removing device with active domains!\n");
1998
1999         for (i = 0; i < smmu->num_global_irqs; ++i)
2000                 free_irq(smmu->irqs[i], smmu);
2001
2002         /* Turn the thing off */
2003         writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
2004         return 0;
2005 }
2006
2007 #ifdef CONFIG_OF
2008 static struct of_device_id arm_smmu_of_match[] = {
2009         { .compatible = "arm,smmu-v1", },
2010         { .compatible = "arm,smmu-v2", },
2011         { .compatible = "arm,mmu-400", },
2012         { .compatible = "arm,mmu-500", },
2013         { },
2014 };
2015 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
2016 #endif
2017
2018 static struct platform_driver arm_smmu_driver = {
2019         .driver = {
2020                 .owner          = THIS_MODULE,
2021                 .name           = "arm-smmu",
2022                 .of_match_table = of_match_ptr(arm_smmu_of_match),
2023         },
2024         .probe  = arm_smmu_device_dt_probe,
2025         .remove = arm_smmu_device_remove,
2026 };
2027
2028 static int __init arm_smmu_init(void)
2029 {
2030         int ret;
2031
2032         ret = platform_driver_register(&arm_smmu_driver);
2033         if (ret)
2034                 return ret;
2035
2036         /* Oh, for a proper bus abstraction */
2037         if (!iommu_present(&platform_bus_type))
2038                 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2039
2040 #ifdef CONFIG_ARM_AMBA
2041         if (!iommu_present(&amba_bustype))
2042                 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2043 #endif
2044
2045 #ifdef CONFIG_PCI
2046         if (!iommu_present(&pci_bus_type))
2047                 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2048 #endif
2049
2050         return 0;
2051 }
2052
2053 static void __exit arm_smmu_exit(void)
2054 {
2055         return platform_driver_unregister(&arm_smmu_driver);
2056 }
2057
2058 subsys_initcall(arm_smmu_init);
2059 module_exit(arm_smmu_exit);
2060
2061 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2062 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2063 MODULE_LICENSE("GPL v2");