drivers/iommu/arm-smmu.c

   1 /*
   2  * IOMMU API for ARM architected SMMU implementations.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16  *
  17  * Copyright (C) 2013 ARM Limited
  18  *
  19  * Author: Will Deacon <will.deacon@arm.com>
  20  *
  21  * This driver currently supports:
  22  *      - SMMUv1 and v2 implementations
  23  *      - Stream-matching and stream-indexing
  24  *      - v7/v8 long-descriptor format
  25  *      - Non-secure access to the SMMU
  26  *      - 4k and 64k pages, with contiguous pte hints.
  27  *      - Up to 42-bit addressing (dependent on VA_BITS)
  28  *      - Context fault reporting
  29  */
  30
  31 #define pr_fmt(fmt) "arm-smmu: " fmt
  32
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/err.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/io.h>
  38 #include <linux/iommu.h>
  39 #include <linux/mm.h>
  40 #include <linux/module.h>
  41 #include <linux/of.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/slab.h>
  44 #include <linux/spinlock.h>
  45
  46 #include <linux/amba/bus.h>
  47
  48 #include <asm/pgalloc.h>
  49
  50 /* Maximum number of stream IDs assigned to a single device */
  51 #define MAX_MASTER_STREAMIDS            MAX_PHANDLE_ARGS
  52
  53 /* Maximum number of context banks per SMMU */
  54 #define ARM_SMMU_MAX_CBS                128
  55
  56 /* Maximum number of mapping groups per SMMU */
  57 #define ARM_SMMU_MAX_SMRS               128
  58
  59 /* SMMU global address space */
  60 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
  61 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (smmu)->pagesize)
  62
  63 /*
  64  * SMMU global address space with conditional offset to access secure
  65  * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
  66  * nsGFSYNR0: 0x450)
  67  */
  68 #define ARM_SMMU_GR0_NS(smmu)                                           \
  69         ((smmu)->base +                                                 \
  70                 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)       \
  71                         ? 0x400 : 0))
  72
  73 /* Page table bits */
  74 #define ARM_SMMU_PTE_XN                 (((pteval_t)3) << 53)
  75 #define ARM_SMMU_PTE_CONT               (((pteval_t)1) << 52)
  76 #define ARM_SMMU_PTE_AF                 (((pteval_t)1) << 10)
  77 #define ARM_SMMU_PTE_SH_NS              (((pteval_t)0) << 8)
  78 #define ARM_SMMU_PTE_SH_OS              (((pteval_t)2) << 8)
  79 #define ARM_SMMU_PTE_SH_IS              (((pteval_t)3) << 8)
  80 #define ARM_SMMU_PTE_PAGE               (((pteval_t)3) << 0)
  81
  82 #if PAGE_SIZE == SZ_4K
  83 #define ARM_SMMU_PTE_CONT_ENTRIES       16
  84 #elif PAGE_SIZE == SZ_64K
  85 #define ARM_SMMU_PTE_CONT_ENTRIES       32
  86 #else
  87 #define ARM_SMMU_PTE_CONT_ENTRIES       1
  88 #endif
  89
  90 #define ARM_SMMU_PTE_CONT_SIZE          (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
  91 #define ARM_SMMU_PTE_CONT_MASK          (~(ARM_SMMU_PTE_CONT_SIZE - 1))
  92
  93 /* Stage-1 PTE */
  94 #define ARM_SMMU_PTE_AP_UNPRIV          (((pteval_t)1) << 6)
  95 #define ARM_SMMU_PTE_AP_RDONLY          (((pteval_t)2) << 6)
  96 #define ARM_SMMU_PTE_ATTRINDX_SHIFT     2
  97 #define ARM_SMMU_PTE_nG                 (((pteval_t)1) << 11)
  98
  99 /* Stage-2 PTE */
 100 #define ARM_SMMU_PTE_HAP_FAULT          (((pteval_t)0) << 6)
 101 #define ARM_SMMU_PTE_HAP_READ           (((pteval_t)1) << 6)
 102 #define ARM_SMMU_PTE_HAP_WRITE          (((pteval_t)2) << 6)
 103 #define ARM_SMMU_PTE_MEMATTR_OIWB       (((pteval_t)0xf) << 2)
 104 #define ARM_SMMU_PTE_MEMATTR_NC         (((pteval_t)0x5) << 2)
 105 #define ARM_SMMU_PTE_MEMATTR_DEV        (((pteval_t)0x1) << 2)
 106
 107 /* Configuration registers */
 108 #define ARM_SMMU_GR0_sCR0               0x0
 109 #define sCR0_CLIENTPD                   (1 << 0)
 110 #define sCR0_GFRE                       (1 << 1)
 111 #define sCR0_GFIE                       (1 << 2)
 112 #define sCR0_GCFGFRE                    (1 << 4)
 113 #define sCR0_GCFGFIE                    (1 << 5)
 114 #define sCR0_USFCFG                     (1 << 10)
 115 #define sCR0_VMIDPNE                    (1 << 11)
 116 #define sCR0_PTM                        (1 << 12)
 117 #define sCR0_FB                         (1 << 13)
 118 #define sCR0_BSU_SHIFT                  14
 119 #define sCR0_BSU_MASK                   0x3
 120
 121 /* Identification registers */
 122 #define ARM_SMMU_GR0_ID0                0x20
 123 #define ARM_SMMU_GR0_ID1                0x24
 124 #define ARM_SMMU_GR0_ID2                0x28
 125 #define ARM_SMMU_GR0_ID3                0x2c
 126 #define ARM_SMMU_GR0_ID4                0x30
 127 #define ARM_SMMU_GR0_ID5                0x34
 128 #define ARM_SMMU_GR0_ID6                0x38
 129 #define ARM_SMMU_GR0_ID7                0x3c
 130 #define ARM_SMMU_GR0_sGFSR              0x48
 131 #define ARM_SMMU_GR0_sGFSYNR0           0x50
 132 #define ARM_SMMU_GR0_sGFSYNR1           0x54
 133 #define ARM_SMMU_GR0_sGFSYNR2           0x58
 134 #define ARM_SMMU_GR0_PIDR0              0xfe0
 135 #define ARM_SMMU_GR0_PIDR1              0xfe4
 136 #define ARM_SMMU_GR0_PIDR2              0xfe8
 137
 138 #define ID0_S1TS                        (1 << 30)
 139 #define ID0_S2TS                        (1 << 29)
 140 #define ID0_NTS                         (1 << 28)
 141 #define ID0_SMS                         (1 << 27)
 142 #define ID0_PTFS_SHIFT                  24
 143 #define ID0_PTFS_MASK                   0x2
 144 #define ID0_PTFS_V8_ONLY                0x2
 145 #define ID0_CTTW                        (1 << 14)
 146 #define ID0_NUMIRPT_SHIFT               16
 147 #define ID0_NUMIRPT_MASK                0xff
 148 #define ID0_NUMSMRG_SHIFT               0
 149 #define ID0_NUMSMRG_MASK                0xff
 150
 151 #define ID1_PAGESIZE                    (1 << 31)
 152 #define ID1_NUMPAGENDXB_SHIFT           28
 153 #define ID1_NUMPAGENDXB_MASK            7
 154 #define ID1_NUMS2CB_SHIFT               16
 155 #define ID1_NUMS2CB_MASK                0xff
 156 #define ID1_NUMCB_SHIFT                 0
 157 #define ID1_NUMCB_MASK                  0xff
 158
 159 #define ID2_OAS_SHIFT                   4
 160 #define ID2_OAS_MASK                    0xf
 161 #define ID2_IAS_SHIFT                   0
 162 #define ID2_IAS_MASK                    0xf
 163 #define ID2_UBS_SHIFT                   8
 164 #define ID2_UBS_MASK                    0xf
 165 #define ID2_PTFS_4K                     (1 << 12)
 166 #define ID2_PTFS_16K                    (1 << 13)
 167 #define ID2_PTFS_64K                    (1 << 14)
 168
 169 #define PIDR2_ARCH_SHIFT                4
 170 #define PIDR2_ARCH_MASK                 0xf
 171
 172 /* Global TLB invalidation */
 173 #define ARM_SMMU_GR0_STLBIALL           0x60
 174 #define ARM_SMMU_GR0_TLBIVMID           0x64
 175 #define ARM_SMMU_GR0_TLBIALLNSNH        0x68
 176 #define ARM_SMMU_GR0_TLBIALLH           0x6c
 177 #define ARM_SMMU_GR0_sTLBGSYNC          0x70
 178 #define ARM_SMMU_GR0_sTLBGSTATUS        0x74
 179 #define sTLBGSTATUS_GSACTIVE            (1 << 0)
 180 #define TLB_LOOP_TIMEOUT                1000000 /* 1s! */
 181
 182 /* Stream mapping registers */
 183 #define ARM_SMMU_GR0_SMR(n)             (0x800 + ((n) << 2))
 184 #define SMR_VALID                       (1 << 31)
 185 #define SMR_MASK_SHIFT                  16
 186 #define SMR_MASK_MASK                   0x7fff
 187 #define SMR_ID_SHIFT                    0
 188 #define SMR_ID_MASK                     0x7fff
 189
 190 #define ARM_SMMU_GR0_S2CR(n)            (0xc00 + ((n) << 2))
 191 #define S2CR_CBNDX_SHIFT                0
 192 #define S2CR_CBNDX_MASK                 0xff
 193 #define S2CR_TYPE_SHIFT                 16
 194 #define S2CR_TYPE_MASK                  0x3
 195 #define S2CR_TYPE_TRANS                 (0 << S2CR_TYPE_SHIFT)
 196 #define S2CR_TYPE_BYPASS                (1 << S2CR_TYPE_SHIFT)
 197 #define S2CR_TYPE_FAULT                 (2 << S2CR_TYPE_SHIFT)
 198
 199 /* Context bank attribute registers */
 200 #define ARM_SMMU_GR1_CBAR(n)            (0x0 + ((n) << 2))
 201 #define CBAR_VMID_SHIFT                 0
 202 #define CBAR_VMID_MASK                  0xff
 203 #define CBAR_S1_BPSHCFG_SHIFT           8
 204 #define CBAR_S1_BPSHCFG_MASK            3
 205 #define CBAR_S1_BPSHCFG_NSH             3
 206 #define CBAR_S1_MEMATTR_SHIFT           12
 207 #define CBAR_S1_MEMATTR_MASK            0xf
 208 #define CBAR_S1_MEMATTR_WB              0xf
 209 #define CBAR_TYPE_SHIFT                 16
 210 #define CBAR_TYPE_MASK                  0x3
 211 #define CBAR_TYPE_S2_TRANS              (0 << CBAR_TYPE_SHIFT)
 212 #define CBAR_TYPE_S1_TRANS_S2_BYPASS    (1 << CBAR_TYPE_SHIFT)
 213 #define CBAR_TYPE_S1_TRANS_S2_FAULT     (2 << CBAR_TYPE_SHIFT)
 214 #define CBAR_TYPE_S1_TRANS_S2_TRANS     (3 << CBAR_TYPE_SHIFT)
 215 #define CBAR_IRPTNDX_SHIFT              24
 216 #define CBAR_IRPTNDX_MASK               0xff
 217
 218 #define ARM_SMMU_GR1_CBA2R(n)           (0x800 + ((n) << 2))
 219 #define CBA2R_RW64_32BIT                (0 << 0)
 220 #define CBA2R_RW64_64BIT                (1 << 0)
 221
 222 /* Translation context bank */
 223 #define ARM_SMMU_CB_BASE(smmu)          ((smmu)->base + ((smmu)->size >> 1))
 224 #define ARM_SMMU_CB(smmu, n)            ((n) * (smmu)->pagesize)
 225
 226 #define ARM_SMMU_CB_SCTLR               0x0
 227 #define ARM_SMMU_CB_RESUME              0x8
 228 #define ARM_SMMU_CB_TTBCR2              0x10
 229 #define ARM_SMMU_CB_TTBR0_LO            0x20
 230 #define ARM_SMMU_CB_TTBR0_HI            0x24
 231 #define ARM_SMMU_CB_TTBCR               0x30
 232 #define ARM_SMMU_CB_S1_MAIR0            0x38
 233 #define ARM_SMMU_CB_FSR                 0x58
 234 #define ARM_SMMU_CB_FAR_LO              0x60
 235 #define ARM_SMMU_CB_FAR_HI              0x64
 236 #define ARM_SMMU_CB_FSYNR0              0x68
 237 #define ARM_SMMU_CB_S1_TLBIASID         0x610
 238
 239 #define SCTLR_S1_ASIDPNE                (1 << 12)
 240 #define SCTLR_CFCFG                     (1 << 7)
 241 #define SCTLR_CFIE                      (1 << 6)
 242 #define SCTLR_CFRE                      (1 << 5)
 243 #define SCTLR_E                         (1 << 4)
 244 #define SCTLR_AFE                       (1 << 2)
 245 #define SCTLR_TRE                       (1 << 1)
 246 #define SCTLR_M                         (1 << 0)
 247 #define SCTLR_EAE_SBOP                  (SCTLR_AFE | SCTLR_TRE)
 248
 249 #define RESUME_RETRY                    (0 << 0)
 250 #define RESUME_TERMINATE                (1 << 0)
 251
 252 #define TTBCR_EAE                       (1 << 31)
 253
 254 #define TTBCR_PASIZE_SHIFT              16
 255 #define TTBCR_PASIZE_MASK               0x7
 256
 257 #define TTBCR_TG0_4K                    (0 << 14)
 258 #define TTBCR_TG0_64K                   (1 << 14)
 259
 260 #define TTBCR_SH0_SHIFT                 12
 261 #define TTBCR_SH0_MASK                  0x3
 262 #define TTBCR_SH_NS                     0
 263 #define TTBCR_SH_OS                     2
 264 #define TTBCR_SH_IS                     3
 265
 266 #define TTBCR_ORGN0_SHIFT               10
 267 #define TTBCR_IRGN0_SHIFT               8
 268 #define TTBCR_RGN_MASK                  0x3
 269 #define TTBCR_RGN_NC                    0
 270 #define TTBCR_RGN_WBWA                  1
 271 #define TTBCR_RGN_WT                    2
 272 #define TTBCR_RGN_WB                    3
 273
 274 #define TTBCR_SL0_SHIFT                 6
 275 #define TTBCR_SL0_MASK                  0x3
 276 #define TTBCR_SL0_LVL_2                 0
 277 #define TTBCR_SL0_LVL_1                 1
 278
 279 #define TTBCR_T1SZ_SHIFT                16
 280 #define TTBCR_T0SZ_SHIFT                0
 281 #define TTBCR_SZ_MASK                   0xf
 282
 283 #define TTBCR2_SEP_SHIFT                15
 284 #define TTBCR2_SEP_MASK                 0x7
 285
 286 #define TTBCR2_PASIZE_SHIFT             0
 287 #define TTBCR2_PASIZE_MASK              0x7
 288
 289 /* Common definitions for PASize and SEP fields */
 290 #define TTBCR2_ADDR_32                  0
 291 #define TTBCR2_ADDR_36                  1
 292 #define TTBCR2_ADDR_40                  2
 293 #define TTBCR2_ADDR_42                  3
 294 #define TTBCR2_ADDR_44                  4
 295 #define TTBCR2_ADDR_48                  5
 296
 297 #define TTBRn_HI_ASID_SHIFT             16
 298
 299 #define MAIR_ATTR_SHIFT(n)              ((n) << 3)
 300 #define MAIR_ATTR_MASK                  0xff
 301 #define MAIR_ATTR_DEVICE                0x04
 302 #define MAIR_ATTR_NC                    0x44
 303 #define MAIR_ATTR_WBRWA                 0xff
 304 #define MAIR_ATTR_IDX_NC                0
 305 #define MAIR_ATTR_IDX_CACHE             1
 306 #define MAIR_ATTR_IDX_DEV               2
 307
 308 #define FSR_MULTI                       (1 << 31)
 309 #define FSR_SS                          (1 << 30)
 310 #define FSR_UUT                         (1 << 8)
 311 #define FSR_ASF                         (1 << 7)
 312 #define FSR_TLBLKF                      (1 << 6)
 313 #define FSR_TLBMCF                      (1 << 5)
 314 #define FSR_EF                          (1 << 4)
 315 #define FSR_PF                          (1 << 3)
 316 #define FSR_AFF                         (1 << 2)
 317 #define FSR_TF                          (1 << 1)
 318
 319 #define FSR_IGN                         (FSR_AFF | FSR_ASF | FSR_TLBMCF |       \
 320                                          FSR_TLBLKF)
 321 #define FSR_FAULT                       (FSR_MULTI | FSR_SS | FSR_UUT |         \
 322                                          FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
 323
 324 #define FSYNR0_WNR                      (1 << 4)
 325
 326 struct arm_smmu_smr {
 327         u8                              idx;
 328         u16                             mask;
 329         u16                             id;
 330 };
 331
 332 struct arm_smmu_master {
 333         struct device_node              *of_node;
 334
 335         /*
 336          * The following is specific to the master's position in the
 337          * SMMU chain.
 338          */
 339         struct rb_node                  node;
 340         int                             num_streamids;
 341         u16                             streamids[MAX_MASTER_STREAMIDS];
 342
 343         /*
 344          * We only need to allocate these on the root SMMU, as we
 345          * configure unmatched streams to bypass translation.
 346          */
 347         struct arm_smmu_smr             *smrs;
 348 };
 349
 350 struct arm_smmu_device {
 351         struct device                   *dev;
 352         struct device_node              *parent_of_node;
 353
 354         void __iomem                    *base;
 355         unsigned long                   size;
 356         unsigned long                   pagesize;
 357
 358 #define ARM_SMMU_FEAT_COHERENT_WALK     (1 << 0)
 359 #define ARM_SMMU_FEAT_STREAM_MATCH      (1 << 1)
 360 #define ARM_SMMU_FEAT_TRANS_S1          (1 << 2)
 361 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
 362 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
 363         u32                             features;
 364
 365 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
 366         u32                             options;
 367         int                             version;
 368
 369         u32                             num_context_banks;
 370         u32                             num_s2_context_banks;
 371         DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
 372         atomic_t                        irptndx;
 373
 374         u32                             num_mapping_groups;
 375         DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
 376
 377         unsigned long                   input_size;
 378         unsigned long                   s1_output_size;
 379         unsigned long                   s2_output_size;
 380
 381         u32                             num_global_irqs;
 382         u32                             num_context_irqs;
 383         unsigned int                    *irqs;
 384
 385         struct list_head                list;
 386         struct rb_root                  masters;
 387 };
 388
 389 struct arm_smmu_cfg {
 390         struct arm_smmu_device          *smmu;
 391         u8                              cbndx;
 392         u8                              irptndx;
 393         u32                             cbar;
 394         pgd_t                           *pgd;
 395 };
 396 #define INVALID_IRPTNDX                 0xff
 397
 398 #define ARM_SMMU_CB_ASID(cfg)           ((cfg)->cbndx)
 399 #define ARM_SMMU_CB_VMID(cfg)           ((cfg)->cbndx + 1)
 400
 401 struct arm_smmu_domain {
 402         /*
 403          * A domain can span across multiple, chained SMMUs and requires
 404          * all devices within the domain to follow the same translation
 405          * path.
 406          */
 407         struct arm_smmu_device          *leaf_smmu;
 408         struct arm_smmu_cfg             root_cfg;
 409         phys_addr_t                     output_mask;
 410
 411         spinlock_t                      lock;
 412 };
 413
 414 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
 415 static LIST_HEAD(arm_smmu_devices);
 416
 417 struct arm_smmu_option_prop {
 418         u32 opt;
 419         const char *prop;
 420 };
 421
 422 static struct arm_smmu_option_prop arm_smmu_options [] = {
 423         { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
 424         { 0, NULL},
 425 };
 426
 427 static void parse_driver_options(struct arm_smmu_device *smmu)
 428 {
 429         int i = 0;
 430         do {
 431                 if (of_property_read_bool(smmu->dev->of_node,
 432                                                 arm_smmu_options[i].prop)) {
 433                         smmu->options |= arm_smmu_options[i].opt;
 434                         dev_notice(smmu->dev, "option %s\n",
 435                                 arm_smmu_options[i].prop);
 436                 }
 437         } while (arm_smmu_options[++i].opt);
 438 }
 439
 440 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
 441                                                 struct device_node *dev_node)
 442 {
 443         struct rb_node *node = smmu->masters.rb_node;
 444
 445         while (node) {
 446                 struct arm_smmu_master *master;
 447                 master = container_of(node, struct arm_smmu_master, node);
 448
 449                 if (dev_node < master->of_node)
 450                         node = node->rb_left;
 451                 else if (dev_node > master->of_node)
 452                         node = node->rb_right;
 453                 else
 454                         return master;
 455         }
 456
 457         return NULL;
 458 }
 459
 460 static int insert_smmu_master(struct arm_smmu_device *smmu,
 461                               struct arm_smmu_master *master)
 462 {
 463         struct rb_node **new, *parent;
 464
 465         new = &smmu->masters.rb_node;
 466         parent = NULL;
 467         while (*new) {
 468                 struct arm_smmu_master *this;
 469                 this = container_of(*new, struct arm_smmu_master, node);
 470
 471                 parent = *new;
 472                 if (master->of_node < this->of_node)
 473                         new = &((*new)->rb_left);
 474                 else if (master->of_node > this->of_node)
 475                         new = &((*new)->rb_right);
 476                 else
 477                         return -EEXIST;
 478         }
 479
 480         rb_link_node(&master->node, parent, new);
 481         rb_insert_color(&master->node, &smmu->masters);
 482         return 0;
 483 }
 484
 485 static int register_smmu_master(struct arm_smmu_device *smmu,
 486                                 struct device *dev,
 487                                 struct of_phandle_args *masterspec)
 488 {
 489         int i;
 490         struct arm_smmu_master *master;
 491
 492         master = find_smmu_master(smmu, masterspec->np);
 493         if (master) {
 494                 dev_err(dev,
 495                         "rejecting multiple registrations for master device %s\n",
 496                         masterspec->np->name);
 497                 return -EBUSY;
 498         }
 499
 500         if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
 501                 dev_err(dev,
 502                         "reached maximum number (%d) of stream IDs for master device %s\n",
 503                         MAX_MASTER_STREAMIDS, masterspec->np->name);
 504                 return -ENOSPC;
 505         }
 506
 507         master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
 508         if (!master)
 509                 return -ENOMEM;
 510
 511         master->of_node         = masterspec->np;
 512         master->num_streamids   = masterspec->args_count;
 513
 514         for (i = 0; i < master->num_streamids; ++i)
 515                 master->streamids[i] = masterspec->args[i];
 516
 517         return insert_smmu_master(smmu, master);
 518 }
 519
 520 static struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu)
 521 {
 522         struct arm_smmu_device *parent;
 523
 524         if (!smmu->parent_of_node)
 525                 return NULL;
 526
 527         spin_lock(&arm_smmu_devices_lock);
 528         list_for_each_entry(parent, &arm_smmu_devices, list)
 529                 if (parent->dev->of_node == smmu->parent_of_node)
 530                         goto out_unlock;
 531
 532         parent = NULL;
 533         dev_warn(smmu->dev,
 534                  "Failed to find SMMU parent despite parent in DT\n");
 535 out_unlock:
 536         spin_unlock(&arm_smmu_devices_lock);
 537         return parent;
 538 }
 539
 540 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
 541 {
 542         int idx;
 543
 544         do {
 545                 idx = find_next_zero_bit(map, end, start);
 546                 if (idx == end)
 547                         return -ENOSPC;
 548         } while (test_and_set_bit(idx, map));
 549
 550         return idx;
 551 }
 552
 553 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
 554 {
 555         clear_bit(idx, map);
 556 }
 557
 558 /* Wait for any pending TLB invalidations to complete */
 559 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
 560 {
 561         int count = 0;
 562         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 563
 564         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
 565         while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
 566                & sTLBGSTATUS_GSACTIVE) {
 567                 cpu_relax();
 568                 if (++count == TLB_LOOP_TIMEOUT) {
 569                         dev_err_ratelimited(smmu->dev,
 570                         "TLB sync timed out -- SMMU may be deadlocked\n");
 571                         return;
 572                 }
 573                 udelay(1);
 574         }
 575 }
 576
 577 static void arm_smmu_tlb_inv_context(struct arm_smmu_cfg *cfg)
 578 {
 579         struct arm_smmu_device *smmu = cfg->smmu;
 580         void __iomem *base = ARM_SMMU_GR0(smmu);
 581         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 582
 583         if (stage1) {
 584                 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 585                 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
 586                                base + ARM_SMMU_CB_S1_TLBIASID);
 587         } else {
 588                 base = ARM_SMMU_GR0(smmu);
 589                 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
 590                                base + ARM_SMMU_GR0_TLBIVMID);
 591         }
 592
 593         arm_smmu_tlb_sync(smmu);
 594 }
 595
 596 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 597 {
 598         int flags, ret;
 599         u32 fsr, far, fsynr, resume;
 600         unsigned long iova;
 601         struct iommu_domain *domain = dev;
 602         struct arm_smmu_domain *smmu_domain = domain->priv;
 603         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 604         struct arm_smmu_device *smmu = root_cfg->smmu;
 605         void __iomem *cb_base;
 606
 607         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
 608         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
 609
 610         if (!(fsr & FSR_FAULT))
 611                 return IRQ_NONE;
 612
 613         if (fsr & FSR_IGN)
 614                 dev_err_ratelimited(smmu->dev,
 615                                     "Unexpected context fault (fsr 0x%u)\n",
 616                                     fsr);
 617
 618         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
 619         flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
 620
 621         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
 622         iova = far;
 623 #ifdef CONFIG_64BIT
 624         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
 625         iova |= ((unsigned long)far << 32);
 626 #endif
 627
 628         if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
 629                 ret = IRQ_HANDLED;
 630                 resume = RESUME_RETRY;
 631         } else {
 632                 dev_err_ratelimited(smmu->dev,
 633                     "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
 634                     iova, fsynr, root_cfg->cbndx);
 635                 ret = IRQ_NONE;
 636                 resume = RESUME_TERMINATE;
 637         }
 638
 639         /* Clear the faulting FSR */
 640         writel(fsr, cb_base + ARM_SMMU_CB_FSR);
 641
 642         /* Retry or terminate any stalled transactions */
 643         if (fsr & FSR_SS)
 644                 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
 645
 646         return ret;
 647 }
 648
 649 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
 650 {
 651         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
 652         struct arm_smmu_device *smmu = dev;
 653         void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
 654
 655         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
 656         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
 657         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
 658         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
 659
 660         if (!gfsr)
 661                 return IRQ_NONE;
 662
 663         dev_err_ratelimited(smmu->dev,
 664                 "Unexpected global fault, this could be serious\n");
 665         dev_err_ratelimited(smmu->dev,
 666                 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
 667                 gfsr, gfsynr0, gfsynr1, gfsynr2);
 668
 669         writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
 670         return IRQ_HANDLED;
 671 }
 672
 673 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
 674                                    size_t size)
 675 {
 676         unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
 677
 678
 679         /* Ensure new page tables are visible to the hardware walker */
 680         if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
 681                 dsb(ishst);
 682         } else {
 683                 /*
 684                  * If the SMMU can't walk tables in the CPU caches, treat them
 685                  * like non-coherent DMA since we need to flush the new entries
 686                  * all the way out to memory. There's no possibility of
 687                  * recursion here as the SMMU table walker will not be wired
 688                  * through another SMMU.
 689                  */
 690                 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
 691                                 DMA_TO_DEVICE);
 692         }
 693 }
 694
 695 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 696 {
 697         u32 reg;
 698         bool stage1;
 699         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 700         struct arm_smmu_device *smmu = root_cfg->smmu;
 701         void __iomem *cb_base, *gr0_base, *gr1_base;
 702
 703         gr0_base = ARM_SMMU_GR0(smmu);
 704         gr1_base = ARM_SMMU_GR1(smmu);
 705         stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS;
 706         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
 707
 708         /* CBAR */
 709         reg = root_cfg->cbar;
 710         if (smmu->version == 1)
 711               reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT;
 712
 713         /*
 714          * Use the weakest shareability/memory types, so they are
 715          * overridden by the ttbcr/pte.
 716          */
 717         if (stage1) {
 718                 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
 719                         (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 720         } else {
 721                 reg |= ARM_SMMU_CB_VMID(root_cfg) << CBAR_VMID_SHIFT;
 722         }
 723         writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(root_cfg->cbndx));
 724
 725         if (smmu->version > 1) {
 726                 /* CBA2R */
 727 #ifdef CONFIG_64BIT
 728                 reg = CBA2R_RW64_64BIT;
 729 #else
 730                 reg = CBA2R_RW64_32BIT;
 731 #endif
 732                 writel_relaxed(reg,
 733                                gr1_base + ARM_SMMU_GR1_CBA2R(root_cfg->cbndx));
 734
 735                 /* TTBCR2 */
 736                 switch (smmu->input_size) {
 737                 case 32:
 738                         reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
 739                         break;
 740                 case 36:
 741                         reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
 742                         break;
 743                 case 39:
 744                         reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
 745                         break;
 746                 case 42:
 747                         reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
 748                         break;
 749                 case 44:
 750                         reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
 751                         break;
 752                 case 48:
 753                         reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
 754                         break;
 755                 }
 756
 757                 switch (smmu->s1_output_size) {
 758                 case 32:
 759                         reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
 760                         break;
 761                 case 36:
 762                         reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
 763                         break;
 764                 case 39:
 765                         reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
 766                         break;
 767                 case 42:
 768                         reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
 769                         break;
 770                 case 44:
 771                         reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
 772                         break;
 773                 case 48:
 774                         reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
 775                         break;
 776                 }
 777
 778                 if (stage1)
 779                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
 780         }
 781
 782         /* TTBR0 */
 783         arm_smmu_flush_pgtable(smmu, root_cfg->pgd,
 784                                PTRS_PER_PGD * sizeof(pgd_t));
 785         reg = __pa(root_cfg->pgd);
 786         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
 787         reg = (phys_addr_t)__pa(root_cfg->pgd) >> 32;
 788         if (stage1)
 789                 reg |= ARM_SMMU_CB_ASID(root_cfg) << TTBRn_HI_ASID_SHIFT;
 790         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
 791
 792         /*
 793          * TTBCR
 794          * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
 795          */
 796         if (smmu->version > 1) {
 797                 if (PAGE_SIZE == SZ_4K)
 798                         reg = TTBCR_TG0_4K;
 799                 else
 800                         reg = TTBCR_TG0_64K;
 801
 802                 if (!stage1) {
 803                         reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
 804
 805                         switch (smmu->s2_output_size) {
 806                         case 32:
 807                                 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
 808                                 break;
 809                         case 36:
 810                                 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
 811                                 break;
 812                         case 40:
 813                                 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
 814                                 break;
 815                         case 42:
 816                                 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
 817                                 break;
 818                         case 44:
 819                                 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
 820                                 break;
 821                         case 48:
 822                                 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
 823                                 break;
 824                         }
 825                 } else {
 826                         reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT;
 827                 }
 828         } else {
 829                 reg = 0;
 830         }
 831
 832         reg |= TTBCR_EAE |
 833               (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
 834               (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
 835               (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
 836               (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
 837         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 838
 839         /* MAIR0 (stage-1 only) */
 840         if (stage1) {
 841                 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
 842                       (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
 843                       (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
 844                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
 845         }
 846
 847         /* SCTLR */
 848         reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
 849         if (stage1)
 850                 reg |= SCTLR_S1_ASIDPNE;
 851 #ifdef __BIG_ENDIAN
 852         reg |= SCTLR_E;
 853 #endif
 854         writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
 855 }
 856
 857 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 858                                         struct device *dev)
 859 {
 860         int irq, ret, start;
 861         struct arm_smmu_domain *smmu_domain = domain->priv;
 862         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 863         struct arm_smmu_device *smmu, *parent;
 864
 865         /*
 866          * Walk the SMMU chain to find the root device for this chain.
 867          * We assume that no masters have translations which terminate
 868          * early, and therefore check that the root SMMU does indeed have
 869          * a StreamID for the master in question.
 870          */
 871         parent = dev->archdata.iommu;
 872         smmu_domain->output_mask = -1;
 873         do {
 874                 smmu = parent;
 875                 smmu_domain->output_mask &= (1ULL << smmu->s2_output_size) - 1;
 876         } while ((parent = find_parent_smmu(smmu)));
 877
 878         if (!find_smmu_master(smmu, dev->of_node)) {
 879                 dev_err(dev, "unable to find root SMMU for device\n");
 880                 return -ENODEV;
 881         }
 882
 883         if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
 884                 /*
 885                  * We will likely want to change this if/when KVM gets
 886                  * involved.
 887                  */
 888                 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 889                 start = smmu->num_s2_context_banks;
 890         } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) {
 891                 root_cfg->cbar = CBAR_TYPE_S2_TRANS;
 892                 start = 0;
 893         } else {
 894                 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 895                 start = smmu->num_s2_context_banks;
 896         }
 897
 898         ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
 899                                       smmu->num_context_banks);
 900         if (IS_ERR_VALUE(ret))
 901                 return ret;
 902
 903         root_cfg->cbndx = ret;
 904         if (smmu->version == 1) {
 905                 root_cfg->irptndx = atomic_inc_return(&smmu->irptndx);
 906                 root_cfg->irptndx %= smmu->num_context_irqs;
 907         } else {
 908                 root_cfg->irptndx = root_cfg->cbndx;
 909         }
 910
 911         irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
 912         ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
 913                           "arm-smmu-context-fault", domain);
 914         if (IS_ERR_VALUE(ret)) {
 915                 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
 916                         root_cfg->irptndx, irq);
 917                 root_cfg->irptndx = INVALID_IRPTNDX;
 918                 goto out_free_context;
 919         }
 920
 921         root_cfg->smmu = smmu;
 922         arm_smmu_init_context_bank(smmu_domain);
 923         return ret;
 924
 925 out_free_context:
 926         __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
 927         return ret;
 928 }
 929
 930 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
 931 {
 932         struct arm_smmu_domain *smmu_domain = domain->priv;
 933         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 934         struct arm_smmu_device *smmu = root_cfg->smmu;
 935         void __iomem *cb_base;
 936         int irq;
 937
 938         if (!smmu)
 939                 return;
 940
 941         /* Disable the context bank and nuke the TLB before freeing it. */
 942         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
 943         writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
 944         arm_smmu_tlb_inv_context(root_cfg);
 945
 946         if (root_cfg->irptndx != INVALID_IRPTNDX) {
 947                 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
 948                 free_irq(irq, domain);
 949         }
 950
 951         __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
 952 }
 953
 954 static int arm_smmu_domain_init(struct iommu_domain *domain)
 955 {
 956         struct arm_smmu_domain *smmu_domain;
 957         pgd_t *pgd;
 958
 959         /*
 960          * Allocate the domain and initialise some of its data structures.
 961          * We can't really do anything meaningful until we've added a
 962          * master.
 963          */
 964         smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
 965         if (!smmu_domain)
 966                 return -ENOMEM;
 967
 968         pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
 969         if (!pgd)
 970                 goto out_free_domain;
 971         smmu_domain->root_cfg.pgd = pgd;
 972
 973         spin_lock_init(&smmu_domain->lock);
 974         domain->priv = smmu_domain;
 975         return 0;
 976
 977 out_free_domain:
 978         kfree(smmu_domain);
 979         return -ENOMEM;
 980 }
 981
 982 static void arm_smmu_free_ptes(pmd_t *pmd)
 983 {
 984         pgtable_t table = pmd_pgtable(*pmd);
 985         pgtable_page_dtor(table);
 986         __free_page(table);
 987 }
 988
 989 static void arm_smmu_free_pmds(pud_t *pud)
 990 {
 991         int i;
 992         pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
 993
 994         pmd = pmd_base;
 995         for (i = 0; i < PTRS_PER_PMD; ++i) {
 996                 if (pmd_none(*pmd))
 997                         continue;
 998
 999                 arm_smmu_free_ptes(pmd);
1000                 pmd++;
1001         }
1002
1003         pmd_free(NULL, pmd_base);
1004 }
1005
1006 static void arm_smmu_free_puds(pgd_t *pgd)
1007 {
1008         int i;
1009         pud_t *pud, *pud_base = pud_offset(pgd, 0);
1010
1011         pud = pud_base;
1012         for (i = 0; i < PTRS_PER_PUD; ++i) {
1013                 if (pud_none(*pud))
1014                         continue;
1015
1016                 arm_smmu_free_pmds(pud);
1017                 pud++;
1018         }
1019
1020         pud_free(NULL, pud_base);
1021 }
1022
1023 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
1024 {
1025         int i;
1026         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1027         pgd_t *pgd, *pgd_base = root_cfg->pgd;
1028
1029         /*
1030          * Recursively free the page tables for this domain. We don't
1031          * care about speculative TLB filling because the tables should
1032          * not be active in any context bank at this point (SCTLR.M is 0).
1033          */
1034         pgd = pgd_base;
1035         for (i = 0; i < PTRS_PER_PGD; ++i) {
1036                 if (pgd_none(*pgd))
1037                         continue;
1038                 arm_smmu_free_puds(pgd);
1039                 pgd++;
1040         }
1041
1042         kfree(pgd_base);
1043 }
1044
1045 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1046 {
1047         struct arm_smmu_domain *smmu_domain = domain->priv;
1048
1049         /*
1050          * Free the domain resources. We assume that all devices have
1051          * already been detached.
1052          */
1053         arm_smmu_destroy_domain_context(domain);
1054         arm_smmu_free_pgtables(smmu_domain);
1055         kfree(smmu_domain);
1056 }
1057
1058 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1059                                           struct arm_smmu_master *master)
1060 {
1061         int i;
1062         struct arm_smmu_smr *smrs;
1063         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1064
1065         if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1066                 return 0;
1067
1068         if (master->smrs)
1069                 return -EEXIST;
1070
1071         smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL);
1072         if (!smrs) {
1073                 dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n",
1074                         master->num_streamids, master->of_node->name);
1075                 return -ENOMEM;
1076         }
1077
1078         /* Allocate the SMRs on the root SMMU */
1079         for (i = 0; i < master->num_streamids; ++i) {
1080                 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1081                                                   smmu->num_mapping_groups);
1082                 if (IS_ERR_VALUE(idx)) {
1083                         dev_err(smmu->dev, "failed to allocate free SMR\n");
1084                         goto err_free_smrs;
1085                 }
1086
1087                 smrs[i] = (struct arm_smmu_smr) {
1088                         .idx    = idx,
1089                         .mask   = 0, /* We don't currently share SMRs */
1090                         .id     = master->streamids[i],
1091                 };
1092         }
1093
1094         /* It worked! Now, poke the actual hardware */
1095         for (i = 0; i < master->num_streamids; ++i) {
1096                 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1097                           smrs[i].mask << SMR_MASK_SHIFT;
1098                 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1099         }
1100
1101         master->smrs = smrs;
1102         return 0;
1103
1104 err_free_smrs:
1105         while (--i >= 0)
1106                 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1107         kfree(smrs);
1108         return -ENOSPC;
1109 }
1110
1111 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1112                                       struct arm_smmu_master *master)
1113 {
1114         int i;
1115         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1116         struct arm_smmu_smr *smrs = master->smrs;
1117
1118         /* Invalidate the SMRs before freeing back to the allocator */
1119         for (i = 0; i < master->num_streamids; ++i) {
1120                 u8 idx = smrs[i].idx;
1121                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1122                 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1123         }
1124
1125         master->smrs = NULL;
1126         kfree(smrs);
1127 }
1128
1129 static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
1130                                            struct arm_smmu_master *master)
1131 {
1132         int i;
1133         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1134
1135         for (i = 0; i < master->num_streamids; ++i) {
1136                 u16 sid = master->streamids[i];
1137                 writel_relaxed(S2CR_TYPE_BYPASS,
1138                                gr0_base + ARM_SMMU_GR0_S2CR(sid));
1139         }
1140 }
1141
1142 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1143                                       struct arm_smmu_master *master)
1144 {
1145         int i, ret;
1146         struct arm_smmu_device *parent, *smmu = smmu_domain->root_cfg.smmu;
1147         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1148
1149         ret = arm_smmu_master_configure_smrs(smmu, master);
1150         if (ret)
1151                 return ret;
1152
1153         /* Bypass the leaves */
1154         smmu = smmu_domain->leaf_smmu;
1155         while ((parent = find_parent_smmu(smmu))) {
1156                 /*
1157                  * We won't have a StreamID match for anything but the root
1158                  * smmu, so we only need to worry about StreamID indexing,
1159                  * where we must install bypass entries in the S2CRs.
1160                  */
1161                 if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)
1162                         continue;
1163
1164                 arm_smmu_bypass_stream_mapping(smmu, master);
1165                 smmu = parent;
1166         }
1167
1168         /* Now we're at the root, time to point at our context bank */
1169         for (i = 0; i < master->num_streamids; ++i) {
1170                 u32 idx, s2cr;
1171                 idx = master->smrs ? master->smrs[i].idx : master->streamids[i];
1172                 s2cr = S2CR_TYPE_TRANS |
1173                        (smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT);
1174                 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1175         }
1176
1177         return 0;
1178 }
1179
1180 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1181                                           struct arm_smmu_master *master)
1182 {
1183         struct arm_smmu_device *smmu = smmu_domain->root_cfg.smmu;
1184
1185         /*
1186          * We *must* clear the S2CR first, because freeing the SMR means
1187          * that it can be re-allocated immediately.
1188          */
1189         arm_smmu_bypass_stream_mapping(smmu, master);
1190         arm_smmu_master_free_smrs(smmu, master);
1191 }
1192
1193 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1194 {
1195         int ret = -EINVAL;
1196         struct arm_smmu_domain *smmu_domain = domain->priv;
1197         struct arm_smmu_device *device_smmu = dev->archdata.iommu;
1198         struct arm_smmu_master *master;
1199         unsigned long flags;
1200
1201         if (!device_smmu) {
1202                 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1203                 return -ENXIO;
1204         }
1205
1206         /*
1207          * Sanity check the domain. We don't currently support domains
1208          * that cross between different SMMU chains.
1209          */
1210         spin_lock_irqsave(&smmu_domain->lock, flags);
1211         if (!smmu_domain->leaf_smmu) {
1212                 /* Now that we have a master, we can finalise the domain */
1213                 ret = arm_smmu_init_domain_context(domain, dev);
1214                 if (IS_ERR_VALUE(ret))
1215                         goto err_unlock;
1216
1217                 smmu_domain->leaf_smmu = device_smmu;
1218         } else if (smmu_domain->leaf_smmu != device_smmu) {
1219                 dev_err(dev,
1220                         "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1221                         dev_name(smmu_domain->leaf_smmu->dev),
1222                         dev_name(device_smmu->dev));
1223                 goto err_unlock;
1224         }
1225         spin_unlock_irqrestore(&smmu_domain->lock, flags);
1226
1227         /* Looks ok, so add the device to the domain */
1228         master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1229         if (!master)
1230                 return -ENODEV;
1231
1232         return arm_smmu_domain_add_master(smmu_domain, master);
1233
1234 err_unlock:
1235         spin_unlock_irqrestore(&smmu_domain->lock, flags);
1236         return ret;
1237 }
1238
1239 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1240 {
1241         struct arm_smmu_domain *smmu_domain = domain->priv;
1242         struct arm_smmu_master *master;
1243
1244         master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1245         if (master)
1246                 arm_smmu_domain_remove_master(smmu_domain, master);
1247 }
1248
1249 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1250                                              unsigned long end)
1251 {
1252         return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1253                 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1254 }
1255
1256 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1257                                    unsigned long addr, unsigned long end,
1258                                    unsigned long pfn, int prot, int stage)
1259 {
1260         pte_t *pte, *start;
1261         pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
1262
1263         if (pmd_none(*pmd)) {
1264                 /* Allocate a new set of tables */
1265                 pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
1266                 if (!table)
1267                         return -ENOMEM;
1268
1269                 arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
1270                 if (!pgtable_page_ctor(table)) {
1271                         __free_page(table);
1272                         return -ENOMEM;
1273                 }
1274                 pmd_populate(NULL, pmd, table);
1275                 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1276         }
1277
1278         if (stage == 1) {
1279                 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1280                 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
1281                         pteval |= ARM_SMMU_PTE_AP_RDONLY;
1282
1283                 if (prot & IOMMU_CACHE)
1284                         pteval |= (MAIR_ATTR_IDX_CACHE <<
1285                                    ARM_SMMU_PTE_ATTRINDX_SHIFT);
1286         } else {
1287                 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1288                 if (prot & IOMMU_READ)
1289                         pteval |= ARM_SMMU_PTE_HAP_READ;
1290                 if (prot & IOMMU_WRITE)
1291                         pteval |= ARM_SMMU_PTE_HAP_WRITE;
1292                 if (prot & IOMMU_CACHE)
1293                         pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1294                 else
1295                         pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1296         }
1297
1298         /* If no access, create a faulting entry to avoid TLB fills */
1299         if (prot & IOMMU_EXEC)
1300                 pteval &= ~ARM_SMMU_PTE_XN;
1301         else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
1302                 pteval &= ~ARM_SMMU_PTE_PAGE;
1303
1304         pteval |= ARM_SMMU_PTE_SH_IS;
1305         start = pmd_page_vaddr(*pmd) + pte_index(addr);
1306         pte = start;
1307
1308         /*
1309          * Install the page table entries. This is fairly complicated
1310          * since we attempt to make use of the contiguous hint in the
1311          * ptes where possible. The contiguous hint indicates a series
1312          * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1313          * contiguous region with the following constraints:
1314          *
1315          *   - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1316          *   - Each pte in the region has the contiguous hint bit set
1317          *
1318          * This complicates unmapping (also handled by this code, when
1319          * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1320          * possible, yet highly unlikely, that a client may unmap only
1321          * part of a contiguous range. This requires clearing of the
1322          * contiguous hint bits in the range before installing the new
1323          * faulting entries.
1324          *
1325          * Note that re-mapping an address range without first unmapping
1326          * it is not supported, so TLB invalidation is not required here
1327          * and is instead performed at unmap and domain-init time.
1328          */
1329         do {
1330                 int i = 1;
1331                 pteval &= ~ARM_SMMU_PTE_CONT;
1332
1333                 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1334                         i = ARM_SMMU_PTE_CONT_ENTRIES;
1335                         pteval |= ARM_SMMU_PTE_CONT;
1336                 } else if (pte_val(*pte) &
1337                            (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1338                         int j;
1339                         pte_t *cont_start;
1340                         unsigned long idx = pte_index(addr);
1341
1342                         idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1343                         cont_start = pmd_page_vaddr(*pmd) + idx;
1344                         for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1345                                 pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT;
1346
1347                         arm_smmu_flush_pgtable(smmu, cont_start,
1348                                                sizeof(*pte) *
1349                                                ARM_SMMU_PTE_CONT_ENTRIES);
1350                 }
1351
1352                 do {
1353                         *pte = pfn_pte(pfn, __pgprot(pteval));
1354                 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1355         } while (addr != end);
1356
1357         arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1358         return 0;
1359 }
1360
1361 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1362                                    unsigned long addr, unsigned long end,
1363                                    phys_addr_t phys, int prot, int stage)
1364 {
1365         int ret;
1366         pmd_t *pmd;
1367         unsigned long next, pfn = __phys_to_pfn(phys);
1368
1369 #ifndef __PAGETABLE_PMD_FOLDED
1370         if (pud_none(*pud)) {
1371                 pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
1372                 if (!pmd)
1373                         return -ENOMEM;
1374
1375                 arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE);
1376                 pud_populate(NULL, pud, pmd);
1377                 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1378
1379                 pmd += pmd_index(addr);
1380         } else
1381 #endif
1382                 pmd = pmd_offset(pud, addr);
1383
1384         do {
1385                 next = pmd_addr_end(addr, end);
1386                 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn,
1387                                               prot, stage);
1388                 phys += next - addr;
1389         } while (pmd++, addr = next, addr < end);
1390
1391         return ret;
1392 }
1393
1394 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1395                                    unsigned long addr, unsigned long end,
1396                                    phys_addr_t phys, int prot, int stage)
1397 {
1398         int ret = 0;
1399         pud_t *pud;
1400         unsigned long next;
1401
1402 #ifndef __PAGETABLE_PUD_FOLDED
1403         if (pgd_none(*pgd)) {
1404                 pud = (pud_t *)get_zeroed_page(GFP_ATOMIC);
1405                 if (!pud)
1406                         return -ENOMEM;
1407
1408                 arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE);
1409                 pgd_populate(NULL, pgd, pud);
1410                 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1411
1412                 pud += pud_index(addr);
1413         } else
1414 #endif
1415                 pud = pud_offset(pgd, addr);
1416
1417         do {
1418                 next = pud_addr_end(addr, end);
1419                 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1420                                               prot, stage);
1421                 phys += next - addr;
1422         } while (pud++, addr = next, addr < end);
1423
1424         return ret;
1425 }
1426
1427 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1428                                    unsigned long iova, phys_addr_t paddr,
1429                                    size_t size, int prot)
1430 {
1431         int ret, stage;
1432         unsigned long end;
1433         phys_addr_t input_mask, output_mask;
1434         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1435         pgd_t *pgd = root_cfg->pgd;
1436         struct arm_smmu_device *smmu = root_cfg->smmu;
1437         unsigned long flags;
1438
1439         if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
1440                 stage = 2;
1441                 output_mask = (1ULL << smmu->s2_output_size) - 1;
1442         } else {
1443                 stage = 1;
1444                 output_mask = (1ULL << smmu->s1_output_size) - 1;
1445         }
1446
1447         if (!pgd)
1448                 return -EINVAL;
1449
1450         if (size & ~PAGE_MASK)
1451                 return -EINVAL;
1452
1453         input_mask = (1ULL << smmu->input_size) - 1;
1454         if ((phys_addr_t)iova & ~input_mask)
1455                 return -ERANGE;
1456
1457         if (paddr & ~output_mask)
1458                 return -ERANGE;
1459
1460         spin_lock_irqsave(&smmu_domain->lock, flags);
1461         pgd += pgd_index(iova);
1462         end = iova + size;
1463         do {
1464                 unsigned long next = pgd_addr_end(iova, end);
1465
1466                 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1467                                               prot, stage);
1468                 if (ret)
1469                         goto out_unlock;
1470
1471                 paddr += next - iova;
1472                 iova = next;
1473         } while (pgd++, iova != end);
1474
1475 out_unlock:
1476         spin_unlock_irqrestore(&smmu_domain->lock, flags);
1477
1478         return ret;
1479 }
1480
1481 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1482                         phys_addr_t paddr, size_t size, int prot)
1483 {
1484         struct arm_smmu_domain *smmu_domain = domain->priv;
1485
1486         if (!smmu_domain)
1487                 return -ENODEV;
1488
1489         /* Check for silent address truncation up the SMMU chain. */
1490         if ((phys_addr_t)iova & ~smmu_domain->output_mask)
1491                 return -ERANGE;
1492
1493         return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
1494 }
1495
1496 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1497                              size_t size)
1498 {
1499         int ret;
1500         struct arm_smmu_domain *smmu_domain = domain->priv;
1501
1502         ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1503         arm_smmu_tlb_inv_context(&smmu_domain->root_cfg);
1504         return ret ? 0 : size;
1505 }
1506
1507 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1508                                          dma_addr_t iova)
1509 {
1510         pgd_t *pgdp, pgd;
1511         pud_t pud;
1512         pmd_t pmd;
1513         pte_t pte;
1514         struct arm_smmu_domain *smmu_domain = domain->priv;
1515         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1516
1517         pgdp = root_cfg->pgd;
1518         if (!pgdp)
1519                 return 0;
1520
1521         pgd = *(pgdp + pgd_index(iova));
1522         if (pgd_none(pgd))
1523                 return 0;
1524
1525         pud = *pud_offset(&pgd, iova);
1526         if (pud_none(pud))
1527                 return 0;
1528
1529         pmd = *pmd_offset(&pud, iova);
1530         if (pmd_none(pmd))
1531                 return 0;
1532
1533         pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1534         if (pte_none(pte))
1535                 return 0;
1536
1537         return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1538 }
1539
1540 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1541                                    unsigned long cap)
1542 {
1543         unsigned long caps = 0;
1544         struct arm_smmu_domain *smmu_domain = domain->priv;
1545
1546         if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1547                 caps |= IOMMU_CAP_CACHE_COHERENCY;
1548
1549         return !!(cap & caps);
1550 }
1551
1552 static int arm_smmu_add_device(struct device *dev)
1553 {
1554         struct arm_smmu_device *child, *parent, *smmu;
1555         struct arm_smmu_master *master = NULL;
1556         struct iommu_group *group;
1557         int ret;
1558
1559         if (dev->archdata.iommu) {
1560                 dev_warn(dev, "IOMMU driver already assigned to device\n");
1561                 return -EINVAL;
1562         }
1563
1564         spin_lock(&arm_smmu_devices_lock);
1565         list_for_each_entry(parent, &arm_smmu_devices, list) {
1566                 smmu = parent;
1567
1568                 /* Try to find a child of the current SMMU. */
1569                 list_for_each_entry(child, &arm_smmu_devices, list) {
1570                         if (child->parent_of_node == parent->dev->of_node) {
1571                                 /* Does the child sit above our master? */
1572                                 master = find_smmu_master(child, dev->of_node);
1573                                 if (master) {
1574                                         smmu = NULL;
1575                                         break;
1576                                 }
1577                         }
1578                 }
1579
1580                 /* We found some children, so keep searching. */
1581                 if (!smmu) {
1582                         master = NULL;
1583                         continue;
1584                 }
1585
1586                 master = find_smmu_master(smmu, dev->of_node);
1587                 if (master)
1588                         break;
1589         }
1590         spin_unlock(&arm_smmu_devices_lock);
1591
1592         if (!master)
1593                 return -ENODEV;
1594
1595         group = iommu_group_alloc();
1596         if (IS_ERR(group)) {
1597                 dev_err(dev, "Failed to allocate IOMMU group\n");
1598                 return PTR_ERR(group);
1599         }
1600
1601         ret = iommu_group_add_device(group, dev);
1602         iommu_group_put(group);
1603         dev->archdata.iommu = smmu;
1604
1605         return ret;
1606 }
1607
1608 static void arm_smmu_remove_device(struct device *dev)
1609 {
1610         dev->archdata.iommu = NULL;
1611         iommu_group_remove_device(dev);
1612 }
1613
1614 static struct iommu_ops arm_smmu_ops = {
1615         .domain_init    = arm_smmu_domain_init,
1616         .domain_destroy = arm_smmu_domain_destroy,
1617         .attach_dev     = arm_smmu_attach_dev,
1618         .detach_dev     = arm_smmu_detach_dev,
1619         .map            = arm_smmu_map,
1620         .unmap          = arm_smmu_unmap,
1621         .iova_to_phys   = arm_smmu_iova_to_phys,
1622         .domain_has_cap = arm_smmu_domain_has_cap,
1623         .add_device     = arm_smmu_add_device,
1624         .remove_device  = arm_smmu_remove_device,
1625         .pgsize_bitmap  = (SECTION_SIZE |
1626                            ARM_SMMU_PTE_CONT_SIZE |
1627                            PAGE_SIZE),
1628 };
1629
1630 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1631 {
1632         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1633         void __iomem *cb_base;
1634         int i = 0;
1635         u32 reg;
1636
1637         /* clear global FSR */
1638         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1639         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1640
1641         /* Mark all SMRn as invalid and all S2CRn as bypass */
1642         for (i = 0; i < smmu->num_mapping_groups; ++i) {
1643                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
1644                 writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i));
1645         }
1646
1647         /* Make sure all context banks are disabled and clear CB_FSR  */
1648         for (i = 0; i < smmu->num_context_banks; ++i) {
1649                 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1650                 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1651                 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1652         }
1653
1654         /* Invalidate the TLB, just in case */
1655         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1656         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1657         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1658
1659         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1660
1661         /* Enable fault reporting */
1662         reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1663
1664         /* Disable TLB broadcasting. */
1665         reg |= (sCR0_VMIDPNE | sCR0_PTM);
1666
1667         /* Enable client access, but bypass when no mapping is found */
1668         reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1669
1670         /* Disable forced broadcasting */
1671         reg &= ~sCR0_FB;
1672
1673         /* Don't upgrade barriers */
1674         reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1675
1676         /* Push the button */
1677         arm_smmu_tlb_sync(smmu);
1678         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1679 }
1680
1681 static int arm_smmu_id_size_to_bits(int size)
1682 {
1683         switch (size) {
1684         case 0:
1685                 return 32;
1686         case 1:
1687                 return 36;
1688         case 2:
1689                 return 40;
1690         case 3:
1691                 return 42;
1692         case 4:
1693                 return 44;
1694         case 5:
1695         default:
1696                 return 48;
1697         }
1698 }
1699
1700 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1701 {
1702         unsigned long size;
1703         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1704         u32 id;
1705
1706         dev_notice(smmu->dev, "probing hardware configuration...\n");
1707
1708         /* Primecell ID */
1709         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1710         smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1711         dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1712
1713         /* ID0 */
1714         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1715 #ifndef CONFIG_64BIT
1716         if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1717                 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1718                 return -ENODEV;
1719         }
1720 #endif
1721         if (id & ID0_S1TS) {
1722                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1723                 dev_notice(smmu->dev, "\tstage 1 translation\n");
1724         }
1725
1726         if (id & ID0_S2TS) {
1727                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1728                 dev_notice(smmu->dev, "\tstage 2 translation\n");
1729         }
1730
1731         if (id & ID0_NTS) {
1732                 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1733                 dev_notice(smmu->dev, "\tnested translation\n");
1734         }
1735
1736         if (!(smmu->features &
1737                 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1738                  ARM_SMMU_FEAT_TRANS_NESTED))) {
1739                 dev_err(smmu->dev, "\tno translation support!\n");
1740                 return -ENODEV;
1741         }
1742
1743         if (id & ID0_CTTW) {
1744                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1745                 dev_notice(smmu->dev, "\tcoherent table walk\n");
1746         }
1747
1748         if (id & ID0_SMS) {
1749                 u32 smr, sid, mask;
1750
1751                 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1752                 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1753                                            ID0_NUMSMRG_MASK;
1754                 if (smmu->num_mapping_groups == 0) {
1755                         dev_err(smmu->dev,
1756                                 "stream-matching supported, but no SMRs present!\n");
1757                         return -ENODEV;
1758                 }
1759
1760                 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1761                 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1762                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1763                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1764
1765                 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1766                 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1767                 if ((mask & sid) != sid) {
1768                         dev_err(smmu->dev,
1769                                 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1770                                 mask, sid);
1771                         return -ENODEV;
1772                 }
1773
1774                 dev_notice(smmu->dev,
1775                            "\tstream matching with %u register groups, mask 0x%x",
1776                            smmu->num_mapping_groups, mask);
1777         }
1778
1779         /* ID1 */
1780         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1781         smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1782
1783         /* Check for size mismatch of SMMU address space from mapped region */
1784         size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1785         size *= (smmu->pagesize << 1);
1786         if (smmu->size != size)
1787                 dev_warn(smmu->dev, "SMMU address space size (0x%lx) differs "
1788                         "from mapped region size (0x%lx)!\n", size, smmu->size);
1789
1790         smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1791                                       ID1_NUMS2CB_MASK;
1792         smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1793         if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1794                 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1795                 return -ENODEV;
1796         }
1797         dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1798                    smmu->num_context_banks, smmu->num_s2_context_banks);
1799
1800         /* ID2 */
1801         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1802         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1803
1804         /*
1805          * Stage-1 output limited by stage-2 input size due to pgd
1806          * allocation (PTRS_PER_PGD).
1807          */
1808 #ifdef CONFIG_64BIT
1809         smmu->s1_output_size = min((unsigned long)VA_BITS, size);
1810 #else
1811         smmu->s1_output_size = min(32UL, size);
1812 #endif
1813
1814         /* The stage-2 output mask is also applied for bypass */
1815         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1816         smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size);
1817
1818         if (smmu->version == 1) {
1819                 smmu->input_size = 32;
1820         } else {
1821 #ifdef CONFIG_64BIT
1822                 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1823                 size = min(VA_BITS, arm_smmu_id_size_to_bits(size));
1824 #else
1825                 size = 32;
1826 #endif
1827                 smmu->input_size = size;
1828
1829                 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1830                     (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1831                     (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1832                         dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1833                                 PAGE_SIZE);
1834                         return -ENODEV;
1835                 }
1836         }
1837
1838         dev_notice(smmu->dev,
1839                    "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1840                    smmu->input_size, smmu->s1_output_size, smmu->s2_output_size);
1841         return 0;
1842 }
1843
1844 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1845 {
1846         struct resource *res;
1847         struct arm_smmu_device *smmu;
1848         struct device_node *dev_node;
1849         struct device *dev = &pdev->dev;
1850         struct rb_node *node;
1851         struct of_phandle_args masterspec;
1852         int num_irqs, i, err;
1853
1854         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1855         if (!smmu) {
1856                 dev_err(dev, "failed to allocate arm_smmu_device\n");
1857                 return -ENOMEM;
1858         }
1859         smmu->dev = dev;
1860
1861         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1862         smmu->base = devm_ioremap_resource(dev, res);
1863         if (IS_ERR(smmu->base))
1864                 return PTR_ERR(smmu->base);
1865         smmu->size = resource_size(res);
1866
1867         if (of_property_read_u32(dev->of_node, "#global-interrupts",
1868                                  &smmu->num_global_irqs)) {
1869                 dev_err(dev, "missing #global-interrupts property\n");
1870                 return -ENODEV;
1871         }
1872
1873         num_irqs = 0;
1874         while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1875                 num_irqs++;
1876                 if (num_irqs > smmu->num_global_irqs)
1877                         smmu->num_context_irqs++;
1878         }
1879
1880         if (!smmu->num_context_irqs) {
1881                 dev_err(dev, "found %d interrupts but expected at least %d\n",
1882                         num_irqs, smmu->num_global_irqs + 1);
1883                 return -ENODEV;
1884         }
1885
1886         smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1887                                   GFP_KERNEL);
1888         if (!smmu->irqs) {
1889                 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1890                 return -ENOMEM;
1891         }
1892
1893         for (i = 0; i < num_irqs; ++i) {
1894                 int irq = platform_get_irq(pdev, i);
1895                 if (irq < 0) {
1896                         dev_err(dev, "failed to get irq index %d\n", i);
1897                         return -ENODEV;
1898                 }
1899                 smmu->irqs[i] = irq;
1900         }
1901
1902         i = 0;
1903         smmu->masters = RB_ROOT;
1904         while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1905                                            "#stream-id-cells", i,
1906                                            &masterspec)) {
1907                 err = register_smmu_master(smmu, dev, &masterspec);
1908                 if (err) {
1909                         dev_err(dev, "failed to add master %s\n",
1910                                 masterspec.np->name);
1911                         goto out_put_masters;
1912                 }
1913
1914                 i++;
1915         }
1916         dev_notice(dev, "registered %d master devices\n", i);
1917
1918         if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0)))
1919                 smmu->parent_of_node = dev_node;
1920
1921         err = arm_smmu_device_cfg_probe(smmu);
1922         if (err)
1923                 goto out_put_parent;
1924
1925         parse_driver_options(smmu);
1926
1927         if (smmu->version > 1 &&
1928             smmu->num_context_banks != smmu->num_context_irqs) {
1929                 dev_err(dev,
1930                         "found only %d context interrupt(s) but %d required\n",
1931                         smmu->num_context_irqs, smmu->num_context_banks);
1932                 err = -ENODEV;
1933                 goto out_put_parent;
1934         }
1935
1936         for (i = 0; i < smmu->num_global_irqs; ++i) {
1937                 err = request_irq(smmu->irqs[i],
1938                                   arm_smmu_global_fault,
1939                                   IRQF_SHARED,
1940                                   "arm-smmu global fault",
1941                                   smmu);
1942                 if (err) {
1943                         dev_err(dev, "failed to request global IRQ %d (%u)\n",
1944                                 i, smmu->irqs[i]);
1945                         goto out_free_irqs;
1946                 }
1947         }
1948
1949         INIT_LIST_HEAD(&smmu->list);
1950         spin_lock(&arm_smmu_devices_lock);
1951         list_add(&smmu->list, &arm_smmu_devices);
1952         spin_unlock(&arm_smmu_devices_lock);
1953
1954         arm_smmu_device_reset(smmu);
1955         return 0;
1956
1957 out_free_irqs:
1958         while (i--)
1959                 free_irq(smmu->irqs[i], smmu);
1960
1961 out_put_parent:
1962         if (smmu->parent_of_node)
1963                 of_node_put(smmu->parent_of_node);
1964
1965 out_put_masters:
1966         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1967                 struct arm_smmu_master *master;
1968                 master = container_of(node, struct arm_smmu_master, node);
1969                 of_node_put(master->of_node);
1970         }
1971
1972         return err;
1973 }
1974
1975 static int arm_smmu_device_remove(struct platform_device *pdev)
1976 {
1977         int i;
1978         struct device *dev = &pdev->dev;
1979         struct arm_smmu_device *curr, *smmu = NULL;
1980         struct rb_node *node;
1981
1982         spin_lock(&arm_smmu_devices_lock);
1983         list_for_each_entry(curr, &arm_smmu_devices, list) {
1984                 if (curr->dev == dev) {
1985                         smmu = curr;
1986                         list_del(&smmu->list);
1987                         break;
1988                 }
1989         }
1990         spin_unlock(&arm_smmu_devices_lock);
1991
1992         if (!smmu)
1993                 return -ENODEV;
1994
1995         if (smmu->parent_of_node)
1996                 of_node_put(smmu->parent_of_node);
1997
1998         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1999                 struct arm_smmu_master *master;
2000                 master = container_of(node, struct arm_smmu_master, node);
2001                 of_node_put(master->of_node);
2002         }
2003
2004         if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
2005                 dev_err(dev, "removing device with active domains!\n");
2006
2007         for (i = 0; i < smmu->num_global_irqs; ++i)
2008                 free_irq(smmu->irqs[i], smmu);
2009
2010         /* Turn the thing off */
2011         writel(sCR0_CLIENTPD,ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
2012         return 0;
2013 }
2014
2015 #ifdef CONFIG_OF
2016 static struct of_device_id arm_smmu_of_match[] = {
2017         { .compatible = "arm,smmu-v1", },
2018         { .compatible = "arm,smmu-v2", },
2019         { .compatible = "arm,mmu-400", },
2020         { .compatible = "arm,mmu-500", },
2021         { },
2022 };
2023 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
2024 #endif
2025
2026 static struct platform_driver arm_smmu_driver = {
2027         .driver = {
2028                 .owner          = THIS_MODULE,
2029                 .name           = "arm-smmu",
2030                 .of_match_table = of_match_ptr(arm_smmu_of_match),
2031         },
2032         .probe  = arm_smmu_device_dt_probe,
2033         .remove = arm_smmu_device_remove,
2034 };
2035
2036 static int __init arm_smmu_init(void)
2037 {
2038         int ret;
2039
2040         ret = platform_driver_register(&arm_smmu_driver);
2041         if (ret)
2042                 return ret;
2043
2044         /* Oh, for a proper bus abstraction */
2045         if (!iommu_present(&platform_bus_type))
2046                 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2047
2048 #ifdef CONFIG_ARM_AMBA
2049         if (!iommu_present(&amba_bustype))
2050                 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2051 #endif
2052
2053         return 0;
2054 }
2055
2056 static void __exit arm_smmu_exit(void)
2057 {
2058         return platform_driver_unregister(&arm_smmu_driver);
2059 }
2060
2061 subsys_initcall(arm_smmu_init);
2062 module_exit(arm_smmu_exit);
2063
2064 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2065 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2066 MODULE_LICENSE("GPL v2");