drivers/iommu/arm-smmu.c

   1 /*
   2  * IOMMU API for ARM architected SMMU implementations.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16  *
  17  * Copyright (C) 2013 ARM Limited
  18  *
  19  * Author: Will Deacon <will.deacon@arm.com>
  20  *
  21  * This driver currently supports:
  22  *      - SMMUv1 and v2 implementations
  23  *      - Stream-matching and stream-indexing
  24  *      - v7/v8 long-descriptor format
  25  *      - Non-secure access to the SMMU
  26  *      - 4k and 64k pages, with contiguous pte hints.
  27  *      - Up to 42-bit addressing (dependent on VA_BITS)
  28  *      - Context fault reporting
  29  */
  30
  31 #define pr_fmt(fmt) "arm-smmu: " fmt
  32
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/err.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/io.h>
  38 #include <linux/iommu.h>
  39 #include <linux/mm.h>
  40 #include <linux/module.h>
  41 #include <linux/of.h>
  42 #include <linux/pci.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/slab.h>
  45 #include <linux/spinlock.h>
  46
  47 #include <linux/amba/bus.h>
  48
  49 #include <asm/pgalloc.h>
  50
  51 /* Maximum number of stream IDs assigned to a single device */
  52 #define MAX_MASTER_STREAMIDS            MAX_PHANDLE_ARGS
  53
  54 /* Maximum number of context banks per SMMU */
  55 #define ARM_SMMU_MAX_CBS                128
  56
  57 /* Maximum number of mapping groups per SMMU */
  58 #define ARM_SMMU_MAX_SMRS               128
  59
  60 /* SMMU global address space */
  61 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
  62 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (1 << (smmu)->pgshift))
  63
  64 /*
  65  * SMMU global address space with conditional offset to access secure
  66  * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
  67  * nsGFSYNR0: 0x450)
  68  */
  69 #define ARM_SMMU_GR0_NS(smmu)                                           \
  70         ((smmu)->base +                                                 \
  71                 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)       \
  72                         ? 0x400 : 0))
  73
  74 /* Page table bits */
  75 #define ARM_SMMU_PTE_XN                 (((pteval_t)3) << 53)
  76 #define ARM_SMMU_PTE_CONT               (((pteval_t)1) << 52)
  77 #define ARM_SMMU_PTE_AF                 (((pteval_t)1) << 10)
  78 #define ARM_SMMU_PTE_SH_NS              (((pteval_t)0) << 8)
  79 #define ARM_SMMU_PTE_SH_OS              (((pteval_t)2) << 8)
  80 #define ARM_SMMU_PTE_SH_IS              (((pteval_t)3) << 8)
  81 #define ARM_SMMU_PTE_PAGE               (((pteval_t)3) << 0)
  82
  83 #if PAGE_SIZE == SZ_4K
  84 #define ARM_SMMU_PTE_CONT_ENTRIES       16
  85 #elif PAGE_SIZE == SZ_64K
  86 #define ARM_SMMU_PTE_CONT_ENTRIES       32
  87 #else
  88 #define ARM_SMMU_PTE_CONT_ENTRIES       1
  89 #endif
  90
  91 #define ARM_SMMU_PTE_CONT_SIZE          (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
  92 #define ARM_SMMU_PTE_CONT_MASK          (~(ARM_SMMU_PTE_CONT_SIZE - 1))
  93
  94 /* Stage-1 PTE */
  95 #define ARM_SMMU_PTE_AP_UNPRIV          (((pteval_t)1) << 6)
  96 #define ARM_SMMU_PTE_AP_RDONLY          (((pteval_t)2) << 6)
  97 #define ARM_SMMU_PTE_ATTRINDX_SHIFT     2
  98 #define ARM_SMMU_PTE_nG                 (((pteval_t)1) << 11)
  99
 100 /* Stage-2 PTE */
 101 #define ARM_SMMU_PTE_HAP_FAULT          (((pteval_t)0) << 6)
 102 #define ARM_SMMU_PTE_HAP_READ           (((pteval_t)1) << 6)
 103 #define ARM_SMMU_PTE_HAP_WRITE          (((pteval_t)2) << 6)
 104 #define ARM_SMMU_PTE_MEMATTR_OIWB       (((pteval_t)0xf) << 2)
 105 #define ARM_SMMU_PTE_MEMATTR_NC         (((pteval_t)0x5) << 2)
 106 #define ARM_SMMU_PTE_MEMATTR_DEV        (((pteval_t)0x1) << 2)
 107
 108 /* Configuration registers */
 109 #define ARM_SMMU_GR0_sCR0               0x0
 110 #define sCR0_CLIENTPD                   (1 << 0)
 111 #define sCR0_GFRE                       (1 << 1)
 112 #define sCR0_GFIE                       (1 << 2)
 113 #define sCR0_GCFGFRE                    (1 << 4)
 114 #define sCR0_GCFGFIE                    (1 << 5)
 115 #define sCR0_USFCFG                     (1 << 10)
 116 #define sCR0_VMIDPNE                    (1 << 11)
 117 #define sCR0_PTM                        (1 << 12)
 118 #define sCR0_FB                         (1 << 13)
 119 #define sCR0_BSU_SHIFT                  14
 120 #define sCR0_BSU_MASK                   0x3
 121
 122 /* Identification registers */
 123 #define ARM_SMMU_GR0_ID0                0x20
 124 #define ARM_SMMU_GR0_ID1                0x24
 125 #define ARM_SMMU_GR0_ID2                0x28
 126 #define ARM_SMMU_GR0_ID3                0x2c
 127 #define ARM_SMMU_GR0_ID4                0x30
 128 #define ARM_SMMU_GR0_ID5                0x34
 129 #define ARM_SMMU_GR0_ID6                0x38
 130 #define ARM_SMMU_GR0_ID7                0x3c
 131 #define ARM_SMMU_GR0_sGFSR              0x48
 132 #define ARM_SMMU_GR0_sGFSYNR0           0x50
 133 #define ARM_SMMU_GR0_sGFSYNR1           0x54
 134 #define ARM_SMMU_GR0_sGFSYNR2           0x58
 135 #define ARM_SMMU_GR0_PIDR0              0xfe0
 136 #define ARM_SMMU_GR0_PIDR1              0xfe4
 137 #define ARM_SMMU_GR0_PIDR2              0xfe8
 138
 139 #define ID0_S1TS                        (1 << 30)
 140 #define ID0_S2TS                        (1 << 29)
 141 #define ID0_NTS                         (1 << 28)
 142 #define ID0_SMS                         (1 << 27)
 143 #define ID0_PTFS_SHIFT                  24
 144 #define ID0_PTFS_MASK                   0x2
 145 #define ID0_PTFS_V8_ONLY                0x2
 146 #define ID0_CTTW                        (1 << 14)
 147 #define ID0_NUMIRPT_SHIFT               16
 148 #define ID0_NUMIRPT_MASK                0xff
 149 #define ID0_NUMSIDB_SHIFT               9
 150 #define ID0_NUMSIDB_MASK                0xf
 151 #define ID0_NUMSMRG_SHIFT               0
 152 #define ID0_NUMSMRG_MASK                0xff
 153
 154 #define ID1_PAGESIZE                    (1 << 31)
 155 #define ID1_NUMPAGENDXB_SHIFT           28
 156 #define ID1_NUMPAGENDXB_MASK            7
 157 #define ID1_NUMS2CB_SHIFT               16
 158 #define ID1_NUMS2CB_MASK                0xff
 159 #define ID1_NUMCB_SHIFT                 0
 160 #define ID1_NUMCB_MASK                  0xff
 161
 162 #define ID2_OAS_SHIFT                   4
 163 #define ID2_OAS_MASK                    0xf
 164 #define ID2_IAS_SHIFT                   0
 165 #define ID2_IAS_MASK                    0xf
 166 #define ID2_UBS_SHIFT                   8
 167 #define ID2_UBS_MASK                    0xf
 168 #define ID2_PTFS_4K                     (1 << 12)
 169 #define ID2_PTFS_16K                    (1 << 13)
 170 #define ID2_PTFS_64K                    (1 << 14)
 171
 172 #define PIDR2_ARCH_SHIFT                4
 173 #define PIDR2_ARCH_MASK                 0xf
 174
 175 /* Global TLB invalidation */
 176 #define ARM_SMMU_GR0_STLBIALL           0x60
 177 #define ARM_SMMU_GR0_TLBIVMID           0x64
 178 #define ARM_SMMU_GR0_TLBIALLNSNH        0x68
 179 #define ARM_SMMU_GR0_TLBIALLH           0x6c
 180 #define ARM_SMMU_GR0_sTLBGSYNC          0x70
 181 #define ARM_SMMU_GR0_sTLBGSTATUS        0x74
 182 #define sTLBGSTATUS_GSACTIVE            (1 << 0)
 183 #define TLB_LOOP_TIMEOUT                1000000 /* 1s! */
 184
 185 /* Stream mapping registers */
 186 #define ARM_SMMU_GR0_SMR(n)             (0x800 + ((n) << 2))
 187 #define SMR_VALID                       (1 << 31)
 188 #define SMR_MASK_SHIFT                  16
 189 #define SMR_MASK_MASK                   0x7fff
 190 #define SMR_ID_SHIFT                    0
 191 #define SMR_ID_MASK                     0x7fff
 192
 193 #define ARM_SMMU_GR0_S2CR(n)            (0xc00 + ((n) << 2))
 194 #define S2CR_CBNDX_SHIFT                0
 195 #define S2CR_CBNDX_MASK                 0xff
 196 #define S2CR_TYPE_SHIFT                 16
 197 #define S2CR_TYPE_MASK                  0x3
 198 #define S2CR_TYPE_TRANS                 (0 << S2CR_TYPE_SHIFT)
 199 #define S2CR_TYPE_BYPASS                (1 << S2CR_TYPE_SHIFT)
 200 #define S2CR_TYPE_FAULT                 (2 << S2CR_TYPE_SHIFT)
 201
 202 /* Context bank attribute registers */
 203 #define ARM_SMMU_GR1_CBAR(n)            (0x0 + ((n) << 2))
 204 #define CBAR_VMID_SHIFT                 0
 205 #define CBAR_VMID_MASK                  0xff
 206 #define CBAR_S1_BPSHCFG_SHIFT           8
 207 #define CBAR_S1_BPSHCFG_MASK            3
 208 #define CBAR_S1_BPSHCFG_NSH             3
 209 #define CBAR_S1_MEMATTR_SHIFT           12
 210 #define CBAR_S1_MEMATTR_MASK            0xf
 211 #define CBAR_S1_MEMATTR_WB              0xf
 212 #define CBAR_TYPE_SHIFT                 16
 213 #define CBAR_TYPE_MASK                  0x3
 214 #define CBAR_TYPE_S2_TRANS              (0 << CBAR_TYPE_SHIFT)
 215 #define CBAR_TYPE_S1_TRANS_S2_BYPASS    (1 << CBAR_TYPE_SHIFT)
 216 #define CBAR_TYPE_S1_TRANS_S2_FAULT     (2 << CBAR_TYPE_SHIFT)
 217 #define CBAR_TYPE_S1_TRANS_S2_TRANS     (3 << CBAR_TYPE_SHIFT)
 218 #define CBAR_IRPTNDX_SHIFT              24
 219 #define CBAR_IRPTNDX_MASK               0xff
 220
 221 #define ARM_SMMU_GR1_CBA2R(n)           (0x800 + ((n) << 2))
 222 #define CBA2R_RW64_32BIT                (0 << 0)
 223 #define CBA2R_RW64_64BIT                (1 << 0)
 224
 225 /* Translation context bank */
 226 #define ARM_SMMU_CB_BASE(smmu)          ((smmu)->base + ((smmu)->size >> 1))
 227 #define ARM_SMMU_CB(smmu, n)            ((n) * (1 << (smmu)->pgshift))
 228
 229 #define ARM_SMMU_CB_SCTLR               0x0
 230 #define ARM_SMMU_CB_RESUME              0x8
 231 #define ARM_SMMU_CB_TTBCR2              0x10
 232 #define ARM_SMMU_CB_TTBR0_LO            0x20
 233 #define ARM_SMMU_CB_TTBR0_HI            0x24
 234 #define ARM_SMMU_CB_TTBCR               0x30
 235 #define ARM_SMMU_CB_S1_MAIR0            0x38
 236 #define ARM_SMMU_CB_FSR                 0x58
 237 #define ARM_SMMU_CB_FAR_LO              0x60
 238 #define ARM_SMMU_CB_FAR_HI              0x64
 239 #define ARM_SMMU_CB_FSYNR0              0x68
 240 #define ARM_SMMU_CB_S1_TLBIASID         0x610
 241
 242 #define SCTLR_S1_ASIDPNE                (1 << 12)
 243 #define SCTLR_CFCFG                     (1 << 7)
 244 #define SCTLR_CFIE                      (1 << 6)
 245 #define SCTLR_CFRE                      (1 << 5)
 246 #define SCTLR_E                         (1 << 4)
 247 #define SCTLR_AFE                       (1 << 2)
 248 #define SCTLR_TRE                       (1 << 1)
 249 #define SCTLR_M                         (1 << 0)
 250 #define SCTLR_EAE_SBOP                  (SCTLR_AFE | SCTLR_TRE)
 251
 252 #define RESUME_RETRY                    (0 << 0)
 253 #define RESUME_TERMINATE                (1 << 0)
 254
 255 #define TTBCR_EAE                       (1 << 31)
 256
 257 #define TTBCR_PASIZE_SHIFT              16
 258 #define TTBCR_PASIZE_MASK               0x7
 259
 260 #define TTBCR_TG0_4K                    (0 << 14)
 261 #define TTBCR_TG0_64K                   (1 << 14)
 262
 263 #define TTBCR_SH0_SHIFT                 12
 264 #define TTBCR_SH0_MASK                  0x3
 265 #define TTBCR_SH_NS                     0
 266 #define TTBCR_SH_OS                     2
 267 #define TTBCR_SH_IS                     3
 268
 269 #define TTBCR_ORGN0_SHIFT               10
 270 #define TTBCR_IRGN0_SHIFT               8
 271 #define TTBCR_RGN_MASK                  0x3
 272 #define TTBCR_RGN_NC                    0
 273 #define TTBCR_RGN_WBWA                  1
 274 #define TTBCR_RGN_WT                    2
 275 #define TTBCR_RGN_WB                    3
 276
 277 #define TTBCR_SL0_SHIFT                 6
 278 #define TTBCR_SL0_MASK                  0x3
 279 #define TTBCR_SL0_LVL_2                 0
 280 #define TTBCR_SL0_LVL_1                 1
 281
 282 #define TTBCR_T1SZ_SHIFT                16
 283 #define TTBCR_T0SZ_SHIFT                0
 284 #define TTBCR_SZ_MASK                   0xf
 285
 286 #define TTBCR2_SEP_SHIFT                15
 287 #define TTBCR2_SEP_MASK                 0x7
 288
 289 #define TTBCR2_PASIZE_SHIFT             0
 290 #define TTBCR2_PASIZE_MASK              0x7
 291
 292 /* Common definitions for PASize and SEP fields */
 293 #define TTBCR2_ADDR_32                  0
 294 #define TTBCR2_ADDR_36                  1
 295 #define TTBCR2_ADDR_40                  2
 296 #define TTBCR2_ADDR_42                  3
 297 #define TTBCR2_ADDR_44                  4
 298 #define TTBCR2_ADDR_48                  5
 299
 300 #define TTBRn_HI_ASID_SHIFT             16
 301
 302 #define MAIR_ATTR_SHIFT(n)              ((n) << 3)
 303 #define MAIR_ATTR_MASK                  0xff
 304 #define MAIR_ATTR_DEVICE                0x04
 305 #define MAIR_ATTR_NC                    0x44
 306 #define MAIR_ATTR_WBRWA                 0xff
 307 #define MAIR_ATTR_IDX_NC                0
 308 #define MAIR_ATTR_IDX_CACHE             1
 309 #define MAIR_ATTR_IDX_DEV               2
 310
 311 #define FSR_MULTI                       (1 << 31)
 312 #define FSR_SS                          (1 << 30)
 313 #define FSR_UUT                         (1 << 8)
 314 #define FSR_ASF                         (1 << 7)
 315 #define FSR_TLBLKF                      (1 << 6)
 316 #define FSR_TLBMCF                      (1 << 5)
 317 #define FSR_EF                          (1 << 4)
 318 #define FSR_PF                          (1 << 3)
 319 #define FSR_AFF                         (1 << 2)
 320 #define FSR_TF                          (1 << 1)
 321
 322 #define FSR_IGN                         (FSR_AFF | FSR_ASF | \
 323                                          FSR_TLBMCF | FSR_TLBLKF)
 324 #define FSR_FAULT                       (FSR_MULTI | FSR_SS | FSR_UUT | \
 325                                          FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
 326
 327 #define FSYNR0_WNR                      (1 << 4)
 328
 329 static int force_stage;
 330 module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR);
 331 MODULE_PARM_DESC(force_stage,
 332         "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
 333
 334 struct arm_smmu_smr {
 335         u8                              idx;
 336         u16                             mask;
 337         u16                             id;
 338 };
 339
 340 struct arm_smmu_master_cfg {
 341         int                             num_streamids;
 342         u16                             streamids[MAX_MASTER_STREAMIDS];
 343         struct arm_smmu_smr             *smrs;
 344 };
 345
 346 struct arm_smmu_master {
 347         struct device_node              *of_node;
 348         struct rb_node                  node;
 349         struct arm_smmu_master_cfg      cfg;
 350 };
 351
 352 struct arm_smmu_device {
 353         struct device                   *dev;
 354
 355         void __iomem                    *base;
 356         unsigned long                   size;
 357         unsigned long                   pgshift;
 358
 359 #define ARM_SMMU_FEAT_COHERENT_WALK     (1 << 0)
 360 #define ARM_SMMU_FEAT_STREAM_MATCH      (1 << 1)
 361 #define ARM_SMMU_FEAT_TRANS_S1          (1 << 2)
 362 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
 363 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
 364         u32                             features;
 365
 366 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
 367         u32                             options;
 368         int                             version;
 369
 370         u32                             num_context_banks;
 371         u32                             num_s2_context_banks;
 372         DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
 373         atomic_t                        irptndx;
 374
 375         u32                             num_mapping_groups;
 376         DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
 377
 378         unsigned long                   input_size;
 379         unsigned long                   s1_output_size;
 380         unsigned long                   s2_output_size;
 381
 382         u32                             num_global_irqs;
 383         u32                             num_context_irqs;
 384         unsigned int                    *irqs;
 385
 386         struct list_head                list;
 387         struct rb_root                  masters;
 388 };
 389
 390 struct arm_smmu_cfg {
 391         u8                              cbndx;
 392         u8                              irptndx;
 393         u32                             cbar;
 394         pgd_t                           *pgd;
 395 };
 396 #define INVALID_IRPTNDX                 0xff
 397
 398 #define ARM_SMMU_CB_ASID(cfg)           ((cfg)->cbndx)
 399 #define ARM_SMMU_CB_VMID(cfg)           ((cfg)->cbndx + 1)
 400
 401 struct arm_smmu_domain {
 402         struct arm_smmu_device          *smmu;
 403         struct arm_smmu_cfg             cfg;
 404         spinlock_t                      lock;
 405 };
 406
 407 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
 408 static LIST_HEAD(arm_smmu_devices);
 409
 410 struct arm_smmu_option_prop {
 411         u32 opt;
 412         const char *prop;
 413 };
 414
 415 static struct arm_smmu_option_prop arm_smmu_options[] = {
 416         { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
 417         { 0, NULL},
 418 };
 419
 420 static void parse_driver_options(struct arm_smmu_device *smmu)
 421 {
 422         int i = 0;
 423
 424         do {
 425                 if (of_property_read_bool(smmu->dev->of_node,
 426                                                 arm_smmu_options[i].prop)) {
 427                         smmu->options |= arm_smmu_options[i].opt;
 428                         dev_notice(smmu->dev, "option %s\n",
 429                                 arm_smmu_options[i].prop);
 430                 }
 431         } while (arm_smmu_options[++i].opt);
 432 }
 433
 434 static struct device_node *dev_get_dev_node(struct device *dev)
 435 {
 436         if (dev_is_pci(dev)) {
 437                 struct pci_bus *bus = to_pci_dev(dev)->bus;
 438
 439                 while (!pci_is_root_bus(bus))
 440                         bus = bus->parent;
 441                 return bus->bridge->parent->of_node;
 442         }
 443
 444         return dev->of_node;
 445 }
 446
 447 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
 448                                                 struct device_node *dev_node)
 449 {
 450         struct rb_node *node = smmu->masters.rb_node;
 451
 452         while (node) {
 453                 struct arm_smmu_master *master;
 454
 455                 master = container_of(node, struct arm_smmu_master, node);
 456
 457                 if (dev_node < master->of_node)
 458                         node = node->rb_left;
 459                 else if (dev_node > master->of_node)
 460                         node = node->rb_right;
 461                 else
 462                         return master;
 463         }
 464
 465         return NULL;
 466 }
 467
 468 static struct arm_smmu_master_cfg *
 469 find_smmu_master_cfg(struct device *dev)
 470 {
 471         struct arm_smmu_master_cfg *cfg = NULL;
 472         struct iommu_group *group = iommu_group_get(dev);
 473
 474         if (group) {
 475                 cfg = iommu_group_get_iommudata(group);
 476                 iommu_group_put(group);
 477         }
 478
 479         return cfg;
 480 }
 481
 482 static int insert_smmu_master(struct arm_smmu_device *smmu,
 483                               struct arm_smmu_master *master)
 484 {
 485         struct rb_node **new, *parent;
 486
 487         new = &smmu->masters.rb_node;
 488         parent = NULL;
 489         while (*new) {
 490                 struct arm_smmu_master *this
 491                         = container_of(*new, struct arm_smmu_master, node);
 492
 493                 parent = *new;
 494                 if (master->of_node < this->of_node)
 495                         new = &((*new)->rb_left);
 496                 else if (master->of_node > this->of_node)
 497                         new = &((*new)->rb_right);
 498                 else
 499                         return -EEXIST;
 500         }
 501
 502         rb_link_node(&master->node, parent, new);
 503         rb_insert_color(&master->node, &smmu->masters);
 504         return 0;
 505 }
 506
 507 static int register_smmu_master(struct arm_smmu_device *smmu,
 508                                 struct device *dev,
 509                                 struct of_phandle_args *masterspec)
 510 {
 511         int i;
 512         struct arm_smmu_master *master;
 513
 514         master = find_smmu_master(smmu, masterspec->np);
 515         if (master) {
 516                 dev_err(dev,
 517                         "rejecting multiple registrations for master device %s\n",
 518                         masterspec->np->name);
 519                 return -EBUSY;
 520         }
 521
 522         if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
 523                 dev_err(dev,
 524                         "reached maximum number (%d) of stream IDs for master device %s\n",
 525                         MAX_MASTER_STREAMIDS, masterspec->np->name);
 526                 return -ENOSPC;
 527         }
 528
 529         master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
 530         if (!master)
 531                 return -ENOMEM;
 532
 533         master->of_node                 = masterspec->np;
 534         master->cfg.num_streamids       = masterspec->args_count;
 535
 536         for (i = 0; i < master->cfg.num_streamids; ++i) {
 537                 u16 streamid = masterspec->args[i];
 538
 539                 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
 540                      (streamid >= smmu->num_mapping_groups)) {
 541                         dev_err(dev,
 542                                 "stream ID for master device %s greater than maximum allowed (%d)\n",
 543                                 masterspec->np->name, smmu->num_mapping_groups);
 544                         return -ERANGE;
 545                 }
 546                 master->cfg.streamids[i] = streamid;
 547         }
 548         return insert_smmu_master(smmu, master);
 549 }
 550
 551 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
 552 {
 553         struct arm_smmu_device *smmu;
 554         struct arm_smmu_master *master = NULL;
 555         struct device_node *dev_node = dev_get_dev_node(dev);
 556
 557         spin_lock(&arm_smmu_devices_lock);
 558         list_for_each_entry(smmu, &arm_smmu_devices, list) {
 559                 master = find_smmu_master(smmu, dev_node);
 560                 if (master)
 561                         break;
 562         }
 563         spin_unlock(&arm_smmu_devices_lock);
 564
 565         return master ? smmu : NULL;
 566 }
 567
 568 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
 569 {
 570         int idx;
 571
 572         do {
 573                 idx = find_next_zero_bit(map, end, start);
 574                 if (idx == end)
 575                         return -ENOSPC;
 576         } while (test_and_set_bit(idx, map));
 577
 578         return idx;
 579 }
 580
 581 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
 582 {
 583         clear_bit(idx, map);
 584 }
 585
 586 /* Wait for any pending TLB invalidations to complete */
 587 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
 588 {
 589         int count = 0;
 590         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 591
 592         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
 593         while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
 594                & sTLBGSTATUS_GSACTIVE) {
 595                 cpu_relax();
 596                 if (++count == TLB_LOOP_TIMEOUT) {
 597                         dev_err_ratelimited(smmu->dev,
 598                         "TLB sync timed out -- SMMU may be deadlocked\n");
 599                         return;
 600                 }
 601                 udelay(1);
 602         }
 603 }
 604
 605 static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain)
 606 {
 607         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 608         struct arm_smmu_device *smmu = smmu_domain->smmu;
 609         void __iomem *base = ARM_SMMU_GR0(smmu);
 610         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 611
 612         if (stage1) {
 613                 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 614                 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
 615                                base + ARM_SMMU_CB_S1_TLBIASID);
 616         } else {
 617                 base = ARM_SMMU_GR0(smmu);
 618                 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
 619                                base + ARM_SMMU_GR0_TLBIVMID);
 620         }
 621
 622         arm_smmu_tlb_sync(smmu);
 623 }
 624
 625 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 626 {
 627         int flags, ret;
 628         u32 fsr, far, fsynr, resume;
 629         unsigned long iova;
 630         struct iommu_domain *domain = dev;
 631         struct arm_smmu_domain *smmu_domain = domain->priv;
 632         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 633         struct arm_smmu_device *smmu = smmu_domain->smmu;
 634         void __iomem *cb_base;
 635
 636         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 637         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
 638
 639         if (!(fsr & FSR_FAULT))
 640                 return IRQ_NONE;
 641
 642         if (fsr & FSR_IGN)
 643                 dev_err_ratelimited(smmu->dev,
 644                                     "Unexpected context fault (fsr 0x%x)\n",
 645                                     fsr);
 646
 647         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
 648         flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
 649
 650         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
 651         iova = far;
 652 #ifdef CONFIG_64BIT
 653         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
 654         iova |= ((unsigned long)far << 32);
 655 #endif
 656
 657         if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
 658                 ret = IRQ_HANDLED;
 659                 resume = RESUME_RETRY;
 660         } else {
 661                 dev_err_ratelimited(smmu->dev,
 662                     "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
 663                     iova, fsynr, cfg->cbndx);
 664                 ret = IRQ_NONE;
 665                 resume = RESUME_TERMINATE;
 666         }
 667
 668         /* Clear the faulting FSR */
 669         writel(fsr, cb_base + ARM_SMMU_CB_FSR);
 670
 671         /* Retry or terminate any stalled transactions */
 672         if (fsr & FSR_SS)
 673                 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
 674
 675         return ret;
 676 }
 677
 678 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
 679 {
 680         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
 681         struct arm_smmu_device *smmu = dev;
 682         void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
 683
 684         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
 685         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
 686         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
 687         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
 688
 689         if (!gfsr)
 690                 return IRQ_NONE;
 691
 692         dev_err_ratelimited(smmu->dev,
 693                 "Unexpected global fault, this could be serious\n");
 694         dev_err_ratelimited(smmu->dev,
 695                 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
 696                 gfsr, gfsynr0, gfsynr1, gfsynr2);
 697
 698         writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
 699         return IRQ_HANDLED;
 700 }
 701
 702 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
 703                                    size_t size)
 704 {
 705         unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
 706
 707
 708         /* Ensure new page tables are visible to the hardware walker */
 709         if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
 710                 dsb(ishst);
 711         } else {
 712                 /*
 713                  * If the SMMU can't walk tables in the CPU caches, treat them
 714                  * like non-coherent DMA since we need to flush the new entries
 715                  * all the way out to memory. There's no possibility of
 716                  * recursion here as the SMMU table walker will not be wired
 717                  * through another SMMU.
 718                  */
 719                 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
 720                                 DMA_TO_DEVICE);
 721         }
 722 }
 723
 724 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 725 {
 726         u32 reg;
 727         bool stage1;
 728         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 729         struct arm_smmu_device *smmu = smmu_domain->smmu;
 730         void __iomem *cb_base, *gr0_base, *gr1_base;
 731
 732         gr0_base = ARM_SMMU_GR0(smmu);
 733         gr1_base = ARM_SMMU_GR1(smmu);
 734         stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 735         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 736
 737         /* CBAR */
 738         reg = cfg->cbar;
 739         if (smmu->version == 1)
 740                 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
 741
 742         /*
 743          * Use the weakest shareability/memory types, so they are
 744          * overridden by the ttbcr/pte.
 745          */
 746         if (stage1) {
 747                 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
 748                         (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 749         } else {
 750                 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
 751         }
 752         writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
 753
 754         if (smmu->version > 1) {
 755                 /* CBA2R */
 756 #ifdef CONFIG_64BIT
 757                 reg = CBA2R_RW64_64BIT;
 758 #else
 759                 reg = CBA2R_RW64_32BIT;
 760 #endif
 761                 writel_relaxed(reg,
 762                                gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
 763
 764                 /* TTBCR2 */
 765                 switch (smmu->input_size) {
 766                 case 32:
 767                         reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
 768                         break;
 769                 case 36:
 770                         reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
 771                         break;
 772                 case 39:
 773                 case 40:
 774                         reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
 775                         break;
 776                 case 42:
 777                         reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
 778                         break;
 779                 case 44:
 780                         reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
 781                         break;
 782                 case 48:
 783                         reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
 784                         break;
 785                 }
 786
 787                 switch (smmu->s1_output_size) {
 788                 case 32:
 789                         reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
 790                         break;
 791                 case 36:
 792                         reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
 793                         break;
 794                 case 39:
 795                 case 40:
 796                         reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
 797                         break;
 798                 case 42:
 799                         reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
 800                         break;
 801                 case 44:
 802                         reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
 803                         break;
 804                 case 48:
 805                         reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
 806                         break;
 807                 }
 808
 809                 if (stage1)
 810                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
 811         }
 812
 813         /* TTBR0 */
 814         arm_smmu_flush_pgtable(smmu, cfg->pgd,
 815                                PTRS_PER_PGD * sizeof(pgd_t));
 816         reg = __pa(cfg->pgd);
 817         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
 818         reg = (phys_addr_t)__pa(cfg->pgd) >> 32;
 819         if (stage1)
 820                 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
 821         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
 822
 823         /*
 824          * TTBCR
 825          * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
 826          */
 827         if (smmu->version > 1) {
 828                 if (PAGE_SIZE == SZ_4K)
 829                         reg = TTBCR_TG0_4K;
 830                 else
 831                         reg = TTBCR_TG0_64K;
 832
 833                 if (!stage1) {
 834                         reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
 835
 836                         switch (smmu->s2_output_size) {
 837                         case 32:
 838                                 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
 839                                 break;
 840                         case 36:
 841                                 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
 842                                 break;
 843                         case 40:
 844                                 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
 845                                 break;
 846                         case 42:
 847                                 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
 848                                 break;
 849                         case 44:
 850                                 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
 851                                 break;
 852                         case 48:
 853                                 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
 854                                 break;
 855                         }
 856                 } else {
 857                         reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT;
 858                 }
 859         } else {
 860                 reg = 0;
 861         }
 862
 863         reg |= TTBCR_EAE |
 864               (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
 865               (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
 866               (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
 867
 868         if (!stage1)
 869                 reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
 870
 871         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 872
 873         /* MAIR0 (stage-1 only) */
 874         if (stage1) {
 875                 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
 876                       (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
 877                       (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
 878                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
 879         }
 880
 881         /* SCTLR */
 882         reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
 883         if (stage1)
 884                 reg |= SCTLR_S1_ASIDPNE;
 885 #ifdef __BIG_ENDIAN
 886         reg |= SCTLR_E;
 887 #endif
 888         writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
 889 }
 890
 891 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 892                                         struct arm_smmu_device *smmu)
 893 {
 894         int irq, start, ret = 0;
 895         unsigned long flags;
 896         struct arm_smmu_domain *smmu_domain = domain->priv;
 897         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 898
 899         spin_lock_irqsave(&smmu_domain->lock, flags);
 900         if (smmu_domain->smmu)
 901                 goto out_unlock;
 902
 903         if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
 904                 /*
 905                  * We will likely want to change this if/when KVM gets
 906                  * involved.
 907                  */
 908                 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 909                 start = smmu->num_s2_context_banks;
 910         } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) {
 911                 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 912                 start = smmu->num_s2_context_banks;
 913         } else {
 914                 cfg->cbar = CBAR_TYPE_S2_TRANS;
 915                 start = 0;
 916         }
 917
 918         ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
 919                                       smmu->num_context_banks);
 920         if (IS_ERR_VALUE(ret))
 921                 goto out_unlock;
 922
 923         cfg->cbndx = ret;
 924         if (smmu->version == 1) {
 925                 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
 926                 cfg->irptndx %= smmu->num_context_irqs;
 927         } else {
 928                 cfg->irptndx = cfg->cbndx;
 929         }
 930
 931         ACCESS_ONCE(smmu_domain->smmu) = smmu;
 932         arm_smmu_init_context_bank(smmu_domain);
 933         spin_unlock_irqrestore(&smmu_domain->lock, flags);
 934
 935         irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
 936         ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
 937                           "arm-smmu-context-fault", domain);
 938         if (IS_ERR_VALUE(ret)) {
 939                 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
 940                         cfg->irptndx, irq);
 941                 cfg->irptndx = INVALID_IRPTNDX;
 942         }
 943
 944         return 0;
 945
 946 out_unlock:
 947         spin_unlock_irqrestore(&smmu_domain->lock, flags);
 948         return ret;
 949 }
 950
 951 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
 952 {
 953         struct arm_smmu_domain *smmu_domain = domain->priv;
 954         struct arm_smmu_device *smmu = smmu_domain->smmu;
 955         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 956         void __iomem *cb_base;
 957         int irq;
 958
 959         if (!smmu)
 960                 return;
 961
 962         /* Disable the context bank and nuke the TLB before freeing it. */
 963         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 964         writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
 965         arm_smmu_tlb_inv_context(smmu_domain);
 966
 967         if (cfg->irptndx != INVALID_IRPTNDX) {
 968                 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
 969                 free_irq(irq, domain);
 970         }
 971
 972         __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
 973 }
 974
 975 static int arm_smmu_domain_init(struct iommu_domain *domain)
 976 {
 977         struct arm_smmu_domain *smmu_domain;
 978         pgd_t *pgd;
 979
 980         /*
 981          * Allocate the domain and initialise some of its data structures.
 982          * We can't really do anything meaningful until we've added a
 983          * master.
 984          */
 985         smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
 986         if (!smmu_domain)
 987                 return -ENOMEM;
 988
 989         pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
 990         if (!pgd)
 991                 goto out_free_domain;
 992         smmu_domain->cfg.pgd = pgd;
 993
 994         spin_lock_init(&smmu_domain->lock);
 995         domain->priv = smmu_domain;
 996         return 0;
 997
 998 out_free_domain:
 999         kfree(smmu_domain);
1000         return -ENOMEM;
1001 }
1002
1003 static void arm_smmu_free_ptes(pmd_t *pmd)
1004 {
1005         pgtable_t table = pmd_pgtable(*pmd);
1006
1007         __free_page(table);
1008 }
1009
1010 static void arm_smmu_free_pmds(pud_t *pud)
1011 {
1012         int i;
1013         pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
1014
1015         pmd = pmd_base;
1016         for (i = 0; i < PTRS_PER_PMD; ++i) {
1017                 if (pmd_none(*pmd))
1018                         continue;
1019
1020                 arm_smmu_free_ptes(pmd);
1021                 pmd++;
1022         }
1023
1024         pmd_free(NULL, pmd_base);
1025 }
1026
1027 static void arm_smmu_free_puds(pgd_t *pgd)
1028 {
1029         int i;
1030         pud_t *pud, *pud_base = pud_offset(pgd, 0);
1031
1032         pud = pud_base;
1033         for (i = 0; i < PTRS_PER_PUD; ++i) {
1034                 if (pud_none(*pud))
1035                         continue;
1036
1037                 arm_smmu_free_pmds(pud);
1038                 pud++;
1039         }
1040
1041         pud_free(NULL, pud_base);
1042 }
1043
1044 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
1045 {
1046         int i;
1047         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1048         pgd_t *pgd, *pgd_base = cfg->pgd;
1049
1050         /*
1051          * Recursively free the page tables for this domain. We don't
1052          * care about speculative TLB filling because the tables should
1053          * not be active in any context bank at this point (SCTLR.M is 0).
1054          */
1055         pgd = pgd_base;
1056         for (i = 0; i < PTRS_PER_PGD; ++i) {
1057                 if (pgd_none(*pgd))
1058                         continue;
1059                 arm_smmu_free_puds(pgd);
1060                 pgd++;
1061         }
1062
1063         kfree(pgd_base);
1064 }
1065
1066 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1067 {
1068         struct arm_smmu_domain *smmu_domain = domain->priv;
1069
1070         /*
1071          * Free the domain resources. We assume that all devices have
1072          * already been detached.
1073          */
1074         arm_smmu_destroy_domain_context(domain);
1075         arm_smmu_free_pgtables(smmu_domain);
1076         kfree(smmu_domain);
1077 }
1078
1079 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1080                                           struct arm_smmu_master_cfg *cfg)
1081 {
1082         int i;
1083         struct arm_smmu_smr *smrs;
1084         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1085
1086         if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1087                 return 0;
1088
1089         if (cfg->smrs)
1090                 return -EEXIST;
1091
1092         smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1093         if (!smrs) {
1094                 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1095                         cfg->num_streamids);
1096                 return -ENOMEM;
1097         }
1098
1099         /* Allocate the SMRs on the SMMU */
1100         for (i = 0; i < cfg->num_streamids; ++i) {
1101                 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1102                                                   smmu->num_mapping_groups);
1103                 if (IS_ERR_VALUE(idx)) {
1104                         dev_err(smmu->dev, "failed to allocate free SMR\n");
1105                         goto err_free_smrs;
1106                 }
1107
1108                 smrs[i] = (struct arm_smmu_smr) {
1109                         .idx    = idx,
1110                         .mask   = 0, /* We don't currently share SMRs */
1111                         .id     = cfg->streamids[i],
1112                 };
1113         }
1114
1115         /* It worked! Now, poke the actual hardware */
1116         for (i = 0; i < cfg->num_streamids; ++i) {
1117                 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1118                           smrs[i].mask << SMR_MASK_SHIFT;
1119                 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1120         }
1121
1122         cfg->smrs = smrs;
1123         return 0;
1124
1125 err_free_smrs:
1126         while (--i >= 0)
1127                 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1128         kfree(smrs);
1129         return -ENOSPC;
1130 }
1131
1132 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1133                                       struct arm_smmu_master_cfg *cfg)
1134 {
1135         int i;
1136         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1137         struct arm_smmu_smr *smrs = cfg->smrs;
1138
1139         if (!smrs)
1140                 return;
1141
1142         /* Invalidate the SMRs before freeing back to the allocator */
1143         for (i = 0; i < cfg->num_streamids; ++i) {
1144                 u8 idx = smrs[i].idx;
1145
1146                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1147                 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1148         }
1149
1150         cfg->smrs = NULL;
1151         kfree(smrs);
1152 }
1153
1154 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1155                                       struct arm_smmu_master_cfg *cfg)
1156 {
1157         int i, ret;
1158         struct arm_smmu_device *smmu = smmu_domain->smmu;
1159         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1160
1161         /* Devices in an IOMMU group may already be configured */
1162         ret = arm_smmu_master_configure_smrs(smmu, cfg);
1163         if (ret)
1164                 return ret == -EEXIST ? 0 : ret;
1165
1166         for (i = 0; i < cfg->num_streamids; ++i) {
1167                 u32 idx, s2cr;
1168
1169                 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1170                 s2cr = S2CR_TYPE_TRANS |
1171                        (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1172                 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1173         }
1174
1175         return 0;
1176 }
1177
1178 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1179                                           struct arm_smmu_master_cfg *cfg)
1180 {
1181         int i;
1182         struct arm_smmu_device *smmu = smmu_domain->smmu;
1183         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1184
1185         /* An IOMMU group is torn down by the first device to be removed */
1186         if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)
1187                 return;
1188
1189         /*
1190          * We *must* clear the S2CR first, because freeing the SMR means
1191          * that it can be re-allocated immediately.
1192          */
1193         for (i = 0; i < cfg->num_streamids; ++i) {
1194                 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1195
1196                 writel_relaxed(S2CR_TYPE_BYPASS,
1197                                gr0_base + ARM_SMMU_GR0_S2CR(idx));
1198         }
1199
1200         arm_smmu_master_free_smrs(smmu, cfg);
1201 }
1202
1203 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1204 {
1205         int ret;
1206         struct arm_smmu_domain *smmu_domain = domain->priv;
1207         struct arm_smmu_device *smmu, *dom_smmu;
1208         struct arm_smmu_master_cfg *cfg;
1209
1210         smmu = find_smmu_for_device(dev);
1211         if (!smmu) {
1212                 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1213                 return -ENXIO;
1214         }
1215
1216         if (dev->archdata.iommu) {
1217                 dev_err(dev, "already attached to IOMMU domain\n");
1218                 return -EEXIST;
1219         }
1220
1221         /*
1222          * Sanity check the domain. We don't support domains across
1223          * different SMMUs.
1224          */
1225         dom_smmu = ACCESS_ONCE(smmu_domain->smmu);
1226         if (!dom_smmu) {
1227                 /* Now that we have a master, we can finalise the domain */
1228                 ret = arm_smmu_init_domain_context(domain, smmu);
1229                 if (IS_ERR_VALUE(ret))
1230                         return ret;
1231
1232                 dom_smmu = smmu_domain->smmu;
1233         }
1234
1235         if (dom_smmu != smmu) {
1236                 dev_err(dev,
1237                         "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1238                         dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1239                 return -EINVAL;
1240         }
1241
1242         /* Looks ok, so add the device to the domain */
1243         cfg = find_smmu_master_cfg(dev);
1244         if (!cfg)
1245                 return -ENODEV;
1246
1247         ret = arm_smmu_domain_add_master(smmu_domain, cfg);
1248         if (!ret)
1249                 dev->archdata.iommu = domain;
1250         return ret;
1251 }
1252
1253 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1254 {
1255         struct arm_smmu_domain *smmu_domain = domain->priv;
1256         struct arm_smmu_master_cfg *cfg;
1257
1258         cfg = find_smmu_master_cfg(dev);
1259         if (!cfg)
1260                 return;
1261
1262         dev->archdata.iommu = NULL;
1263         arm_smmu_domain_remove_master(smmu_domain, cfg);
1264 }
1265
1266 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1267                                              unsigned long end)
1268 {
1269         return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1270                 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1271 }
1272
1273 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1274                                    unsigned long addr, unsigned long end,
1275                                    unsigned long pfn, int prot, int stage)
1276 {
1277         pte_t *pte, *start;
1278         pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
1279
1280         if (pmd_none(*pmd)) {
1281                 /* Allocate a new set of tables */
1282                 pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
1283
1284                 if (!table)
1285                         return -ENOMEM;
1286
1287                 arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
1288                 pmd_populate(NULL, pmd, table);
1289                 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1290         }
1291
1292         if (stage == 1) {
1293                 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1294                 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
1295                         pteval |= ARM_SMMU_PTE_AP_RDONLY;
1296
1297                 if (prot & IOMMU_CACHE)
1298                         pteval |= (MAIR_ATTR_IDX_CACHE <<
1299                                    ARM_SMMU_PTE_ATTRINDX_SHIFT);
1300         } else {
1301                 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1302                 if (prot & IOMMU_READ)
1303                         pteval |= ARM_SMMU_PTE_HAP_READ;
1304                 if (prot & IOMMU_WRITE)
1305                         pteval |= ARM_SMMU_PTE_HAP_WRITE;
1306                 if (prot & IOMMU_CACHE)
1307                         pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1308                 else
1309                         pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1310         }
1311
1312         /* If no access, create a faulting entry to avoid TLB fills */
1313         if (prot & IOMMU_EXEC)
1314                 pteval &= ~ARM_SMMU_PTE_XN;
1315         else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
1316                 pteval &= ~ARM_SMMU_PTE_PAGE;
1317
1318         pteval |= ARM_SMMU_PTE_SH_IS;
1319         start = pmd_page_vaddr(*pmd) + pte_index(addr);
1320         pte = start;
1321
1322         /*
1323          * Install the page table entries. This is fairly complicated
1324          * since we attempt to make use of the contiguous hint in the
1325          * ptes where possible. The contiguous hint indicates a series
1326          * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1327          * contiguous region with the following constraints:
1328          *
1329          *   - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1330          *   - Each pte in the region has the contiguous hint bit set
1331          *
1332          * This complicates unmapping (also handled by this code, when
1333          * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1334          * possible, yet highly unlikely, that a client may unmap only
1335          * part of a contiguous range. This requires clearing of the
1336          * contiguous hint bits in the range before installing the new
1337          * faulting entries.
1338          *
1339          * Note that re-mapping an address range without first unmapping
1340          * it is not supported, so TLB invalidation is not required here
1341          * and is instead performed at unmap and domain-init time.
1342          */
1343         do {
1344                 int i = 1;
1345
1346                 pteval &= ~ARM_SMMU_PTE_CONT;
1347
1348                 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1349                         i = ARM_SMMU_PTE_CONT_ENTRIES;
1350                         pteval |= ARM_SMMU_PTE_CONT;
1351                 } else if (pte_val(*pte) &
1352                            (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1353                         int j;
1354                         pte_t *cont_start;
1355                         unsigned long idx = pte_index(addr);
1356
1357                         idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1358                         cont_start = pmd_page_vaddr(*pmd) + idx;
1359                         for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1360                                 pte_val(*(cont_start + j)) &=
1361                                         ~ARM_SMMU_PTE_CONT;
1362
1363                         arm_smmu_flush_pgtable(smmu, cont_start,
1364                                                sizeof(*pte) *
1365                                                ARM_SMMU_PTE_CONT_ENTRIES);
1366                 }
1367
1368                 do {
1369                         *pte = pfn_pte(pfn, __pgprot(pteval));
1370                 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1371         } while (addr != end);
1372
1373         arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1374         return 0;
1375 }
1376
1377 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1378                                    unsigned long addr, unsigned long end,
1379                                    phys_addr_t phys, int prot, int stage)
1380 {
1381         int ret;
1382         pmd_t *pmd;
1383         unsigned long next, pfn = __phys_to_pfn(phys);
1384
1385 #ifndef __PAGETABLE_PMD_FOLDED
1386         if (pud_none(*pud)) {
1387                 pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
1388                 if (!pmd)
1389                         return -ENOMEM;
1390
1391                 arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE);
1392                 pud_populate(NULL, pud, pmd);
1393                 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1394
1395                 pmd += pmd_index(addr);
1396         } else
1397 #endif
1398                 pmd = pmd_offset(pud, addr);
1399
1400         do {
1401                 next = pmd_addr_end(addr, end);
1402                 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn,
1403                                               prot, stage);
1404                 phys += next - addr;
1405         } while (pmd++, addr = next, addr < end);
1406
1407         return ret;
1408 }
1409
1410 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1411                                    unsigned long addr, unsigned long end,
1412                                    phys_addr_t phys, int prot, int stage)
1413 {
1414         int ret = 0;
1415         pud_t *pud;
1416         unsigned long next;
1417
1418 #ifndef __PAGETABLE_PUD_FOLDED
1419         if (pgd_none(*pgd)) {
1420                 pud = (pud_t *)get_zeroed_page(GFP_ATOMIC);
1421                 if (!pud)
1422                         return -ENOMEM;
1423
1424                 arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE);
1425                 pgd_populate(NULL, pgd, pud);
1426                 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1427
1428                 pud += pud_index(addr);
1429         } else
1430 #endif
1431                 pud = pud_offset(pgd, addr);
1432
1433         do {
1434                 next = pud_addr_end(addr, end);
1435                 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1436                                               prot, stage);
1437                 phys += next - addr;
1438         } while (pud++, addr = next, addr < end);
1439
1440         return ret;
1441 }
1442
1443 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1444                                    unsigned long iova, phys_addr_t paddr,
1445                                    size_t size, int prot)
1446 {
1447         int ret, stage;
1448         unsigned long end;
1449         phys_addr_t input_mask, output_mask;
1450         struct arm_smmu_device *smmu = smmu_domain->smmu;
1451         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1452         pgd_t *pgd = cfg->pgd;
1453         unsigned long flags;
1454
1455         if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
1456                 stage = 2;
1457                 output_mask = (1ULL << smmu->s2_output_size) - 1;
1458         } else {
1459                 stage = 1;
1460                 output_mask = (1ULL << smmu->s1_output_size) - 1;
1461         }
1462
1463         if (!pgd)
1464                 return -EINVAL;
1465
1466         if (size & ~PAGE_MASK)
1467                 return -EINVAL;
1468
1469         input_mask = (1ULL << smmu->input_size) - 1;
1470         if ((phys_addr_t)iova & ~input_mask)
1471                 return -ERANGE;
1472
1473         if (paddr & ~output_mask)
1474                 return -ERANGE;
1475
1476         spin_lock_irqsave(&smmu_domain->lock, flags);
1477         pgd += pgd_index(iova);
1478         end = iova + size;
1479         do {
1480                 unsigned long next = pgd_addr_end(iova, end);
1481
1482                 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1483                                               prot, stage);
1484                 if (ret)
1485                         goto out_unlock;
1486
1487                 paddr += next - iova;
1488                 iova = next;
1489         } while (pgd++, iova != end);
1490
1491 out_unlock:
1492         spin_unlock_irqrestore(&smmu_domain->lock, flags);
1493
1494         return ret;
1495 }
1496
1497 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1498                         phys_addr_t paddr, size_t size, int prot)
1499 {
1500         struct arm_smmu_domain *smmu_domain = domain->priv;
1501
1502         if (!smmu_domain)
1503                 return -ENODEV;
1504
1505         return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
1506 }
1507
1508 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1509                              size_t size)
1510 {
1511         int ret;
1512         struct arm_smmu_domain *smmu_domain = domain->priv;
1513
1514         ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1515         arm_smmu_tlb_inv_context(smmu_domain);
1516         return ret ? 0 : size;
1517 }
1518
1519 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1520                                          dma_addr_t iova)
1521 {
1522         pgd_t *pgdp, pgd;
1523         pud_t pud;
1524         pmd_t pmd;
1525         pte_t pte;
1526         struct arm_smmu_domain *smmu_domain = domain->priv;
1527         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1528
1529         pgdp = cfg->pgd;
1530         if (!pgdp)
1531                 return 0;
1532
1533         pgd = *(pgdp + pgd_index(iova));
1534         if (pgd_none(pgd))
1535                 return 0;
1536
1537         pud = *pud_offset(&pgd, iova);
1538         if (pud_none(pud))
1539                 return 0;
1540
1541         pmd = *pmd_offset(&pud, iova);
1542         if (pmd_none(pmd))
1543                 return 0;
1544
1545         pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1546         if (pte_none(pte))
1547                 return 0;
1548
1549         return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1550 }
1551
1552 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1553                                    unsigned long cap)
1554 {
1555         struct arm_smmu_domain *smmu_domain = domain->priv;
1556         struct arm_smmu_device *smmu = smmu_domain->smmu;
1557         u32 features = smmu ? smmu->features : 0;
1558
1559         switch (cap) {
1560         case IOMMU_CAP_CACHE_COHERENCY:
1561                 return features & ARM_SMMU_FEAT_COHERENT_WALK;
1562         case IOMMU_CAP_INTR_REMAP:
1563                 return 1; /* MSIs are just memory writes */
1564         default:
1565                 return 0;
1566         }
1567 }
1568
1569 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1570 {
1571         *((u16 *)data) = alias;
1572         return 0; /* Continue walking */
1573 }
1574
1575 static void __arm_smmu_release_pci_iommudata(void *data)
1576 {
1577         kfree(data);
1578 }
1579
1580 static int arm_smmu_add_device(struct device *dev)
1581 {
1582         struct arm_smmu_device *smmu;
1583         struct arm_smmu_master_cfg *cfg;
1584         struct iommu_group *group;
1585         void (*releasefn)(void *) = NULL;
1586         int ret;
1587
1588         smmu = find_smmu_for_device(dev);
1589         if (!smmu)
1590                 return -ENODEV;
1591
1592         group = iommu_group_alloc();
1593         if (IS_ERR(group)) {
1594                 dev_err(dev, "Failed to allocate IOMMU group\n");
1595                 return PTR_ERR(group);
1596         }
1597
1598         if (dev_is_pci(dev)) {
1599                 struct pci_dev *pdev = to_pci_dev(dev);
1600
1601                 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1602                 if (!cfg) {
1603                         ret = -ENOMEM;
1604                         goto out_put_group;
1605                 }
1606
1607                 cfg->num_streamids = 1;
1608                 /*
1609                  * Assume Stream ID == Requester ID for now.
1610                  * We need a way to describe the ID mappings in FDT.
1611                  */
1612                 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid,
1613                                        &cfg->streamids[0]);
1614                 releasefn = __arm_smmu_release_pci_iommudata;
1615         } else {
1616                 struct arm_smmu_master *master;
1617
1618                 master = find_smmu_master(smmu, dev->of_node);
1619                 if (!master) {
1620                         ret = -ENODEV;
1621                         goto out_put_group;
1622                 }
1623
1624                 cfg = &master->cfg;
1625         }
1626
1627         iommu_group_set_iommudata(group, cfg, releasefn);
1628         ret = iommu_group_add_device(group, dev);
1629
1630 out_put_group:
1631         iommu_group_put(group);
1632         return ret;
1633 }
1634
1635 static void arm_smmu_remove_device(struct device *dev)
1636 {
1637         iommu_group_remove_device(dev);
1638 }
1639
1640 static const struct iommu_ops arm_smmu_ops = {
1641         .domain_init    = arm_smmu_domain_init,
1642         .domain_destroy = arm_smmu_domain_destroy,
1643         .attach_dev     = arm_smmu_attach_dev,
1644         .detach_dev     = arm_smmu_detach_dev,
1645         .map            = arm_smmu_map,
1646         .unmap          = arm_smmu_unmap,
1647         .iova_to_phys   = arm_smmu_iova_to_phys,
1648         .domain_has_cap = arm_smmu_domain_has_cap,
1649         .add_device     = arm_smmu_add_device,
1650         .remove_device  = arm_smmu_remove_device,
1651         .pgsize_bitmap  = (SECTION_SIZE |
1652                            ARM_SMMU_PTE_CONT_SIZE |
1653                            PAGE_SIZE),
1654 };
1655
1656 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1657 {
1658         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1659         void __iomem *cb_base;
1660         int i = 0;
1661         u32 reg;
1662
1663         /* clear global FSR */
1664         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1665         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1666
1667         /* Mark all SMRn as invalid and all S2CRn as bypass */
1668         for (i = 0; i < smmu->num_mapping_groups; ++i) {
1669                 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
1670                 writel_relaxed(S2CR_TYPE_BYPASS,
1671                         gr0_base + ARM_SMMU_GR0_S2CR(i));
1672         }
1673
1674         /* Make sure all context banks are disabled and clear CB_FSR  */
1675         for (i = 0; i < smmu->num_context_banks; ++i) {
1676                 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1677                 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1678                 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1679         }
1680
1681         /* Invalidate the TLB, just in case */
1682         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1683         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1684         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1685
1686         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1687
1688         /* Enable fault reporting */
1689         reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1690
1691         /* Disable TLB broadcasting. */
1692         reg |= (sCR0_VMIDPNE | sCR0_PTM);
1693
1694         /* Enable client access, but bypass when no mapping is found */
1695         reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1696
1697         /* Disable forced broadcasting */
1698         reg &= ~sCR0_FB;
1699
1700         /* Don't upgrade barriers */
1701         reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1702
1703         /* Push the button */
1704         arm_smmu_tlb_sync(smmu);
1705         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1706 }
1707
1708 static int arm_smmu_id_size_to_bits(int size)
1709 {
1710         switch (size) {
1711         case 0:
1712                 return 32;
1713         case 1:
1714                 return 36;
1715         case 2:
1716                 return 40;
1717         case 3:
1718                 return 42;
1719         case 4:
1720                 return 44;
1721         case 5:
1722         default:
1723                 return 48;
1724         }
1725 }
1726
1727 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1728 {
1729         unsigned long size;
1730         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1731         u32 id;
1732
1733         dev_notice(smmu->dev, "probing hardware configuration...\n");
1734
1735         /* Primecell ID */
1736         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1737         smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1738         dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1739
1740         /* ID0 */
1741         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1742 #ifndef CONFIG_64BIT
1743         if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1744                 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1745                 return -ENODEV;
1746         }
1747 #endif
1748
1749         /* Restrict available stages based on module parameter */
1750         if (force_stage == 1)
1751                 id &= ~(ID0_S2TS | ID0_NTS);
1752         else if (force_stage == 2)
1753                 id &= ~(ID0_S1TS | ID0_NTS);
1754
1755         if (id & ID0_S1TS) {
1756                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1757                 dev_notice(smmu->dev, "\tstage 1 translation\n");
1758         }
1759
1760         if (id & ID0_S2TS) {
1761                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1762                 dev_notice(smmu->dev, "\tstage 2 translation\n");
1763         }
1764
1765         if (id & ID0_NTS) {
1766                 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1767                 dev_notice(smmu->dev, "\tnested translation\n");
1768         }
1769
1770         if (!(smmu->features &
1771                 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
1772                 dev_err(smmu->dev, "\tno translation support!\n");
1773                 return -ENODEV;
1774         }
1775
1776         if (id & ID0_CTTW) {
1777                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1778                 dev_notice(smmu->dev, "\tcoherent table walk\n");
1779         }
1780
1781         if (id & ID0_SMS) {
1782                 u32 smr, sid, mask;
1783
1784                 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1785                 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1786                                            ID0_NUMSMRG_MASK;
1787                 if (smmu->num_mapping_groups == 0) {
1788                         dev_err(smmu->dev,
1789                                 "stream-matching supported, but no SMRs present!\n");
1790                         return -ENODEV;
1791                 }
1792
1793                 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1794                 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1795                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1796                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1797
1798                 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1799                 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1800                 if ((mask & sid) != sid) {
1801                         dev_err(smmu->dev,
1802                                 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1803                                 mask, sid);
1804                         return -ENODEV;
1805                 }
1806
1807                 dev_notice(smmu->dev,
1808                            "\tstream matching with %u register groups, mask 0x%x",
1809                            smmu->num_mapping_groups, mask);
1810         } else {
1811                 smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
1812                                            ID0_NUMSIDB_MASK;
1813         }
1814
1815         /* ID1 */
1816         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1817         smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
1818
1819         /* Check for size mismatch of SMMU address space from mapped region */
1820         size = 1 <<
1821                 (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1822         size *= 2 << smmu->pgshift;
1823         if (smmu->size != size)
1824                 dev_warn(smmu->dev,
1825                         "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1826                         size, smmu->size);
1827
1828         smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1829                                       ID1_NUMS2CB_MASK;
1830         smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1831         if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1832                 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1833                 return -ENODEV;
1834         }
1835         dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1836                    smmu->num_context_banks, smmu->num_s2_context_banks);
1837
1838         /* ID2 */
1839         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1840         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1841
1842         /*
1843          * Stage-1 output limited by stage-2 input size due to pgd
1844          * allocation (PTRS_PER_PGD).
1845          */
1846         if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
1847 #ifdef CONFIG_64BIT
1848                 smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
1849 #else
1850                 smmu->s1_output_size = min(32UL, size);
1851 #endif
1852         } else {
1853                 smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT,
1854                                              size);
1855         }
1856
1857         /* The stage-2 output mask is also applied for bypass */
1858         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1859         smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
1860
1861         if (smmu->version == 1) {
1862                 smmu->input_size = 32;
1863         } else {
1864 #ifdef CONFIG_64BIT
1865                 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1866                 size = min(VA_BITS, arm_smmu_id_size_to_bits(size));
1867 #else
1868                 size = 32;
1869 #endif
1870                 smmu->input_size = size;
1871
1872                 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1873                     (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1874                     (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1875                         dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1876                                 PAGE_SIZE);
1877                         return -ENODEV;
1878                 }
1879         }
1880
1881         dev_notice(smmu->dev,
1882                    "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1883                    smmu->input_size, smmu->s1_output_size,
1884                    smmu->s2_output_size);
1885         return 0;
1886 }
1887
1888 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1889 {
1890         struct resource *res;
1891         struct arm_smmu_device *smmu;
1892         struct device *dev = &pdev->dev;
1893         struct rb_node *node;
1894         struct of_phandle_args masterspec;
1895         int num_irqs, i, err;
1896
1897         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1898         if (!smmu) {
1899                 dev_err(dev, "failed to allocate arm_smmu_device\n");
1900                 return -ENOMEM;
1901         }
1902         smmu->dev = dev;
1903
1904         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1905         smmu->base = devm_ioremap_resource(dev, res);
1906         if (IS_ERR(smmu->base))
1907                 return PTR_ERR(smmu->base);
1908         smmu->size = resource_size(res);
1909
1910         if (of_property_read_u32(dev->of_node, "#global-interrupts",
1911                                  &smmu->num_global_irqs)) {
1912                 dev_err(dev, "missing #global-interrupts property\n");
1913                 return -ENODEV;
1914         }
1915
1916         num_irqs = 0;
1917         while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1918                 num_irqs++;
1919                 if (num_irqs > smmu->num_global_irqs)
1920                         smmu->num_context_irqs++;
1921         }
1922
1923         if (!smmu->num_context_irqs) {
1924                 dev_err(dev, "found %d interrupts but expected at least %d\n",
1925                         num_irqs, smmu->num_global_irqs + 1);
1926                 return -ENODEV;
1927         }
1928
1929         smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1930                                   GFP_KERNEL);
1931         if (!smmu->irqs) {
1932                 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1933                 return -ENOMEM;
1934         }
1935
1936         for (i = 0; i < num_irqs; ++i) {
1937                 int irq = platform_get_irq(pdev, i);
1938
1939                 if (irq < 0) {
1940                         dev_err(dev, "failed to get irq index %d\n", i);
1941                         return -ENODEV;
1942                 }
1943                 smmu->irqs[i] = irq;
1944         }
1945
1946         err = arm_smmu_device_cfg_probe(smmu);
1947         if (err)
1948                 return err;
1949
1950         i = 0;
1951         smmu->masters = RB_ROOT;
1952         while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1953                                            "#stream-id-cells", i,
1954                                            &masterspec)) {
1955                 err = register_smmu_master(smmu, dev, &masterspec);
1956                 if (err) {
1957                         dev_err(dev, "failed to add master %s\n",
1958                                 masterspec.np->name);
1959                         goto out_put_masters;
1960                 }
1961
1962                 i++;
1963         }
1964         dev_notice(dev, "registered %d master devices\n", i);
1965
1966         parse_driver_options(smmu);
1967
1968         if (smmu->version > 1 &&
1969             smmu->num_context_banks != smmu->num_context_irqs) {
1970                 dev_err(dev,
1971                         "found only %d context interrupt(s) but %d required\n",
1972                         smmu->num_context_irqs, smmu->num_context_banks);
1973                 err = -ENODEV;
1974                 goto out_put_masters;
1975         }
1976
1977         for (i = 0; i < smmu->num_global_irqs; ++i) {
1978                 err = request_irq(smmu->irqs[i],
1979                                   arm_smmu_global_fault,
1980                                   IRQF_SHARED,
1981                                   "arm-smmu global fault",
1982                                   smmu);
1983                 if (err) {
1984                         dev_err(dev, "failed to request global IRQ %d (%u)\n",
1985                                 i, smmu->irqs[i]);
1986                         goto out_free_irqs;
1987                 }
1988         }
1989
1990         INIT_LIST_HEAD(&smmu->list);
1991         spin_lock(&arm_smmu_devices_lock);
1992         list_add(&smmu->list, &arm_smmu_devices);
1993         spin_unlock(&arm_smmu_devices_lock);
1994
1995         arm_smmu_device_reset(smmu);
1996         return 0;
1997
1998 out_free_irqs:
1999         while (i--)
2000                 free_irq(smmu->irqs[i], smmu);
2001
2002 out_put_masters:
2003         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
2004                 struct arm_smmu_master *master
2005                         = container_of(node, struct arm_smmu_master, node);
2006                 of_node_put(master->of_node);
2007         }
2008
2009         return err;
2010 }
2011
2012 static int arm_smmu_device_remove(struct platform_device *pdev)
2013 {
2014         int i;
2015         struct device *dev = &pdev->dev;
2016         struct arm_smmu_device *curr, *smmu = NULL;
2017         struct rb_node *node;
2018
2019         spin_lock(&arm_smmu_devices_lock);
2020         list_for_each_entry(curr, &arm_smmu_devices, list) {
2021                 if (curr->dev == dev) {
2022                         smmu = curr;
2023                         list_del(&smmu->list);
2024                         break;
2025                 }
2026         }
2027         spin_unlock(&arm_smmu_devices_lock);
2028
2029         if (!smmu)
2030                 return -ENODEV;
2031
2032         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
2033                 struct arm_smmu_master *master
2034                         = container_of(node, struct arm_smmu_master, node);
2035                 of_node_put(master->of_node);
2036         }
2037
2038         if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
2039                 dev_err(dev, "removing device with active domains!\n");
2040
2041         for (i = 0; i < smmu->num_global_irqs; ++i)
2042                 free_irq(smmu->irqs[i], smmu);
2043
2044         /* Turn the thing off */
2045         writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
2046         return 0;
2047 }
2048
2049 #ifdef CONFIG_OF
2050 static struct of_device_id arm_smmu_of_match[] = {
2051         { .compatible = "arm,smmu-v1", },
2052         { .compatible = "arm,smmu-v2", },
2053         { .compatible = "arm,mmu-400", },
2054         { .compatible = "arm,mmu-500", },
2055         { },
2056 };
2057 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
2058 #endif
2059
2060 static struct platform_driver arm_smmu_driver = {
2061         .driver = {
2062                 .owner          = THIS_MODULE,
2063                 .name           = "arm-smmu",
2064                 .of_match_table = of_match_ptr(arm_smmu_of_match),
2065         },
2066         .probe  = arm_smmu_device_dt_probe,
2067         .remove = arm_smmu_device_remove,
2068 };
2069
2070 static int __init arm_smmu_init(void)
2071 {
2072         int ret;
2073
2074         ret = platform_driver_register(&arm_smmu_driver);
2075         if (ret)
2076                 return ret;
2077
2078         /* Oh, for a proper bus abstraction */
2079         if (!iommu_present(&platform_bus_type))
2080                 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2081
2082 #ifdef CONFIG_ARM_AMBA
2083         if (!iommu_present(&amba_bustype))
2084                 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2085 #endif
2086
2087 #ifdef CONFIG_PCI
2088         if (!iommu_present(&pci_bus_type))
2089                 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2090 #endif
2091
2092         return 0;
2093 }
2094
2095 static void __exit arm_smmu_exit(void)
2096 {
2097         return platform_driver_unregister(&arm_smmu_driver);
2098 }
2099
2100 subsys_initcall(arm_smmu_init);
2101 module_exit(arm_smmu_exit);
2102
2103 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2104 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2105 MODULE_LICENSE("GPL v2");