2 * IOMMU API for ARM architected SMMU implementations.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 * Copyright (C) 2013 ARM Limited
19 * Author: Will Deacon <will.deacon@arm.com>
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - 4k and 64k pages, with contiguous pte hints.
27 * - Up to 42-bit addressing (dependent on VA_BITS)
28 * - Context fault reporting
31 #define pr_fmt(fmt) "arm-smmu: " fmt
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/err.h>
36 #include <linux/interrupt.h>
38 #include <linux/iommu.h>
40 #include <linux/module.h>
42 #include <linux/pci.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <linux/spinlock.h>
47 #include <linux/amba/bus.h>
49 #include <asm/pgalloc.h>
51 /* Maximum number of stream IDs assigned to a single device */
52 #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
54 /* Maximum number of context banks per SMMU */
55 #define ARM_SMMU_MAX_CBS 128
57 /* Maximum number of mapping groups per SMMU */
58 #define ARM_SMMU_MAX_SMRS 128
60 /* SMMU global address space */
61 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
62 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
65 * SMMU global address space with conditional offset to access secure
66 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
69 #define ARM_SMMU_GR0_NS(smmu) \
71 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
75 #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53)
76 #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
77 #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10)
78 #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8)
79 #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8)
80 #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8)
81 #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0)
83 #if PAGE_SIZE == SZ_4K
84 #define ARM_SMMU_PTE_CONT_ENTRIES 16
85 #elif PAGE_SIZE == SZ_64K
86 #define ARM_SMMU_PTE_CONT_ENTRIES 32
88 #define ARM_SMMU_PTE_CONT_ENTRIES 1
91 #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
92 #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1))
95 #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6)
96 #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6)
97 #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2
98 #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11)
101 #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6)
102 #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6)
103 #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6)
104 #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2)
105 #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2)
106 #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2)
108 /* Configuration registers */
109 #define ARM_SMMU_GR0_sCR0 0x0
110 #define sCR0_CLIENTPD (1 << 0)
111 #define sCR0_GFRE (1 << 1)
112 #define sCR0_GFIE (1 << 2)
113 #define sCR0_GCFGFRE (1 << 4)
114 #define sCR0_GCFGFIE (1 << 5)
115 #define sCR0_USFCFG (1 << 10)
116 #define sCR0_VMIDPNE (1 << 11)
117 #define sCR0_PTM (1 << 12)
118 #define sCR0_FB (1 << 13)
119 #define sCR0_BSU_SHIFT 14
120 #define sCR0_BSU_MASK 0x3
122 /* Identification registers */
123 #define ARM_SMMU_GR0_ID0 0x20
124 #define ARM_SMMU_GR0_ID1 0x24
125 #define ARM_SMMU_GR0_ID2 0x28
126 #define ARM_SMMU_GR0_ID3 0x2c
127 #define ARM_SMMU_GR0_ID4 0x30
128 #define ARM_SMMU_GR0_ID5 0x34
129 #define ARM_SMMU_GR0_ID6 0x38
130 #define ARM_SMMU_GR0_ID7 0x3c
131 #define ARM_SMMU_GR0_sGFSR 0x48
132 #define ARM_SMMU_GR0_sGFSYNR0 0x50
133 #define ARM_SMMU_GR0_sGFSYNR1 0x54
134 #define ARM_SMMU_GR0_sGFSYNR2 0x58
135 #define ARM_SMMU_GR0_PIDR0 0xfe0
136 #define ARM_SMMU_GR0_PIDR1 0xfe4
137 #define ARM_SMMU_GR0_PIDR2 0xfe8
139 #define ID0_S1TS (1 << 30)
140 #define ID0_S2TS (1 << 29)
141 #define ID0_NTS (1 << 28)
142 #define ID0_SMS (1 << 27)
143 #define ID0_PTFS_SHIFT 24
144 #define ID0_PTFS_MASK 0x2
145 #define ID0_PTFS_V8_ONLY 0x2
146 #define ID0_CTTW (1 << 14)
147 #define ID0_NUMIRPT_SHIFT 16
148 #define ID0_NUMIRPT_MASK 0xff
149 #define ID0_NUMSIDB_SHIFT 9
150 #define ID0_NUMSIDB_MASK 0xf
151 #define ID0_NUMSMRG_SHIFT 0
152 #define ID0_NUMSMRG_MASK 0xff
154 #define ID1_PAGESIZE (1 << 31)
155 #define ID1_NUMPAGENDXB_SHIFT 28
156 #define ID1_NUMPAGENDXB_MASK 7
157 #define ID1_NUMS2CB_SHIFT 16
158 #define ID1_NUMS2CB_MASK 0xff
159 #define ID1_NUMCB_SHIFT 0
160 #define ID1_NUMCB_MASK 0xff
162 #define ID2_OAS_SHIFT 4
163 #define ID2_OAS_MASK 0xf
164 #define ID2_IAS_SHIFT 0
165 #define ID2_IAS_MASK 0xf
166 #define ID2_UBS_SHIFT 8
167 #define ID2_UBS_MASK 0xf
168 #define ID2_PTFS_4K (1 << 12)
169 #define ID2_PTFS_16K (1 << 13)
170 #define ID2_PTFS_64K (1 << 14)
172 #define PIDR2_ARCH_SHIFT 4
173 #define PIDR2_ARCH_MASK 0xf
175 /* Global TLB invalidation */
176 #define ARM_SMMU_GR0_STLBIALL 0x60
177 #define ARM_SMMU_GR0_TLBIVMID 0x64
178 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
179 #define ARM_SMMU_GR0_TLBIALLH 0x6c
180 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
181 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
182 #define sTLBGSTATUS_GSACTIVE (1 << 0)
183 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
185 /* Stream mapping registers */
186 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
187 #define SMR_VALID (1 << 31)
188 #define SMR_MASK_SHIFT 16
189 #define SMR_MASK_MASK 0x7fff
190 #define SMR_ID_SHIFT 0
191 #define SMR_ID_MASK 0x7fff
193 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
194 #define S2CR_CBNDX_SHIFT 0
195 #define S2CR_CBNDX_MASK 0xff
196 #define S2CR_TYPE_SHIFT 16
197 #define S2CR_TYPE_MASK 0x3
198 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
199 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
200 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
202 /* Context bank attribute registers */
203 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
204 #define CBAR_VMID_SHIFT 0
205 #define CBAR_VMID_MASK 0xff
206 #define CBAR_S1_BPSHCFG_SHIFT 8
207 #define CBAR_S1_BPSHCFG_MASK 3
208 #define CBAR_S1_BPSHCFG_NSH 3
209 #define CBAR_S1_MEMATTR_SHIFT 12
210 #define CBAR_S1_MEMATTR_MASK 0xf
211 #define CBAR_S1_MEMATTR_WB 0xf
212 #define CBAR_TYPE_SHIFT 16
213 #define CBAR_TYPE_MASK 0x3
214 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
215 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
216 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
217 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
218 #define CBAR_IRPTNDX_SHIFT 24
219 #define CBAR_IRPTNDX_MASK 0xff
221 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
222 #define CBA2R_RW64_32BIT (0 << 0)
223 #define CBA2R_RW64_64BIT (1 << 0)
225 /* Translation context bank */
226 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
227 #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize)
229 #define ARM_SMMU_CB_SCTLR 0x0
230 #define ARM_SMMU_CB_RESUME 0x8
231 #define ARM_SMMU_CB_TTBCR2 0x10
232 #define ARM_SMMU_CB_TTBR0_LO 0x20
233 #define ARM_SMMU_CB_TTBR0_HI 0x24
234 #define ARM_SMMU_CB_TTBCR 0x30
235 #define ARM_SMMU_CB_S1_MAIR0 0x38
236 #define ARM_SMMU_CB_FSR 0x58
237 #define ARM_SMMU_CB_FAR_LO 0x60
238 #define ARM_SMMU_CB_FAR_HI 0x64
239 #define ARM_SMMU_CB_FSYNR0 0x68
240 #define ARM_SMMU_CB_S1_TLBIASID 0x610
242 #define SCTLR_S1_ASIDPNE (1 << 12)
243 #define SCTLR_CFCFG (1 << 7)
244 #define SCTLR_CFIE (1 << 6)
245 #define SCTLR_CFRE (1 << 5)
246 #define SCTLR_E (1 << 4)
247 #define SCTLR_AFE (1 << 2)
248 #define SCTLR_TRE (1 << 1)
249 #define SCTLR_M (1 << 0)
250 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
252 #define RESUME_RETRY (0 << 0)
253 #define RESUME_TERMINATE (1 << 0)
255 #define TTBCR_EAE (1 << 31)
257 #define TTBCR_PASIZE_SHIFT 16
258 #define TTBCR_PASIZE_MASK 0x7
260 #define TTBCR_TG0_4K (0 << 14)
261 #define TTBCR_TG0_64K (1 << 14)
263 #define TTBCR_SH0_SHIFT 12
264 #define TTBCR_SH0_MASK 0x3
265 #define TTBCR_SH_NS 0
266 #define TTBCR_SH_OS 2
267 #define TTBCR_SH_IS 3
269 #define TTBCR_ORGN0_SHIFT 10
270 #define TTBCR_IRGN0_SHIFT 8
271 #define TTBCR_RGN_MASK 0x3
272 #define TTBCR_RGN_NC 0
273 #define TTBCR_RGN_WBWA 1
274 #define TTBCR_RGN_WT 2
275 #define TTBCR_RGN_WB 3
277 #define TTBCR_SL0_SHIFT 6
278 #define TTBCR_SL0_MASK 0x3
279 #define TTBCR_SL0_LVL_2 0
280 #define TTBCR_SL0_LVL_1 1
282 #define TTBCR_T1SZ_SHIFT 16
283 #define TTBCR_T0SZ_SHIFT 0
284 #define TTBCR_SZ_MASK 0xf
286 #define TTBCR2_SEP_SHIFT 15
287 #define TTBCR2_SEP_MASK 0x7
289 #define TTBCR2_PASIZE_SHIFT 0
290 #define TTBCR2_PASIZE_MASK 0x7
292 /* Common definitions for PASize and SEP fields */
293 #define TTBCR2_ADDR_32 0
294 #define TTBCR2_ADDR_36 1
295 #define TTBCR2_ADDR_40 2
296 #define TTBCR2_ADDR_42 3
297 #define TTBCR2_ADDR_44 4
298 #define TTBCR2_ADDR_48 5
300 #define TTBRn_HI_ASID_SHIFT 16
302 #define MAIR_ATTR_SHIFT(n) ((n) << 3)
303 #define MAIR_ATTR_MASK 0xff
304 #define MAIR_ATTR_DEVICE 0x04
305 #define MAIR_ATTR_NC 0x44
306 #define MAIR_ATTR_WBRWA 0xff
307 #define MAIR_ATTR_IDX_NC 0
308 #define MAIR_ATTR_IDX_CACHE 1
309 #define MAIR_ATTR_IDX_DEV 2
311 #define FSR_MULTI (1 << 31)
312 #define FSR_SS (1 << 30)
313 #define FSR_UUT (1 << 8)
314 #define FSR_ASF (1 << 7)
315 #define FSR_TLBLKF (1 << 6)
316 #define FSR_TLBMCF (1 << 5)
317 #define FSR_EF (1 << 4)
318 #define FSR_PF (1 << 3)
319 #define FSR_AFF (1 << 2)
320 #define FSR_TF (1 << 1)
322 #define FSR_IGN (FSR_AFF | FSR_ASF | \
323 FSR_TLBMCF | FSR_TLBLKF)
324 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
325 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
327 #define FSYNR0_WNR (1 << 4)
329 struct arm_smmu_smr {
335 struct arm_smmu_master_cfg {
337 u16 streamids[MAX_MASTER_STREAMIDS];
338 struct arm_smmu_smr *smrs;
341 struct arm_smmu_master {
342 struct device_node *of_node;
344 struct arm_smmu_master_cfg cfg;
347 struct arm_smmu_device {
352 unsigned long pagesize;
354 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
355 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
356 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
357 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
358 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
361 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
365 u32 num_context_banks;
366 u32 num_s2_context_banks;
367 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
370 u32 num_mapping_groups;
371 DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
373 unsigned long input_size;
374 unsigned long s1_output_size;
375 unsigned long s2_output_size;
378 u32 num_context_irqs;
381 struct list_head list;
382 struct rb_root masters;
385 struct arm_smmu_cfg {
391 #define INVALID_IRPTNDX 0xff
393 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
394 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
396 struct arm_smmu_domain {
397 struct arm_smmu_device *smmu;
398 struct arm_smmu_cfg cfg;
402 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
403 static LIST_HEAD(arm_smmu_devices);
405 struct arm_smmu_option_prop {
410 static struct arm_smmu_option_prop arm_smmu_options[] = {
411 { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
415 static void parse_driver_options(struct arm_smmu_device *smmu)
420 if (of_property_read_bool(smmu->dev->of_node,
421 arm_smmu_options[i].prop)) {
422 smmu->options |= arm_smmu_options[i].opt;
423 dev_notice(smmu->dev, "option %s\n",
424 arm_smmu_options[i].prop);
426 } while (arm_smmu_options[++i].opt);
429 static struct device *dev_get_master_dev(struct device *dev)
431 if (dev_is_pci(dev)) {
432 struct pci_bus *bus = to_pci_dev(dev)->bus;
434 while (!pci_is_root_bus(bus))
436 return bus->bridge->parent;
442 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
443 struct device_node *dev_node)
445 struct rb_node *node = smmu->masters.rb_node;
448 struct arm_smmu_master *master;
450 master = container_of(node, struct arm_smmu_master, node);
452 if (dev_node < master->of_node)
453 node = node->rb_left;
454 else if (dev_node > master->of_node)
455 node = node->rb_right;
463 static struct arm_smmu_master_cfg *
464 find_smmu_master_cfg(struct arm_smmu_device *smmu, struct device *dev)
466 struct arm_smmu_master *master;
469 return dev->archdata.iommu;
471 master = find_smmu_master(smmu, dev->of_node);
472 return master ? &master->cfg : NULL;
475 static int insert_smmu_master(struct arm_smmu_device *smmu,
476 struct arm_smmu_master *master)
478 struct rb_node **new, *parent;
480 new = &smmu->masters.rb_node;
483 struct arm_smmu_master *this
484 = container_of(*new, struct arm_smmu_master, node);
487 if (master->of_node < this->of_node)
488 new = &((*new)->rb_left);
489 else if (master->of_node > this->of_node)
490 new = &((*new)->rb_right);
495 rb_link_node(&master->node, parent, new);
496 rb_insert_color(&master->node, &smmu->masters);
500 static int register_smmu_master(struct arm_smmu_device *smmu,
502 struct of_phandle_args *masterspec)
505 struct arm_smmu_master *master;
507 master = find_smmu_master(smmu, masterspec->np);
510 "rejecting multiple registrations for master device %s\n",
511 masterspec->np->name);
515 if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
517 "reached maximum number (%d) of stream IDs for master device %s\n",
518 MAX_MASTER_STREAMIDS, masterspec->np->name);
522 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
526 master->of_node = masterspec->np;
527 master->cfg.num_streamids = masterspec->args_count;
529 for (i = 0; i < master->cfg.num_streamids; ++i) {
530 u16 streamid = masterspec->args[i];
532 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
533 (streamid >= smmu->num_mapping_groups)) {
535 "stream ID for master device %s greater than maximum allowed (%d)\n",
536 masterspec->np->name, smmu->num_mapping_groups);
539 master->cfg.streamids[i] = streamid;
541 return insert_smmu_master(smmu, master);
544 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
546 struct arm_smmu_device *smmu;
547 struct arm_smmu_master *master = NULL;
548 struct device_node *dev_node = dev_get_master_dev(dev)->of_node;
550 spin_lock(&arm_smmu_devices_lock);
551 list_for_each_entry(smmu, &arm_smmu_devices, list) {
552 master = find_smmu_master(smmu, dev_node);
556 spin_unlock(&arm_smmu_devices_lock);
558 return master ? smmu : NULL;
561 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
566 idx = find_next_zero_bit(map, end, start);
569 } while (test_and_set_bit(idx, map));
574 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
579 /* Wait for any pending TLB invalidations to complete */
580 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
583 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
585 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
586 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
587 & sTLBGSTATUS_GSACTIVE) {
589 if (++count == TLB_LOOP_TIMEOUT) {
590 dev_err_ratelimited(smmu->dev,
591 "TLB sync timed out -- SMMU may be deadlocked\n");
598 static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain)
600 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
601 struct arm_smmu_device *smmu = smmu_domain->smmu;
602 void __iomem *base = ARM_SMMU_GR0(smmu);
603 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
606 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
607 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
608 base + ARM_SMMU_CB_S1_TLBIASID);
610 base = ARM_SMMU_GR0(smmu);
611 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
612 base + ARM_SMMU_GR0_TLBIVMID);
615 arm_smmu_tlb_sync(smmu);
618 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
621 u32 fsr, far, fsynr, resume;
623 struct iommu_domain *domain = dev;
624 struct arm_smmu_domain *smmu_domain = domain->priv;
625 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
626 struct arm_smmu_device *smmu = smmu_domain->smmu;
627 void __iomem *cb_base;
629 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
630 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
632 if (!(fsr & FSR_FAULT))
636 dev_err_ratelimited(smmu->dev,
637 "Unexpected context fault (fsr 0x%x)\n",
640 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
641 flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
643 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
646 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
647 iova |= ((unsigned long)far << 32);
650 if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
652 resume = RESUME_RETRY;
654 dev_err_ratelimited(smmu->dev,
655 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
656 iova, fsynr, cfg->cbndx);
658 resume = RESUME_TERMINATE;
661 /* Clear the faulting FSR */
662 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
664 /* Retry or terminate any stalled transactions */
666 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
671 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
673 u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
674 struct arm_smmu_device *smmu = dev;
675 void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
677 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
678 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
679 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
680 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
685 dev_err_ratelimited(smmu->dev,
686 "Unexpected global fault, this could be serious\n");
687 dev_err_ratelimited(smmu->dev,
688 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
689 gfsr, gfsynr0, gfsynr1, gfsynr2);
691 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
695 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
698 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
701 /* Ensure new page tables are visible to the hardware walker */
702 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
706 * If the SMMU can't walk tables in the CPU caches, treat them
707 * like non-coherent DMA since we need to flush the new entries
708 * all the way out to memory. There's no possibility of
709 * recursion here as the SMMU table walker will not be wired
710 * through another SMMU.
712 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
717 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
721 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
722 struct arm_smmu_device *smmu = smmu_domain->smmu;
723 void __iomem *cb_base, *gr0_base, *gr1_base;
725 gr0_base = ARM_SMMU_GR0(smmu);
726 gr1_base = ARM_SMMU_GR1(smmu);
727 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
728 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
732 if (smmu->version == 1)
733 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
736 * Use the weakest shareability/memory types, so they are
737 * overridden by the ttbcr/pte.
740 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
741 (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
743 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
745 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
747 if (smmu->version > 1) {
750 reg = CBA2R_RW64_64BIT;
752 reg = CBA2R_RW64_32BIT;
755 gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
758 switch (smmu->input_size) {
760 reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
763 reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
767 reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
770 reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
773 reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
776 reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
780 switch (smmu->s1_output_size) {
782 reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
785 reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
789 reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
792 reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
795 reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
798 reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
803 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
807 arm_smmu_flush_pgtable(smmu, cfg->pgd,
808 PTRS_PER_PGD * sizeof(pgd_t));
809 reg = __pa(cfg->pgd);
810 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
811 reg = (phys_addr_t)__pa(cfg->pgd) >> 32;
813 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
814 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
818 * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
820 if (smmu->version > 1) {
821 if (PAGE_SIZE == SZ_4K)
827 reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
829 switch (smmu->s2_output_size) {
831 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
834 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
837 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
840 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
843 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
846 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
850 reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT;
857 (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
858 (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
859 (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
862 reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
864 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
866 /* MAIR0 (stage-1 only) */
868 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
869 (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
870 (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
871 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
875 reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
877 reg |= SCTLR_S1_ASIDPNE;
881 writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
884 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
885 struct arm_smmu_device *smmu)
887 int irq, start, ret = 0;
889 struct arm_smmu_domain *smmu_domain = domain->priv;
890 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
892 spin_lock_irqsave(&smmu_domain->lock, flags);
893 if (smmu_domain->smmu)
896 if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
898 * We will likely want to change this if/when KVM gets
901 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
902 start = smmu->num_s2_context_banks;
903 } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) {
904 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
905 start = smmu->num_s2_context_banks;
907 cfg->cbar = CBAR_TYPE_S2_TRANS;
911 ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
912 smmu->num_context_banks);
913 if (IS_ERR_VALUE(ret))
917 if (smmu->version == 1) {
918 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
919 cfg->irptndx %= smmu->num_context_irqs;
921 cfg->irptndx = cfg->cbndx;
924 ACCESS_ONCE(smmu_domain->smmu) = smmu;
925 arm_smmu_init_context_bank(smmu_domain);
926 spin_unlock_irqrestore(&smmu_domain->lock, flags);
928 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
929 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
930 "arm-smmu-context-fault", domain);
931 if (IS_ERR_VALUE(ret)) {
932 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
934 cfg->irptndx = INVALID_IRPTNDX;
940 spin_unlock_irqrestore(&smmu_domain->lock, flags);
944 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
946 struct arm_smmu_domain *smmu_domain = domain->priv;
947 struct arm_smmu_device *smmu = smmu_domain->smmu;
948 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
949 void __iomem *cb_base;
955 /* Disable the context bank and nuke the TLB before freeing it. */
956 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
957 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
958 arm_smmu_tlb_inv_context(smmu_domain);
960 if (cfg->irptndx != INVALID_IRPTNDX) {
961 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
962 free_irq(irq, domain);
965 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
968 static int arm_smmu_domain_init(struct iommu_domain *domain)
970 struct arm_smmu_domain *smmu_domain;
974 * Allocate the domain and initialise some of its data structures.
975 * We can't really do anything meaningful until we've added a
978 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
982 pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
984 goto out_free_domain;
985 smmu_domain->cfg.pgd = pgd;
987 spin_lock_init(&smmu_domain->lock);
988 domain->priv = smmu_domain;
996 static void arm_smmu_free_ptes(pmd_t *pmd)
998 pgtable_t table = pmd_pgtable(*pmd);
1003 static void arm_smmu_free_pmds(pud_t *pud)
1006 pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
1009 for (i = 0; i < PTRS_PER_PMD; ++i) {
1013 arm_smmu_free_ptes(pmd);
1017 pmd_free(NULL, pmd_base);
1020 static void arm_smmu_free_puds(pgd_t *pgd)
1023 pud_t *pud, *pud_base = pud_offset(pgd, 0);
1026 for (i = 0; i < PTRS_PER_PUD; ++i) {
1030 arm_smmu_free_pmds(pud);
1034 pud_free(NULL, pud_base);
1037 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
1040 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1041 pgd_t *pgd, *pgd_base = cfg->pgd;
1044 * Recursively free the page tables for this domain. We don't
1045 * care about speculative TLB filling because the tables should
1046 * not be active in any context bank at this point (SCTLR.M is 0).
1049 for (i = 0; i < PTRS_PER_PGD; ++i) {
1052 arm_smmu_free_puds(pgd);
1059 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1061 struct arm_smmu_domain *smmu_domain = domain->priv;
1064 * Free the domain resources. We assume that all devices have
1065 * already been detached.
1067 arm_smmu_destroy_domain_context(domain);
1068 arm_smmu_free_pgtables(smmu_domain);
1072 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1073 struct arm_smmu_master_cfg *cfg)
1076 struct arm_smmu_smr *smrs;
1077 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1079 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1085 smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1087 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1088 cfg->num_streamids);
1092 /* Allocate the SMRs on the SMMU */
1093 for (i = 0; i < cfg->num_streamids; ++i) {
1094 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1095 smmu->num_mapping_groups);
1096 if (IS_ERR_VALUE(idx)) {
1097 dev_err(smmu->dev, "failed to allocate free SMR\n");
1101 smrs[i] = (struct arm_smmu_smr) {
1103 .mask = 0, /* We don't currently share SMRs */
1104 .id = cfg->streamids[i],
1108 /* It worked! Now, poke the actual hardware */
1109 for (i = 0; i < cfg->num_streamids; ++i) {
1110 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1111 smrs[i].mask << SMR_MASK_SHIFT;
1112 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1120 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1125 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1126 struct arm_smmu_master_cfg *cfg)
1129 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1130 struct arm_smmu_smr *smrs = cfg->smrs;
1135 /* Invalidate the SMRs before freeing back to the allocator */
1136 for (i = 0; i < cfg->num_streamids; ++i) {
1137 u8 idx = smrs[i].idx;
1139 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1140 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1147 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1148 struct arm_smmu_master_cfg *cfg)
1151 struct arm_smmu_device *smmu = smmu_domain->smmu;
1152 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1154 ret = arm_smmu_master_configure_smrs(smmu, cfg);
1158 for (i = 0; i < cfg->num_streamids; ++i) {
1161 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1162 s2cr = S2CR_TYPE_TRANS |
1163 (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1164 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1170 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1171 struct arm_smmu_master_cfg *cfg)
1174 struct arm_smmu_device *smmu = smmu_domain->smmu;
1175 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1178 * We *must* clear the S2CR first, because freeing the SMR means
1179 * that it can be re-allocated immediately.
1181 for (i = 0; i < cfg->num_streamids; ++i) {
1182 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1184 writel_relaxed(S2CR_TYPE_BYPASS,
1185 gr0_base + ARM_SMMU_GR0_S2CR(idx));
1188 arm_smmu_master_free_smrs(smmu, cfg);
1191 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1194 struct arm_smmu_domain *smmu_domain = domain->priv;
1195 struct arm_smmu_device *smmu, *dom_smmu;
1196 struct arm_smmu_master_cfg *cfg;
1198 smmu = dev_get_master_dev(dev)->archdata.iommu;
1200 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1205 * Sanity check the domain. We don't support domains across
1208 dom_smmu = ACCESS_ONCE(smmu_domain->smmu);
1210 /* Now that we have a master, we can finalise the domain */
1211 ret = arm_smmu_init_domain_context(domain, smmu);
1212 if (IS_ERR_VALUE(ret))
1215 dom_smmu = smmu_domain->smmu;
1218 if (dom_smmu != smmu) {
1220 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1221 dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1225 /* Looks ok, so add the device to the domain */
1226 cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
1230 return arm_smmu_domain_add_master(smmu_domain, cfg);
1233 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1235 struct arm_smmu_domain *smmu_domain = domain->priv;
1236 struct arm_smmu_master_cfg *cfg;
1238 cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
1240 arm_smmu_domain_remove_master(smmu_domain, cfg);
1243 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1246 return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1247 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1250 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1251 unsigned long addr, unsigned long end,
1252 unsigned long pfn, int prot, int stage)
1255 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
1257 if (pmd_none(*pmd)) {
1258 /* Allocate a new set of tables */
1259 pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
1264 arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
1265 pmd_populate(NULL, pmd, table);
1266 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1270 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1271 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
1272 pteval |= ARM_SMMU_PTE_AP_RDONLY;
1274 if (prot & IOMMU_CACHE)
1275 pteval |= (MAIR_ATTR_IDX_CACHE <<
1276 ARM_SMMU_PTE_ATTRINDX_SHIFT);
1278 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1279 if (prot & IOMMU_READ)
1280 pteval |= ARM_SMMU_PTE_HAP_READ;
1281 if (prot & IOMMU_WRITE)
1282 pteval |= ARM_SMMU_PTE_HAP_WRITE;
1283 if (prot & IOMMU_CACHE)
1284 pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1286 pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1289 /* If no access, create a faulting entry to avoid TLB fills */
1290 if (prot & IOMMU_EXEC)
1291 pteval &= ~ARM_SMMU_PTE_XN;
1292 else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
1293 pteval &= ~ARM_SMMU_PTE_PAGE;
1295 pteval |= ARM_SMMU_PTE_SH_IS;
1296 start = pmd_page_vaddr(*pmd) + pte_index(addr);
1300 * Install the page table entries. This is fairly complicated
1301 * since we attempt to make use of the contiguous hint in the
1302 * ptes where possible. The contiguous hint indicates a series
1303 * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1304 * contiguous region with the following constraints:
1306 * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1307 * - Each pte in the region has the contiguous hint bit set
1309 * This complicates unmapping (also handled by this code, when
1310 * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1311 * possible, yet highly unlikely, that a client may unmap only
1312 * part of a contiguous range. This requires clearing of the
1313 * contiguous hint bits in the range before installing the new
1316 * Note that re-mapping an address range without first unmapping
1317 * it is not supported, so TLB invalidation is not required here
1318 * and is instead performed at unmap and domain-init time.
1323 pteval &= ~ARM_SMMU_PTE_CONT;
1325 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1326 i = ARM_SMMU_PTE_CONT_ENTRIES;
1327 pteval |= ARM_SMMU_PTE_CONT;
1328 } else if (pte_val(*pte) &
1329 (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1332 unsigned long idx = pte_index(addr);
1334 idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1335 cont_start = pmd_page_vaddr(*pmd) + idx;
1336 for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1337 pte_val(*(cont_start + j)) &=
1340 arm_smmu_flush_pgtable(smmu, cont_start,
1342 ARM_SMMU_PTE_CONT_ENTRIES);
1346 *pte = pfn_pte(pfn, __pgprot(pteval));
1347 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1348 } while (addr != end);
1350 arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1354 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1355 unsigned long addr, unsigned long end,
1356 phys_addr_t phys, int prot, int stage)
1360 unsigned long next, pfn = __phys_to_pfn(phys);
1362 #ifndef __PAGETABLE_PMD_FOLDED
1363 if (pud_none(*pud)) {
1364 pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
1368 arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE);
1369 pud_populate(NULL, pud, pmd);
1370 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1372 pmd += pmd_index(addr);
1375 pmd = pmd_offset(pud, addr);
1378 next = pmd_addr_end(addr, end);
1379 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn,
1381 phys += next - addr;
1382 } while (pmd++, addr = next, addr < end);
1387 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1388 unsigned long addr, unsigned long end,
1389 phys_addr_t phys, int prot, int stage)
1395 #ifndef __PAGETABLE_PUD_FOLDED
1396 if (pgd_none(*pgd)) {
1397 pud = (pud_t *)get_zeroed_page(GFP_ATOMIC);
1401 arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE);
1402 pgd_populate(NULL, pgd, pud);
1403 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1405 pud += pud_index(addr);
1408 pud = pud_offset(pgd, addr);
1411 next = pud_addr_end(addr, end);
1412 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1414 phys += next - addr;
1415 } while (pud++, addr = next, addr < end);
1420 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1421 unsigned long iova, phys_addr_t paddr,
1422 size_t size, int prot)
1426 phys_addr_t input_mask, output_mask;
1427 struct arm_smmu_device *smmu = smmu_domain->smmu;
1428 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1429 pgd_t *pgd = cfg->pgd;
1430 unsigned long flags;
1432 if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
1434 output_mask = (1ULL << smmu->s2_output_size) - 1;
1437 output_mask = (1ULL << smmu->s1_output_size) - 1;
1443 if (size & ~PAGE_MASK)
1446 input_mask = (1ULL << smmu->input_size) - 1;
1447 if ((phys_addr_t)iova & ~input_mask)
1450 if (paddr & ~output_mask)
1453 spin_lock_irqsave(&smmu_domain->lock, flags);
1454 pgd += pgd_index(iova);
1457 unsigned long next = pgd_addr_end(iova, end);
1459 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1464 paddr += next - iova;
1466 } while (pgd++, iova != end);
1469 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1474 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1475 phys_addr_t paddr, size_t size, int prot)
1477 struct arm_smmu_domain *smmu_domain = domain->priv;
1482 return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
1485 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1489 struct arm_smmu_domain *smmu_domain = domain->priv;
1491 ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1492 arm_smmu_tlb_inv_context(smmu_domain);
1493 return ret ? 0 : size;
1496 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1503 struct arm_smmu_domain *smmu_domain = domain->priv;
1504 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1510 pgd = *(pgdp + pgd_index(iova));
1514 pud = *pud_offset(&pgd, iova);
1518 pmd = *pmd_offset(&pud, iova);
1522 pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1526 return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1529 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1532 struct arm_smmu_domain *smmu_domain = domain->priv;
1533 struct arm_smmu_device *smmu = smmu_domain->smmu;
1534 u32 features = smmu ? smmu->features : 0;
1537 case IOMMU_CAP_CACHE_COHERENCY:
1538 return features & ARM_SMMU_FEAT_COHERENT_WALK;
1539 case IOMMU_CAP_INTR_REMAP:
1540 return 1; /* MSIs are just memory writes */
1546 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1548 *((u16 *)data) = alias;
1549 return 0; /* Continue walking */
1552 static int arm_smmu_add_device(struct device *dev)
1554 struct arm_smmu_device *smmu;
1555 struct iommu_group *group;
1558 if (dev->archdata.iommu) {
1559 dev_warn(dev, "IOMMU driver already assigned to device\n");
1563 smmu = find_smmu_for_device(dev);
1567 group = iommu_group_alloc();
1568 if (IS_ERR(group)) {
1569 dev_err(dev, "Failed to allocate IOMMU group\n");
1570 return PTR_ERR(group);
1573 if (dev_is_pci(dev)) {
1574 struct arm_smmu_master_cfg *cfg;
1575 struct pci_dev *pdev = to_pci_dev(dev);
1577 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1583 cfg->num_streamids = 1;
1585 * Assume Stream ID == Requester ID for now.
1586 * We need a way to describe the ID mappings in FDT.
1588 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid,
1589 &cfg->streamids[0]);
1590 dev->archdata.iommu = cfg;
1592 dev->archdata.iommu = smmu;
1595 ret = iommu_group_add_device(group, dev);
1598 iommu_group_put(group);
1602 static void arm_smmu_remove_device(struct device *dev)
1604 if (dev_is_pci(dev))
1605 kfree(dev->archdata.iommu);
1607 dev->archdata.iommu = NULL;
1608 iommu_group_remove_device(dev);
1611 static const struct iommu_ops arm_smmu_ops = {
1612 .domain_init = arm_smmu_domain_init,
1613 .domain_destroy = arm_smmu_domain_destroy,
1614 .attach_dev = arm_smmu_attach_dev,
1615 .detach_dev = arm_smmu_detach_dev,
1616 .map = arm_smmu_map,
1617 .unmap = arm_smmu_unmap,
1618 .iova_to_phys = arm_smmu_iova_to_phys,
1619 .domain_has_cap = arm_smmu_domain_has_cap,
1620 .add_device = arm_smmu_add_device,
1621 .remove_device = arm_smmu_remove_device,
1622 .pgsize_bitmap = (SECTION_SIZE |
1623 ARM_SMMU_PTE_CONT_SIZE |
1627 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1629 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1630 void __iomem *cb_base;
1634 /* clear global FSR */
1635 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1636 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1638 /* Mark all SMRn as invalid and all S2CRn as bypass */
1639 for (i = 0; i < smmu->num_mapping_groups; ++i) {
1640 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
1641 writel_relaxed(S2CR_TYPE_BYPASS,
1642 gr0_base + ARM_SMMU_GR0_S2CR(i));
1645 /* Make sure all context banks are disabled and clear CB_FSR */
1646 for (i = 0; i < smmu->num_context_banks; ++i) {
1647 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1648 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1649 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1652 /* Invalidate the TLB, just in case */
1653 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1654 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1655 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1657 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1659 /* Enable fault reporting */
1660 reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1662 /* Disable TLB broadcasting. */
1663 reg |= (sCR0_VMIDPNE | sCR0_PTM);
1665 /* Enable client access, but bypass when no mapping is found */
1666 reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1668 /* Disable forced broadcasting */
1671 /* Don't upgrade barriers */
1672 reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1674 /* Push the button */
1675 arm_smmu_tlb_sync(smmu);
1676 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1679 static int arm_smmu_id_size_to_bits(int size)
1698 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1701 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1704 dev_notice(smmu->dev, "probing hardware configuration...\n");
1707 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1708 smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1709 dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1712 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1713 #ifndef CONFIG_64BIT
1714 if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1715 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1719 if (id & ID0_S1TS) {
1720 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1721 dev_notice(smmu->dev, "\tstage 1 translation\n");
1724 if (id & ID0_S2TS) {
1725 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1726 dev_notice(smmu->dev, "\tstage 2 translation\n");
1730 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1731 dev_notice(smmu->dev, "\tnested translation\n");
1734 if (!(smmu->features &
1735 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1736 ARM_SMMU_FEAT_TRANS_NESTED))) {
1737 dev_err(smmu->dev, "\tno translation support!\n");
1741 if (id & ID0_CTTW) {
1742 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1743 dev_notice(smmu->dev, "\tcoherent table walk\n");
1749 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1750 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1752 if (smmu->num_mapping_groups == 0) {
1754 "stream-matching supported, but no SMRs present!\n");
1758 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1759 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1760 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1761 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1763 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1764 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1765 if ((mask & sid) != sid) {
1767 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1772 dev_notice(smmu->dev,
1773 "\tstream matching with %u register groups, mask 0x%x",
1774 smmu->num_mapping_groups, mask);
1776 smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
1781 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1782 smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1784 /* Check for size mismatch of SMMU address space from mapped region */
1786 (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1787 size *= (smmu->pagesize << 1);
1788 if (smmu->size != size)
1790 "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1793 smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1795 smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1796 if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1797 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1800 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1801 smmu->num_context_banks, smmu->num_s2_context_banks);
1804 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1805 size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1808 * Stage-1 output limited by stage-2 input size due to pgd
1809 * allocation (PTRS_PER_PGD).
1811 if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
1813 smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
1815 smmu->s1_output_size = min(32UL, size);
1818 smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT,
1822 /* The stage-2 output mask is also applied for bypass */
1823 size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1824 smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
1826 if (smmu->version == 1) {
1827 smmu->input_size = 32;
1830 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1831 size = min(VA_BITS, arm_smmu_id_size_to_bits(size));
1835 smmu->input_size = size;
1837 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1838 (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1839 (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1840 dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1846 dev_notice(smmu->dev,
1847 "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1848 smmu->input_size, smmu->s1_output_size,
1849 smmu->s2_output_size);
1853 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1855 struct resource *res;
1856 struct arm_smmu_device *smmu;
1857 struct device *dev = &pdev->dev;
1858 struct rb_node *node;
1859 struct of_phandle_args masterspec;
1860 int num_irqs, i, err;
1862 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1864 dev_err(dev, "failed to allocate arm_smmu_device\n");
1869 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1870 smmu->base = devm_ioremap_resource(dev, res);
1871 if (IS_ERR(smmu->base))
1872 return PTR_ERR(smmu->base);
1873 smmu->size = resource_size(res);
1875 if (of_property_read_u32(dev->of_node, "#global-interrupts",
1876 &smmu->num_global_irqs)) {
1877 dev_err(dev, "missing #global-interrupts property\n");
1882 while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1884 if (num_irqs > smmu->num_global_irqs)
1885 smmu->num_context_irqs++;
1888 if (!smmu->num_context_irqs) {
1889 dev_err(dev, "found %d interrupts but expected at least %d\n",
1890 num_irqs, smmu->num_global_irqs + 1);
1894 smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1897 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1901 for (i = 0; i < num_irqs; ++i) {
1902 int irq = platform_get_irq(pdev, i);
1905 dev_err(dev, "failed to get irq index %d\n", i);
1908 smmu->irqs[i] = irq;
1911 err = arm_smmu_device_cfg_probe(smmu);
1916 smmu->masters = RB_ROOT;
1917 while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1918 "#stream-id-cells", i,
1920 err = register_smmu_master(smmu, dev, &masterspec);
1922 dev_err(dev, "failed to add master %s\n",
1923 masterspec.np->name);
1924 goto out_put_masters;
1929 dev_notice(dev, "registered %d master devices\n", i);
1931 parse_driver_options(smmu);
1933 if (smmu->version > 1 &&
1934 smmu->num_context_banks != smmu->num_context_irqs) {
1936 "found only %d context interrupt(s) but %d required\n",
1937 smmu->num_context_irqs, smmu->num_context_banks);
1939 goto out_put_masters;
1942 for (i = 0; i < smmu->num_global_irqs; ++i) {
1943 err = request_irq(smmu->irqs[i],
1944 arm_smmu_global_fault,
1946 "arm-smmu global fault",
1949 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1955 INIT_LIST_HEAD(&smmu->list);
1956 spin_lock(&arm_smmu_devices_lock);
1957 list_add(&smmu->list, &arm_smmu_devices);
1958 spin_unlock(&arm_smmu_devices_lock);
1960 arm_smmu_device_reset(smmu);
1965 free_irq(smmu->irqs[i], smmu);
1968 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1969 struct arm_smmu_master *master
1970 = container_of(node, struct arm_smmu_master, node);
1971 of_node_put(master->of_node);
1977 static int arm_smmu_device_remove(struct platform_device *pdev)
1980 struct device *dev = &pdev->dev;
1981 struct arm_smmu_device *curr, *smmu = NULL;
1982 struct rb_node *node;
1984 spin_lock(&arm_smmu_devices_lock);
1985 list_for_each_entry(curr, &arm_smmu_devices, list) {
1986 if (curr->dev == dev) {
1988 list_del(&smmu->list);
1992 spin_unlock(&arm_smmu_devices_lock);
1997 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1998 struct arm_smmu_master *master
1999 = container_of(node, struct arm_smmu_master, node);
2000 of_node_put(master->of_node);
2003 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
2004 dev_err(dev, "removing device with active domains!\n");
2006 for (i = 0; i < smmu->num_global_irqs; ++i)
2007 free_irq(smmu->irqs[i], smmu);
2009 /* Turn the thing off */
2010 writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
2015 static struct of_device_id arm_smmu_of_match[] = {
2016 { .compatible = "arm,smmu-v1", },
2017 { .compatible = "arm,smmu-v2", },
2018 { .compatible = "arm,mmu-400", },
2019 { .compatible = "arm,mmu-500", },
2022 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
2025 static struct platform_driver arm_smmu_driver = {
2027 .owner = THIS_MODULE,
2029 .of_match_table = of_match_ptr(arm_smmu_of_match),
2031 .probe = arm_smmu_device_dt_probe,
2032 .remove = arm_smmu_device_remove,
2035 static int __init arm_smmu_init(void)
2039 ret = platform_driver_register(&arm_smmu_driver);
2043 /* Oh, for a proper bus abstraction */
2044 if (!iommu_present(&platform_bus_type))
2045 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2047 #ifdef CONFIG_ARM_AMBA
2048 if (!iommu_present(&amba_bustype))
2049 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2053 if (!iommu_present(&pci_bus_type))
2054 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2060 static void __exit arm_smmu_exit(void)
2062 return platform_driver_unregister(&arm_smmu_driver);
2065 subsys_initcall(arm_smmu_init);
2066 module_exit(arm_smmu_exit);
2068 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2069 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2070 MODULE_LICENSE("GPL v2");