drivers/iommu/exynos-iommu.c

   1 /* linux/drivers/iommu/exynos_iommu.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  12 #define DEBUG
  13 #endif
  14
  15 #include <linux/io.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/clk.h>
  21 #include <linux/err.h>
  22 #include <linux/mm.h>
  23 #include <linux/iommu.h>
  24 #include <linux/errno.h>
  25 #include <linux/list.h>
  26 #include <linux/memblock.h>
  27 #include <linux/export.h>
  28
  29 #include <asm/cacheflush.h>
  30 #include <asm/pgtable.h>
  31
  32 typedef u32 sysmmu_iova_t;
  33 typedef u32 sysmmu_pte_t;
  34
  35 /* We do not consider super section mapping (16MB) */
  36 #define SECT_ORDER 20
  37 #define LPAGE_ORDER 16
  38 #define SPAGE_ORDER 12
  39
  40 #define SECT_SIZE (1 << SECT_ORDER)
  41 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  42 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  43
  44 #define SECT_MASK (~(SECT_SIZE - 1))
  45 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  46 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  47
  48 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  49                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  50 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  51 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  52 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  53                           ((*(sent) & 3) == 1))
  54 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  55
  56 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  57 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  58 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  59
  60 static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size)
  61 {
  62         return iova & (size - 1);
  63 }
  64
  65 #define section_phys(sent) (*(sent) & SECT_MASK)
  66 #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE)
  67 #define lpage_phys(pent) (*(pent) & LPAGE_MASK)
  68 #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE)
  69 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
  70 #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE)
  71
  72 #define NUM_LV1ENTRIES 4096
  73 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
  74
  75 static u32 lv1ent_offset(sysmmu_iova_t iova)
  76 {
  77         return iova >> SECT_ORDER;
  78 }
  79
  80 static u32 lv2ent_offset(sysmmu_iova_t iova)
  81 {
  82         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
  83 }
  84
  85 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
  86
  87 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
  88
  89 #define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
  90
  91 #define mk_lv1ent_sect(pa) ((pa) | 2)
  92 #define mk_lv1ent_page(pa) ((pa) | 1)
  93 #define mk_lv2ent_lpage(pa) ((pa) | 1)
  94 #define mk_lv2ent_spage(pa) ((pa) | 2)
  95
  96 #define CTRL_ENABLE     0x5
  97 #define CTRL_BLOCK      0x7
  98 #define CTRL_DISABLE    0x0
  99
 100 #define CFG_LRU         0x1
 101 #define CFG_QOS(n)      ((n & 0xF) << 7)
 102 #define CFG_MASK        0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */
 103 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 104 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 105 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 106
 107 #define REG_MMU_CTRL            0x000
 108 #define REG_MMU_CFG             0x004
 109 #define REG_MMU_STATUS          0x008
 110 #define REG_MMU_FLUSH           0x00C
 111 #define REG_MMU_FLUSH_ENTRY     0x010
 112 #define REG_PT_BASE_ADDR        0x014
 113 #define REG_INT_STATUS          0x018
 114 #define REG_INT_CLEAR           0x01C
 115
 116 #define REG_PAGE_FAULT_ADDR     0x024
 117 #define REG_AW_FAULT_ADDR       0x028
 118 #define REG_AR_FAULT_ADDR       0x02C
 119 #define REG_DEFAULT_SLAVE_ADDR  0x030
 120
 121 #define REG_MMU_VERSION         0x034
 122
 123 #define MMU_MAJ_VER(val)        ((val) >> 7)
 124 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 125 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 126
 127 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 128
 129 #define REG_PB0_SADDR           0x04C
 130 #define REG_PB0_EADDR           0x050
 131 #define REG_PB1_SADDR           0x054
 132 #define REG_PB1_EADDR           0x058
 133
 134 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 135
 136 static struct kmem_cache *lv2table_kmem_cache;
 137 static sysmmu_pte_t *zero_lv2_table;
 138 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 139
 140 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 141 {
 142         return pgtable + lv1ent_offset(iova);
 143 }
 144
 145 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 146 {
 147         return (sysmmu_pte_t *)phys_to_virt(
 148                                 lv2table_base(sent)) + lv2ent_offset(iova);
 149 }
 150
 151 enum exynos_sysmmu_inttype {
 152         SYSMMU_PAGEFAULT,
 153         SYSMMU_AR_MULTIHIT,
 154         SYSMMU_AW_MULTIHIT,
 155         SYSMMU_BUSERROR,
 156         SYSMMU_AR_SECURITY,
 157         SYSMMU_AR_ACCESS,
 158         SYSMMU_AW_SECURITY,
 159         SYSMMU_AW_PROTECTION, /* 7 */
 160         SYSMMU_FAULT_UNKNOWN,
 161         SYSMMU_FAULTS_NUM
 162 };
 163
 164 static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
 165         REG_PAGE_FAULT_ADDR,
 166         REG_AR_FAULT_ADDR,
 167         REG_AW_FAULT_ADDR,
 168         REG_DEFAULT_SLAVE_ADDR,
 169         REG_AR_FAULT_ADDR,
 170         REG_AR_FAULT_ADDR,
 171         REG_AW_FAULT_ADDR,
 172         REG_AW_FAULT_ADDR
 173 };
 174
 175 static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
 176         "PAGE FAULT",
 177         "AR MULTI-HIT FAULT",
 178         "AW MULTI-HIT FAULT",
 179         "BUS ERROR",
 180         "AR SECURITY PROTECTION FAULT",
 181         "AR ACCESS PROTECTION FAULT",
 182         "AW SECURITY PROTECTION FAULT",
 183         "AW ACCESS PROTECTION FAULT",
 184         "UNKNOWN FAULT"
 185 };
 186
 187 /* attached to dev.archdata.iommu of the master device */
 188 struct exynos_iommu_owner {
 189         struct list_head client; /* entry of exynos_iommu_domain.clients */
 190         struct device *dev;
 191         struct device *sysmmu;
 192         struct iommu_domain *domain;
 193         void *vmm_data;         /* IO virtual memory manager's data */
 194         spinlock_t lock;        /* Lock to preserve consistency of System MMU */
 195 };
 196
 197 struct exynos_iommu_domain {
 198         struct list_head clients; /* list of sysmmu_drvdata.node */
 199         sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */
 200         short *lv2entcnt; /* free lv2 entry counter for each section */
 201         spinlock_t lock; /* lock for this structure */
 202         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 203         struct iommu_domain domain; /* generic domain data structure */
 204 };
 205
 206 struct sysmmu_drvdata {
 207         struct device *sysmmu;  /* System MMU's device descriptor */
 208         struct device *master;  /* Owner of system MMU */
 209         void __iomem *sfrbase;
 210         struct clk *clk;
 211         struct clk *clk_master;
 212         int activations;
 213         spinlock_t lock;
 214         struct iommu_domain *domain;
 215         phys_addr_t pgtable;
 216         unsigned int version;
 217 };
 218
 219 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 220 {
 221         return container_of(dom, struct exynos_iommu_domain, domain);
 222 }
 223
 224 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 225 {
 226         /* return true if the System MMU was not active previously
 227            and it needs to be initialized */
 228         return ++data->activations == 1;
 229 }
 230
 231 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 232 {
 233         /* return true if the System MMU is needed to be disabled */
 234         BUG_ON(data->activations < 1);
 235         return --data->activations == 0;
 236 }
 237
 238 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 239 {
 240         return data->activations > 0;
 241 }
 242
 243 static void sysmmu_unblock(void __iomem *sfrbase)
 244 {
 245         __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
 246 }
 247
 248 static bool sysmmu_block(void __iomem *sfrbase)
 249 {
 250         int i = 120;
 251
 252         __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
 253         while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1))
 254                 --i;
 255
 256         if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) {
 257                 sysmmu_unblock(sfrbase);
 258                 return false;
 259         }
 260
 261         return true;
 262 }
 263
 264 static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
 265 {
 266         __raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
 267 }
 268
 269 static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
 270                                 sysmmu_iova_t iova, unsigned int num_inv)
 271 {
 272         unsigned int i;
 273
 274         for (i = 0; i < num_inv; i++) {
 275                 __raw_writel((iova & SPAGE_MASK) | 1,
 276                                 sfrbase + REG_MMU_FLUSH_ENTRY);
 277                 iova += SPAGE_SIZE;
 278         }
 279 }
 280
 281 static void __sysmmu_set_ptbase(void __iomem *sfrbase,
 282                                        phys_addr_t pgd)
 283 {
 284         __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
 285
 286         __sysmmu_tlb_invalidate(sfrbase);
 287 }
 288
 289 static void show_fault_information(const char *name,
 290                 enum exynos_sysmmu_inttype itype,
 291                 phys_addr_t pgtable_base, sysmmu_iova_t fault_addr)
 292 {
 293         sysmmu_pte_t *ent;
 294
 295         if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
 296                 itype = SYSMMU_FAULT_UNKNOWN;
 297
 298         pr_err("%s occurred at %#x by %s(Page table base: %pa)\n",
 299                 sysmmu_fault_name[itype], fault_addr, name, &pgtable_base);
 300
 301         ent = section_entry(phys_to_virt(pgtable_base), fault_addr);
 302         pr_err("\tLv1 entry: %#x\n", *ent);
 303
 304         if (lv1ent_page(ent)) {
 305                 ent = page_entry(ent, fault_addr);
 306                 pr_err("\t Lv2 entry: %#x\n", *ent);
 307         }
 308 }
 309
 310 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 311 {
 312         /* SYSMMU is in blocked state when interrupt occurred. */
 313         struct sysmmu_drvdata *data = dev_id;
 314         enum exynos_sysmmu_inttype itype;
 315         sysmmu_iova_t addr = -1;
 316         int ret = -ENOSYS;
 317
 318         WARN_ON(!is_sysmmu_active(data));
 319
 320         spin_lock(&data->lock);
 321
 322         if (!IS_ERR(data->clk_master))
 323                 clk_enable(data->clk_master);
 324
 325         itype = (enum exynos_sysmmu_inttype)
 326                 __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
 327         if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
 328                 itype = SYSMMU_FAULT_UNKNOWN;
 329         else
 330                 addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]);
 331
 332         if (itype == SYSMMU_FAULT_UNKNOWN) {
 333                 pr_err("%s: Fault is not occurred by System MMU '%s'!\n",
 334                         __func__, dev_name(data->sysmmu));
 335                 pr_err("%s: Please check if IRQ is correctly configured.\n",
 336                         __func__);
 337                 BUG();
 338         } else {
 339                 unsigned int base =
 340                                 __raw_readl(data->sfrbase + REG_PT_BASE_ADDR);
 341                 show_fault_information(dev_name(data->sysmmu),
 342                                         itype, base, addr);
 343                 if (data->domain)
 344                         ret = report_iommu_fault(data->domain,
 345                                         data->master, addr, itype);
 346         }
 347
 348         /* fault is not recovered by fault handler */
 349         BUG_ON(ret != 0);
 350
 351         __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR);
 352
 353         sysmmu_unblock(data->sfrbase);
 354
 355         if (!IS_ERR(data->clk_master))
 356                 clk_disable(data->clk_master);
 357
 358         spin_unlock(&data->lock);
 359
 360         return IRQ_HANDLED;
 361 }
 362
 363 static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
 364 {
 365         if (!IS_ERR(data->clk_master))
 366                 clk_enable(data->clk_master);
 367
 368         __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 369         __raw_writel(0, data->sfrbase + REG_MMU_CFG);
 370
 371         clk_disable(data->clk);
 372         if (!IS_ERR(data->clk_master))
 373                 clk_disable(data->clk_master);
 374 }
 375
 376 static bool __sysmmu_disable(struct sysmmu_drvdata *data)
 377 {
 378         bool disabled;
 379         unsigned long flags;
 380
 381         spin_lock_irqsave(&data->lock, flags);
 382
 383         disabled = set_sysmmu_inactive(data);
 384
 385         if (disabled) {
 386                 data->pgtable = 0;
 387                 data->domain = NULL;
 388
 389                 __sysmmu_disable_nocount(data);
 390
 391                 dev_dbg(data->sysmmu, "Disabled\n");
 392         } else  {
 393                 dev_dbg(data->sysmmu, "%d times left to disable\n",
 394                                         data->activations);
 395         }
 396
 397         spin_unlock_irqrestore(&data->lock, flags);
 398
 399         return disabled;
 400 }
 401
 402 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 403 {
 404         unsigned int cfg = CFG_LRU | CFG_QOS(15);
 405         unsigned int ver;
 406
 407         ver = MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION));
 408         if (MMU_MAJ_VER(ver) == 3) {
 409                 if (MMU_MIN_VER(ver) >= 2) {
 410                         cfg |= CFG_FLPDCACHE;
 411                         if (MMU_MIN_VER(ver) == 3) {
 412                                 cfg |= CFG_ACGEN;
 413                                 cfg &= ~CFG_LRU;
 414                         } else {
 415                                 cfg |= CFG_SYSSEL;
 416                         }
 417                 }
 418         }
 419
 420         __raw_writel(cfg, data->sfrbase + REG_MMU_CFG);
 421         data->version = ver;
 422 }
 423
 424 static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
 425 {
 426         if (!IS_ERR(data->clk_master))
 427                 clk_enable(data->clk_master);
 428         clk_enable(data->clk);
 429
 430         __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 431
 432         __sysmmu_init_config(data);
 433
 434         __sysmmu_set_ptbase(data->sfrbase, data->pgtable);
 435
 436         __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 437
 438         if (!IS_ERR(data->clk_master))
 439                 clk_disable(data->clk_master);
 440 }
 441
 442 static int __sysmmu_enable(struct sysmmu_drvdata *data,
 443                         phys_addr_t pgtable, struct iommu_domain *domain)
 444 {
 445         int ret = 0;
 446         unsigned long flags;
 447
 448         spin_lock_irqsave(&data->lock, flags);
 449         if (set_sysmmu_active(data)) {
 450                 data->pgtable = pgtable;
 451                 data->domain = domain;
 452
 453                 __sysmmu_enable_nocount(data);
 454
 455                 dev_dbg(data->sysmmu, "Enabled\n");
 456         } else {
 457                 ret = (pgtable == data->pgtable) ? 1 : -EBUSY;
 458
 459                 dev_dbg(data->sysmmu, "already enabled\n");
 460         }
 461
 462         if (WARN_ON(ret < 0))
 463                 set_sysmmu_inactive(data); /* decrement count */
 464
 465         spin_unlock_irqrestore(&data->lock, flags);
 466
 467         return ret;
 468 }
 469
 470 /* __exynos_sysmmu_enable: Enables System MMU
 471  *
 472  * returns -error if an error occurred and System MMU is not enabled,
 473  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 474  * enabled before.
 475  */
 476 static int __exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable,
 477                                   struct iommu_domain *domain)
 478 {
 479         int ret = 0;
 480         unsigned long flags;
 481         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 482         struct sysmmu_drvdata *data;
 483
 484         BUG_ON(!has_sysmmu(dev));
 485
 486         spin_lock_irqsave(&owner->lock, flags);
 487
 488         data = dev_get_drvdata(owner->sysmmu);
 489
 490         ret = __sysmmu_enable(data, pgtable, domain);
 491         if (ret >= 0)
 492                 data->master = dev;
 493
 494         spin_unlock_irqrestore(&owner->lock, flags);
 495
 496         return ret;
 497 }
 498
 499 int exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable)
 500 {
 501         BUG_ON(!memblock_is_memory(pgtable));
 502
 503         return __exynos_sysmmu_enable(dev, pgtable, NULL);
 504 }
 505
 506 static bool exynos_sysmmu_disable(struct device *dev)
 507 {
 508         unsigned long flags;
 509         bool disabled = true;
 510         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 511         struct sysmmu_drvdata *data;
 512
 513         BUG_ON(!has_sysmmu(dev));
 514
 515         spin_lock_irqsave(&owner->lock, flags);
 516
 517         data = dev_get_drvdata(owner->sysmmu);
 518
 519         disabled = __sysmmu_disable(data);
 520         if (disabled)
 521                 data->master = NULL;
 522
 523         spin_unlock_irqrestore(&owner->lock, flags);
 524
 525         return disabled;
 526 }
 527
 528 static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 529                                               sysmmu_iova_t iova)
 530 {
 531         if (data->version == MAKE_MMU_VER(3, 3))
 532                 __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY);
 533 }
 534
 535 static void sysmmu_tlb_invalidate_flpdcache(struct device *dev,
 536                                             sysmmu_iova_t iova)
 537 {
 538         unsigned long flags;
 539         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 540         struct sysmmu_drvdata *data = dev_get_drvdata(owner->sysmmu);
 541
 542         if (!IS_ERR(data->clk_master))
 543                 clk_enable(data->clk_master);
 544
 545         spin_lock_irqsave(&data->lock, flags);
 546         if (is_sysmmu_active(data))
 547                 __sysmmu_tlb_invalidate_flpdcache(data, iova);
 548         spin_unlock_irqrestore(&data->lock, flags);
 549
 550         if (!IS_ERR(data->clk_master))
 551                 clk_disable(data->clk_master);
 552 }
 553
 554 static void sysmmu_tlb_invalidate_entry(struct device *dev, sysmmu_iova_t iova,
 555                                         size_t size)
 556 {
 557         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 558         unsigned long flags;
 559         struct sysmmu_drvdata *data;
 560
 561         data = dev_get_drvdata(owner->sysmmu);
 562
 563         spin_lock_irqsave(&data->lock, flags);
 564         if (is_sysmmu_active(data)) {
 565                 unsigned int num_inv = 1;
 566
 567                 if (!IS_ERR(data->clk_master))
 568                         clk_enable(data->clk_master);
 569
 570                 /*
 571                  * L2TLB invalidation required
 572                  * 4KB page: 1 invalidation
 573                  * 64KB page: 16 invalidations
 574                  * 1MB page: 64 invalidations
 575                  * because it is set-associative TLB
 576                  * with 8-way and 64 sets.
 577                  * 1MB page can be cached in one of all sets.
 578                  * 64KB page can be one of 16 consecutive sets.
 579                  */
 580                 if (MMU_MAJ_VER(data->version) == 2)
 581                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 582
 583                 if (sysmmu_block(data->sfrbase)) {
 584                         __sysmmu_tlb_invalidate_entry(
 585                                 data->sfrbase, iova, num_inv);
 586                         sysmmu_unblock(data->sfrbase);
 587                 }
 588                 if (!IS_ERR(data->clk_master))
 589                         clk_disable(data->clk_master);
 590         } else {
 591                 dev_dbg(dev, "disabled. Skipping TLB invalidation @ %#x\n",
 592                         iova);
 593         }
 594         spin_unlock_irqrestore(&data->lock, flags);
 595 }
 596
 597 void exynos_sysmmu_tlb_invalidate(struct device *dev)
 598 {
 599         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 600         unsigned long flags;
 601         struct sysmmu_drvdata *data;
 602
 603         data = dev_get_drvdata(owner->sysmmu);
 604
 605         spin_lock_irqsave(&data->lock, flags);
 606         if (is_sysmmu_active(data)) {
 607                 if (!IS_ERR(data->clk_master))
 608                         clk_enable(data->clk_master);
 609                 if (sysmmu_block(data->sfrbase)) {
 610                         __sysmmu_tlb_invalidate(data->sfrbase);
 611                         sysmmu_unblock(data->sfrbase);
 612                 }
 613                 if (!IS_ERR(data->clk_master))
 614                         clk_disable(data->clk_master);
 615         } else {
 616                 dev_dbg(dev, "disabled. Skipping TLB invalidation\n");
 617         }
 618         spin_unlock_irqrestore(&data->lock, flags);
 619 }
 620
 621 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 622 {
 623         int irq, ret;
 624         struct device *dev = &pdev->dev;
 625         struct sysmmu_drvdata *data;
 626         struct resource *res;
 627
 628         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 629         if (!data)
 630                 return -ENOMEM;
 631
 632         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 633         data->sfrbase = devm_ioremap_resource(dev, res);
 634         if (IS_ERR(data->sfrbase))
 635                 return PTR_ERR(data->sfrbase);
 636
 637         irq = platform_get_irq(pdev, 0);
 638         if (irq <= 0) {
 639                 dev_err(dev, "Unable to find IRQ resource\n");
 640                 return irq;
 641         }
 642
 643         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 644                                 dev_name(dev), data);
 645         if (ret) {
 646                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 647                 return ret;
 648         }
 649
 650         data->clk = devm_clk_get(dev, "sysmmu");
 651         if (IS_ERR(data->clk)) {
 652                 dev_err(dev, "Failed to get clock!\n");
 653                 return PTR_ERR(data->clk);
 654         } else  {
 655                 ret = clk_prepare(data->clk);
 656                 if (ret) {
 657                         dev_err(dev, "Failed to prepare clk\n");
 658                         return ret;
 659                 }
 660         }
 661
 662         data->clk_master = devm_clk_get(dev, "master");
 663         if (!IS_ERR(data->clk_master)) {
 664                 ret = clk_prepare(data->clk_master);
 665                 if (ret) {
 666                         clk_unprepare(data->clk);
 667                         dev_err(dev, "Failed to prepare master's clk\n");
 668                         return ret;
 669                 }
 670         }
 671
 672         data->sysmmu = dev;
 673         spin_lock_init(&data->lock);
 674
 675         platform_set_drvdata(pdev, data);
 676
 677         pm_runtime_enable(dev);
 678
 679         return 0;
 680 }
 681
 682 static const struct of_device_id sysmmu_of_match[] __initconst = {
 683         { .compatible   = "samsung,exynos-sysmmu", },
 684         { },
 685 };
 686
 687 static struct platform_driver exynos_sysmmu_driver __refdata = {
 688         .probe  = exynos_sysmmu_probe,
 689         .driver = {
 690                 .name           = "exynos-sysmmu",
 691                 .of_match_table = sysmmu_of_match,
 692         }
 693 };
 694
 695 static inline void pgtable_flush(void *vastart, void *vaend)
 696 {
 697         dmac_flush_range(vastart, vaend);
 698         outer_flush_range(virt_to_phys(vastart),
 699                                 virt_to_phys(vaend));
 700 }
 701
 702 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 703 {
 704         struct exynos_iommu_domain *exynos_domain;
 705         int i;
 706
 707         if (type != IOMMU_DOMAIN_UNMANAGED)
 708                 return NULL;
 709
 710         exynos_domain = kzalloc(sizeof(*exynos_domain), GFP_KERNEL);
 711         if (!exynos_domain)
 712                 return NULL;
 713
 714         exynos_domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 715         if (!exynos_domain->pgtable)
 716                 goto err_pgtable;
 717
 718         exynos_domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 719         if (!exynos_domain->lv2entcnt)
 720                 goto err_counter;
 721
 722         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 723         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 724                 exynos_domain->pgtable[i + 0] = ZERO_LV2LINK;
 725                 exynos_domain->pgtable[i + 1] = ZERO_LV2LINK;
 726                 exynos_domain->pgtable[i + 2] = ZERO_LV2LINK;
 727                 exynos_domain->pgtable[i + 3] = ZERO_LV2LINK;
 728                 exynos_domain->pgtable[i + 4] = ZERO_LV2LINK;
 729                 exynos_domain->pgtable[i + 5] = ZERO_LV2LINK;
 730                 exynos_domain->pgtable[i + 6] = ZERO_LV2LINK;
 731                 exynos_domain->pgtable[i + 7] = ZERO_LV2LINK;
 732         }
 733
 734         pgtable_flush(exynos_domain->pgtable, exynos_domain->pgtable + NUM_LV1ENTRIES);
 735
 736         spin_lock_init(&exynos_domain->lock);
 737         spin_lock_init(&exynos_domain->pgtablelock);
 738         INIT_LIST_HEAD(&exynos_domain->clients);
 739
 740         exynos_domain->domain.geometry.aperture_start = 0;
 741         exynos_domain->domain.geometry.aperture_end   = ~0UL;
 742         exynos_domain->domain.geometry.force_aperture = true;
 743
 744         return &exynos_domain->domain;
 745
 746 err_counter:
 747         free_pages((unsigned long)exynos_domain->pgtable, 2);
 748 err_pgtable:
 749         kfree(exynos_domain);
 750         return NULL;
 751 }
 752
 753 static void exynos_iommu_domain_free(struct iommu_domain *domain)
 754 {
 755         struct exynos_iommu_domain *priv = to_exynos_domain(domain);
 756         struct exynos_iommu_owner *owner;
 757         unsigned long flags;
 758         int i;
 759
 760         WARN_ON(!list_empty(&priv->clients));
 761
 762         spin_lock_irqsave(&priv->lock, flags);
 763
 764         list_for_each_entry(owner, &priv->clients, client) {
 765                 while (!exynos_sysmmu_disable(owner->dev))
 766                         ; /* until System MMU is actually disabled */
 767         }
 768
 769         while (!list_empty(&priv->clients))
 770                 list_del_init(priv->clients.next);
 771
 772         spin_unlock_irqrestore(&priv->lock, flags);
 773
 774         for (i = 0; i < NUM_LV1ENTRIES; i++)
 775                 if (lv1ent_page(priv->pgtable + i))
 776                         kmem_cache_free(lv2table_kmem_cache,
 777                                 phys_to_virt(lv2table_base(priv->pgtable + i)));
 778
 779         free_pages((unsigned long)priv->pgtable, 2);
 780         free_pages((unsigned long)priv->lv2entcnt, 1);
 781         kfree(priv);
 782 }
 783
 784 static int exynos_iommu_attach_device(struct iommu_domain *domain,
 785                                    struct device *dev)
 786 {
 787         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 788         struct exynos_iommu_domain *priv = to_exynos_domain(domain);
 789         phys_addr_t pagetable = virt_to_phys(priv->pgtable);
 790         unsigned long flags;
 791         int ret;
 792
 793         spin_lock_irqsave(&priv->lock, flags);
 794
 795         ret = __exynos_sysmmu_enable(dev, pagetable, domain);
 796         if (ret == 0) {
 797                 list_add_tail(&owner->client, &priv->clients);
 798                 owner->domain = domain;
 799         }
 800
 801         spin_unlock_irqrestore(&priv->lock, flags);
 802
 803         if (ret < 0) {
 804                 dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
 805                                         __func__, &pagetable);
 806                 return ret;
 807         }
 808
 809         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
 810                 __func__, &pagetable, (ret == 0) ? "" : ", again");
 811
 812         return ret;
 813 }
 814
 815 static void exynos_iommu_detach_device(struct iommu_domain *domain,
 816                                     struct device *dev)
 817 {
 818         struct exynos_iommu_owner *owner;
 819         struct exynos_iommu_domain *priv = to_exynos_domain(domain);
 820         phys_addr_t pagetable = virt_to_phys(priv->pgtable);
 821         unsigned long flags;
 822
 823         spin_lock_irqsave(&priv->lock, flags);
 824
 825         list_for_each_entry(owner, &priv->clients, client) {
 826                 if (owner == dev->archdata.iommu) {
 827                         if (exynos_sysmmu_disable(dev)) {
 828                                 list_del_init(&owner->client);
 829                                 owner->domain = NULL;
 830                         }
 831                         break;
 832                 }
 833         }
 834
 835         spin_unlock_irqrestore(&priv->lock, flags);
 836
 837         if (owner == dev->archdata.iommu)
 838                 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
 839                                         __func__, &pagetable);
 840         else
 841                 dev_err(dev, "%s: No IOMMU is attached\n", __func__);
 842 }
 843
 844 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *priv,
 845                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 846 {
 847         if (lv1ent_section(sent)) {
 848                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 849                 return ERR_PTR(-EADDRINUSE);
 850         }
 851
 852         if (lv1ent_fault(sent)) {
 853                 sysmmu_pte_t *pent;
 854                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 855
 856                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 857                 BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1));
 858                 if (!pent)
 859                         return ERR_PTR(-ENOMEM);
 860
 861                 *sent = mk_lv1ent_page(virt_to_phys(pent));
 862                 kmemleak_ignore(pent);
 863                 *pgcounter = NUM_LV2ENTRIES;
 864                 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 865                 pgtable_flush(sent, sent + 1);
 866
 867                 /*
 868                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 869                  * FLPD cache may cache the address of zero_l2_table. This
 870                  * function replaces the zero_l2_table with new L2 page table
 871                  * to write valid mappings.
 872                  * Accessing the valid area may cause page fault since FLPD
 873                  * cache may still cache zero_l2_table for the valid area
 874                  * instead of new L2 page table that has the mapping
 875                  * information of the valid area.
 876                  * Thus any replacement of zero_l2_table with other valid L2
 877                  * page table must involve FLPD cache invalidation for System
 878                  * MMU v3.3.
 879                  * FLPD cache invalidation is performed with TLB invalidation
 880                  * by VPN without blocking. It is safe to invalidate TLB without
 881                  * blocking because the target address of TLB invalidation is
 882                  * not currently mapped.
 883                  */
 884                 if (need_flush_flpd_cache) {
 885                         struct exynos_iommu_owner *owner;
 886
 887                         spin_lock(&priv->lock);
 888                         list_for_each_entry(owner, &priv->clients, client)
 889                                 sysmmu_tlb_invalidate_flpdcache(
 890                                                         owner->dev, iova);
 891                         spin_unlock(&priv->lock);
 892                 }
 893         }
 894
 895         return page_entry(sent, iova);
 896 }
 897
 898 static int lv1set_section(struct exynos_iommu_domain *priv,
 899                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 900                           phys_addr_t paddr, short *pgcnt)
 901 {
 902         if (lv1ent_section(sent)) {
 903                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 904                         iova);
 905                 return -EADDRINUSE;
 906         }
 907
 908         if (lv1ent_page(sent)) {
 909                 if (*pgcnt != NUM_LV2ENTRIES) {
 910                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 911                                 iova);
 912                         return -EADDRINUSE;
 913                 }
 914
 915                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 916                 *pgcnt = 0;
 917         }
 918
 919         *sent = mk_lv1ent_sect(paddr);
 920
 921         pgtable_flush(sent, sent + 1);
 922
 923         spin_lock(&priv->lock);
 924         if (lv1ent_page_zero(sent)) {
 925                 struct exynos_iommu_owner *owner;
 926                 /*
 927                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 928                  * entry by speculative prefetch of SLPD which has no mapping.
 929                  */
 930                 list_for_each_entry(owner, &priv->clients, client)
 931                         sysmmu_tlb_invalidate_flpdcache(owner->dev, iova);
 932         }
 933         spin_unlock(&priv->lock);
 934
 935         return 0;
 936 }
 937
 938 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
 939                                                                 short *pgcnt)
 940 {
 941         if (size == SPAGE_SIZE) {
 942                 if (WARN_ON(!lv2ent_fault(pent)))
 943                         return -EADDRINUSE;
 944
 945                 *pent = mk_lv2ent_spage(paddr);
 946                 pgtable_flush(pent, pent + 1);
 947                 *pgcnt -= 1;
 948         } else { /* size == LPAGE_SIZE */
 949                 int i;
 950
 951                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
 952                         if (WARN_ON(!lv2ent_fault(pent))) {
 953                                 if (i > 0)
 954                                         memset(pent - i, 0, sizeof(*pent) * i);
 955                                 return -EADDRINUSE;
 956                         }
 957
 958                         *pent = mk_lv2ent_lpage(paddr);
 959                 }
 960                 pgtable_flush(pent - SPAGES_PER_LPAGE, pent);
 961                 *pgcnt -= SPAGES_PER_LPAGE;
 962         }
 963
 964         return 0;
 965 }
 966
 967 /*
 968  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
 969  *
 970  * System MMU v3.x has advanced logic to improve address translation
 971  * performance with caching more page table entries by a page table walk.
 972  * However, the logic has a bug that while caching faulty page table entries,
 973  * System MMU reports page fault if the cached fault entry is hit even though
 974  * the fault entry is updated to a valid entry after the entry is cached.
 975  * To prevent caching faulty page table entries which may be updated to valid
 976  * entries later, the virtual memory manager should care about the workaround
 977  * for the problem. The following describes the workaround.
 978  *
 979  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
 980  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
 981  *
 982  * Precisely, any start address of I/O virtual region must be aligned with
 983  * the following sizes for System MMU v3.1 and v3.2.
 984  * System MMU v3.1: 128KiB
 985  * System MMU v3.2: 256KiB
 986  *
 987  * Because System MMU v3.3 caches page table entries more aggressively, it needs
 988  * more workarounds.
 989  * - Any two consecutive I/O virtual regions must have a hole of size larger
 990  *   than or equal to 128KiB.
 991  * - Start address of an I/O virtual region must be aligned by 128KiB.
 992  */
 993 static int exynos_iommu_map(struct iommu_domain *domain, unsigned long l_iova,
 994                          phys_addr_t paddr, size_t size, int prot)
 995 {
 996         struct exynos_iommu_domain *priv = to_exynos_domain(domain);
 997         sysmmu_pte_t *entry;
 998         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
 999         unsigned long flags;
1000         int ret = -ENOMEM;
1001
1002         BUG_ON(priv->pgtable == NULL);
1003
1004         spin_lock_irqsave(&priv->pgtablelock, flags);
1005
1006         entry = section_entry(priv->pgtable, iova);
1007
1008         if (size == SECT_SIZE) {
1009                 ret = lv1set_section(priv, entry, iova, paddr,
1010                                         &priv->lv2entcnt[lv1ent_offset(iova)]);
1011         } else {
1012                 sysmmu_pte_t *pent;
1013
1014                 pent = alloc_lv2entry(priv, entry, iova,
1015                                         &priv->lv2entcnt[lv1ent_offset(iova)]);
1016
1017                 if (IS_ERR(pent))
1018                         ret = PTR_ERR(pent);
1019                 else
1020                         ret = lv2set_page(pent, paddr, size,
1021                                         &priv->lv2entcnt[lv1ent_offset(iova)]);
1022         }
1023
1024         if (ret)
1025                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1026                         __func__, ret, size, iova);
1027
1028         spin_unlock_irqrestore(&priv->pgtablelock, flags);
1029
1030         return ret;
1031 }
1032
1033 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *priv,
1034                                                 sysmmu_iova_t iova, size_t size)
1035 {
1036         struct exynos_iommu_owner *owner;
1037         unsigned long flags;
1038
1039         spin_lock_irqsave(&priv->lock, flags);
1040
1041         list_for_each_entry(owner, &priv->clients, client)
1042                 sysmmu_tlb_invalidate_entry(owner->dev, iova, size);
1043
1044         spin_unlock_irqrestore(&priv->lock, flags);
1045 }
1046
1047 static size_t exynos_iommu_unmap(struct iommu_domain *domain,
1048                                         unsigned long l_iova, size_t size)
1049 {
1050         struct exynos_iommu_domain *priv = to_exynos_domain(domain);
1051         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1052         sysmmu_pte_t *ent;
1053         size_t err_pgsize;
1054         unsigned long flags;
1055
1056         BUG_ON(priv->pgtable == NULL);
1057
1058         spin_lock_irqsave(&priv->pgtablelock, flags);
1059
1060         ent = section_entry(priv->pgtable, iova);
1061
1062         if (lv1ent_section(ent)) {
1063                 if (WARN_ON(size < SECT_SIZE)) {
1064                         err_pgsize = SECT_SIZE;
1065                         goto err;
1066                 }
1067
1068                 /* workaround for h/w bug in System MMU v3.3 */
1069                 *ent = ZERO_LV2LINK;
1070                 pgtable_flush(ent, ent + 1);
1071                 size = SECT_SIZE;
1072                 goto done;
1073         }
1074
1075         if (unlikely(lv1ent_fault(ent))) {
1076                 if (size > SECT_SIZE)
1077                         size = SECT_SIZE;
1078                 goto done;
1079         }
1080
1081         /* lv1ent_page(sent) == true here */
1082
1083         ent = page_entry(ent, iova);
1084
1085         if (unlikely(lv2ent_fault(ent))) {
1086                 size = SPAGE_SIZE;
1087                 goto done;
1088         }
1089
1090         if (lv2ent_small(ent)) {
1091                 *ent = 0;
1092                 size = SPAGE_SIZE;
1093                 pgtable_flush(ent, ent + 1);
1094                 priv->lv2entcnt[lv1ent_offset(iova)] += 1;
1095                 goto done;
1096         }
1097
1098         /* lv1ent_large(ent) == true here */
1099         if (WARN_ON(size < LPAGE_SIZE)) {
1100                 err_pgsize = LPAGE_SIZE;
1101                 goto err;
1102         }
1103
1104         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1105         pgtable_flush(ent, ent + SPAGES_PER_LPAGE);
1106
1107         size = LPAGE_SIZE;
1108         priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1109 done:
1110         spin_unlock_irqrestore(&priv->pgtablelock, flags);
1111
1112         exynos_iommu_tlb_invalidate_entry(priv, iova, size);
1113
1114         return size;
1115 err:
1116         spin_unlock_irqrestore(&priv->pgtablelock, flags);
1117
1118         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1119                 __func__, size, iova, err_pgsize);
1120
1121         return 0;
1122 }
1123
1124 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
1125                                           dma_addr_t iova)
1126 {
1127         struct exynos_iommu_domain *priv = to_exynos_domain(domain);
1128         sysmmu_pte_t *entry;
1129         unsigned long flags;
1130         phys_addr_t phys = 0;
1131
1132         spin_lock_irqsave(&priv->pgtablelock, flags);
1133
1134         entry = section_entry(priv->pgtable, iova);
1135
1136         if (lv1ent_section(entry)) {
1137                 phys = section_phys(entry) + section_offs(iova);
1138         } else if (lv1ent_page(entry)) {
1139                 entry = page_entry(entry, iova);
1140
1141                 if (lv2ent_large(entry))
1142                         phys = lpage_phys(entry) + lpage_offs(iova);
1143                 else if (lv2ent_small(entry))
1144                         phys = spage_phys(entry) + spage_offs(iova);
1145         }
1146
1147         spin_unlock_irqrestore(&priv->pgtablelock, flags);
1148
1149         return phys;
1150 }
1151
1152 static int exynos_iommu_add_device(struct device *dev)
1153 {
1154         struct iommu_group *group;
1155         int ret;
1156
1157         group = iommu_group_get(dev);
1158
1159         if (!group) {
1160                 group = iommu_group_alloc();
1161                 if (IS_ERR(group)) {
1162                         dev_err(dev, "Failed to allocate IOMMU group\n");
1163                         return PTR_ERR(group);
1164                 }
1165         }
1166
1167         ret = iommu_group_add_device(group, dev);
1168         iommu_group_put(group);
1169
1170         return ret;
1171 }
1172
1173 static void exynos_iommu_remove_device(struct device *dev)
1174 {
1175         iommu_group_remove_device(dev);
1176 }
1177
1178 static const struct iommu_ops exynos_iommu_ops = {
1179         .domain_alloc = exynos_iommu_domain_alloc,
1180         .domain_free = exynos_iommu_domain_free,
1181         .attach_dev = exynos_iommu_attach_device,
1182         .detach_dev = exynos_iommu_detach_device,
1183         .map = exynos_iommu_map,
1184         .unmap = exynos_iommu_unmap,
1185         .map_sg = default_iommu_map_sg,
1186         .iova_to_phys = exynos_iommu_iova_to_phys,
1187         .add_device = exynos_iommu_add_device,
1188         .remove_device = exynos_iommu_remove_device,
1189         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1190 };
1191
1192 static int __init exynos_iommu_init(void)
1193 {
1194         struct device_node *np;
1195         int ret;
1196
1197         np = of_find_matching_node(NULL, sysmmu_of_match);
1198         if (!np)
1199                 return 0;
1200
1201         of_node_put(np);
1202
1203         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1204                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1205         if (!lv2table_kmem_cache) {
1206                 pr_err("%s: Failed to create kmem cache\n", __func__);
1207                 return -ENOMEM;
1208         }
1209
1210         ret = platform_driver_register(&exynos_sysmmu_driver);
1211         if (ret) {
1212                 pr_err("%s: Failed to register driver\n", __func__);
1213                 goto err_reg_driver;
1214         }
1215
1216         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1217         if (zero_lv2_table == NULL) {
1218                 pr_err("%s: Failed to allocate zero level2 page table\n",
1219                         __func__);
1220                 ret = -ENOMEM;
1221                 goto err_zero_lv2;
1222         }
1223
1224         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1225         if (ret) {
1226                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1227                                                                 __func__);
1228                 goto err_set_iommu;
1229         }
1230
1231         return 0;
1232 err_set_iommu:
1233         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1234 err_zero_lv2:
1235         platform_driver_unregister(&exynos_sysmmu_driver);
1236 err_reg_driver:
1237         kmem_cache_destroy(lv2table_kmem_cache);
1238         return ret;
1239 }
1240 subsys_initcall(exynos_iommu_init);