1 /* linux/drivers/iommu/exynos_iommu.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
16 #include <linux/interrupt.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/clk.h>
21 #include <linux/err.h>
23 #include <linux/iommu.h>
24 #include <linux/errno.h>
25 #include <linux/list.h>
26 #include <linux/memblock.h>
27 #include <linux/export.h>
29 #include <asm/cacheflush.h>
30 #include <asm/pgtable.h>
32 #include <mach/sysmmu.h>
34 /* We does not consider super section mapping (16MB) */
36 #define LPAGE_ORDER 16
37 #define SPAGE_ORDER 12
39 #define SECT_SIZE (1 << SECT_ORDER)
40 #define LPAGE_SIZE (1 << LPAGE_ORDER)
41 #define SPAGE_SIZE (1 << SPAGE_ORDER)
43 #define SECT_MASK (~(SECT_SIZE - 1))
44 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
45 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
47 #define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
48 #define lv1ent_page(sent) ((*(sent) & 3) == 1)
49 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
51 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
52 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
53 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
55 #define section_phys(sent) (*(sent) & SECT_MASK)
56 #define section_offs(iova) ((iova) & 0xFFFFF)
57 #define lpage_phys(pent) (*(pent) & LPAGE_MASK)
58 #define lpage_offs(iova) ((iova) & 0xFFFF)
59 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
60 #define spage_offs(iova) ((iova) & 0xFFF)
62 #define lv1ent_offset(iova) ((iova) >> SECT_ORDER)
63 #define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER)
65 #define NUM_LV1ENTRIES 4096
66 #define NUM_LV2ENTRIES 256
68 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
70 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
72 #define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
74 #define mk_lv1ent_sect(pa) ((pa) | 2)
75 #define mk_lv1ent_page(pa) ((pa) | 1)
76 #define mk_lv2ent_lpage(pa) ((pa) | 1)
77 #define mk_lv2ent_spage(pa) ((pa) | 2)
79 #define CTRL_ENABLE 0x5
80 #define CTRL_BLOCK 0x7
81 #define CTRL_DISABLE 0x0
83 #define REG_MMU_CTRL 0x000
84 #define REG_MMU_CFG 0x004
85 #define REG_MMU_STATUS 0x008
86 #define REG_MMU_FLUSH 0x00C
87 #define REG_MMU_FLUSH_ENTRY 0x010
88 #define REG_PT_BASE_ADDR 0x014
89 #define REG_INT_STATUS 0x018
90 #define REG_INT_CLEAR 0x01C
92 #define REG_PAGE_FAULT_ADDR 0x024
93 #define REG_AW_FAULT_ADDR 0x028
94 #define REG_AR_FAULT_ADDR 0x02C
95 #define REG_DEFAULT_SLAVE_ADDR 0x030
97 #define REG_MMU_VERSION 0x034
99 #define REG_PB0_SADDR 0x04C
100 #define REG_PB0_EADDR 0x050
101 #define REG_PB1_SADDR 0x054
102 #define REG_PB1_EADDR 0x058
104 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
106 return pgtable + lv1ent_offset(iova);
109 static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
111 return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
114 enum exynos_sysmmu_inttype {
122 SYSMMU_AW_PROTECTION, /* 7 */
123 SYSMMU_FAULT_UNKNOWN,
128 * @itype: type of fault.
129 * @pgtable_base: the physical address of page table base. This is 0 if @itype
130 * is SYSMMU_BUSERROR.
131 * @fault_addr: the device (virtual) address that the System MMU tried to
132 * translated. This is 0 if @itype is SYSMMU_BUSERROR.
134 typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype,
135 unsigned long pgtable_base, unsigned long fault_addr);
137 static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
141 REG_DEFAULT_SLAVE_ADDR,
148 static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
150 "AR MULTI-HIT FAULT",
151 "AW MULTI-HIT FAULT",
153 "AR SECURITY PROTECTION FAULT",
154 "AR ACCESS PROTECTION FAULT",
155 "AW SECURITY PROTECTION FAULT",
156 "AW ACCESS PROTECTION FAULT",
160 struct exynos_iommu_domain {
161 struct list_head clients; /* list of sysmmu_drvdata.node */
162 unsigned long *pgtable; /* lv1 page table, 16KB */
163 short *lv2entcnt; /* free lv2 entry counter for each section */
164 spinlock_t lock; /* lock for this structure */
165 spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
168 struct sysmmu_drvdata {
169 struct list_head node; /* entry of exynos_iommu_domain.clients */
170 struct device *sysmmu; /* System MMU's device descriptor */
171 struct device *dev; /* Owner of system MMU */
174 void __iomem **sfrbases;
178 struct iommu_domain *domain;
179 sysmmu_fault_handler_t fault_handler;
180 unsigned long pgtable;
183 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
185 /* return true if the System MMU was not active previously
186 and it needs to be initialized */
187 return ++data->activations == 1;
190 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
192 /* return true if the System MMU is needed to be disabled */
193 BUG_ON(data->activations < 1);
194 return --data->activations == 0;
197 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
199 return data->activations > 0;
202 static void sysmmu_unblock(void __iomem *sfrbase)
204 __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
207 static bool sysmmu_block(void __iomem *sfrbase)
211 __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
212 while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1))
215 if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) {
216 sysmmu_unblock(sfrbase);
223 static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
225 __raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
228 static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
231 __raw_writel((iova & SPAGE_MASK) | 1, sfrbase + REG_MMU_FLUSH_ENTRY);
234 static void __sysmmu_set_ptbase(void __iomem *sfrbase,
237 __raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */
238 __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
240 __sysmmu_tlb_invalidate(sfrbase);
243 static void __sysmmu_set_prefbuf(void __iomem *sfrbase, unsigned long base,
244 unsigned long size, int idx)
246 __raw_writel(base, sfrbase + REG_PB0_SADDR + idx * 8);
247 __raw_writel(size - 1 + base, sfrbase + REG_PB0_EADDR + idx * 8);
250 static void __set_fault_handler(struct sysmmu_drvdata *data,
251 sysmmu_fault_handler_t handler)
255 write_lock_irqsave(&data->lock, flags);
256 data->fault_handler = handler;
257 write_unlock_irqrestore(&data->lock, flags);
260 void exynos_sysmmu_set_fault_handler(struct device *dev,
261 sysmmu_fault_handler_t handler)
263 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
265 __set_fault_handler(data, handler);
268 static int default_fault_handler(enum exynos_sysmmu_inttype itype,
269 unsigned long pgtable_base, unsigned long fault_addr)
273 if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
274 itype = SYSMMU_FAULT_UNKNOWN;
276 pr_err("%s occurred at 0x%lx(Page table base: 0x%lx)\n",
277 sysmmu_fault_name[itype], fault_addr, pgtable_base);
279 ent = section_entry(__va(pgtable_base), fault_addr);
280 pr_err("\tLv1 entry: 0x%lx\n", *ent);
282 if (lv1ent_page(ent)) {
283 ent = page_entry(ent, fault_addr);
284 pr_err("\t Lv2 entry: 0x%lx\n", *ent);
287 pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
294 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
296 /* SYSMMU is in blocked when interrupt occurred. */
297 struct sysmmu_drvdata *data = dev_id;
298 struct resource *irqres;
299 struct platform_device *pdev;
300 enum exynos_sysmmu_inttype itype;
301 unsigned long addr = -1;
303 int i, ret = -ENOSYS;
305 read_lock(&data->lock);
307 WARN_ON(!is_sysmmu_active(data));
309 pdev = to_platform_device(data->sysmmu);
310 for (i = 0; i < (pdev->num_resources / 2); i++) {
311 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
312 if (irqres && ((int)irqres->start == irq))
316 if (i == pdev->num_resources) {
317 itype = SYSMMU_FAULT_UNKNOWN;
319 itype = (enum exynos_sysmmu_inttype)
320 __ffs(__raw_readl(data->sfrbases[i] + REG_INT_STATUS));
321 if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
322 itype = SYSMMU_FAULT_UNKNOWN;
325 data->sfrbases[i] + fault_reg_offset[itype]);
329 ret = report_iommu_fault(data->domain, data->dev,
332 if ((ret == -ENOSYS) && data->fault_handler) {
333 unsigned long base = data->pgtable;
334 if (itype != SYSMMU_FAULT_UNKNOWN)
336 data->sfrbases[i] + REG_PT_BASE_ADDR);
337 ret = data->fault_handler(itype, base, addr);
340 if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
341 __raw_writel(1 << itype, data->sfrbases[i] + REG_INT_CLEAR);
343 dev_dbg(data->sysmmu, "(%s) %s is not handled.\n",
344 data->dbgname, sysmmu_fault_name[itype]);
346 if (itype != SYSMMU_FAULT_UNKNOWN)
347 sysmmu_unblock(data->sfrbases[i]);
349 read_unlock(&data->lock);
354 static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data)
357 bool disabled = false;
360 write_lock_irqsave(&data->lock, flags);
362 if (!set_sysmmu_inactive(data))
365 for (i = 0; i < data->nsfrs; i++)
366 __raw_writel(CTRL_DISABLE, data->sfrbases[i] + REG_MMU_CTRL);
369 clk_disable(data->clk[1]);
371 clk_disable(data->clk[0]);
377 write_unlock_irqrestore(&data->lock, flags);
380 dev_dbg(data->sysmmu, "(%s) Disabled\n", data->dbgname);
382 dev_dbg(data->sysmmu, "(%s) %d times left to be disabled\n",
383 data->dbgname, data->activations);
388 /* __exynos_sysmmu_enable: Enables System MMU
390 * returns -error if an error occurred and System MMU is not enabled,
391 * 0 if the System MMU has been just enabled and 1 if System MMU was already
394 static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data,
395 unsigned long pgtable, struct iommu_domain *domain)
400 write_lock_irqsave(&data->lock, flags);
402 if (!set_sysmmu_active(data)) {
403 if (WARN_ON(pgtable != data->pgtable)) {
405 set_sysmmu_inactive(data);
410 dev_dbg(data->sysmmu, "(%s) Already enabled\n", data->dbgname);
415 clk_enable(data->clk[0]);
417 clk_enable(data->clk[1]);
419 data->pgtable = pgtable;
421 for (i = 0; i < data->nsfrs; i++) {
422 __sysmmu_set_ptbase(data->sfrbases[i], pgtable);
424 if ((readl(data->sfrbases[i] + REG_MMU_VERSION) >> 28) == 3) {
425 /* System MMU version is 3.x */
426 __raw_writel((1 << 12) | (2 << 28),
427 data->sfrbases[i] + REG_MMU_CFG);
428 __sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 0);
429 __sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 1);
432 __raw_writel(CTRL_ENABLE, data->sfrbases[i] + REG_MMU_CTRL);
435 data->domain = domain;
437 dev_dbg(data->sysmmu, "(%s) Enabled\n", data->dbgname);
439 write_unlock_irqrestore(&data->lock, flags);
444 int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable)
446 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
449 BUG_ON(!memblock_is_memory(pgtable));
451 ret = pm_runtime_get_sync(data->sysmmu);
453 dev_dbg(data->sysmmu, "(%s) Failed to enable\n", data->dbgname);
457 ret = __exynos_sysmmu_enable(data, pgtable, NULL);
458 if (WARN_ON(ret < 0)) {
459 pm_runtime_put(data->sysmmu);
460 dev_err(data->sysmmu,
461 "(%s) Already enabled with page table %#lx\n",
462 data->dbgname, data->pgtable);
470 static bool exynos_sysmmu_disable(struct device *dev)
472 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
475 disabled = __exynos_sysmmu_disable(data);
476 pm_runtime_put(data->sysmmu);
481 static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova)
484 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
486 read_lock_irqsave(&data->lock, flags);
488 if (is_sysmmu_active(data)) {
490 for (i = 0; i < data->nsfrs; i++) {
491 if (sysmmu_block(data->sfrbases[i])) {
492 __sysmmu_tlb_invalidate_entry(
493 data->sfrbases[i], iova);
494 sysmmu_unblock(data->sfrbases[i]);
498 dev_dbg(data->sysmmu,
499 "(%s) Disabled. Skipping invalidating TLB.\n",
503 read_unlock_irqrestore(&data->lock, flags);
506 void exynos_sysmmu_tlb_invalidate(struct device *dev)
509 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
511 read_lock_irqsave(&data->lock, flags);
513 if (is_sysmmu_active(data)) {
515 for (i = 0; i < data->nsfrs; i++) {
516 if (sysmmu_block(data->sfrbases[i])) {
517 __sysmmu_tlb_invalidate(data->sfrbases[i]);
518 sysmmu_unblock(data->sfrbases[i]);
522 dev_dbg(data->sysmmu,
523 "(%s) Disabled. Skipping invalidating TLB.\n",
527 read_unlock_irqrestore(&data->lock, flags);
530 static int exynos_sysmmu_probe(struct platform_device *pdev)
534 struct sysmmu_drvdata *data;
538 data = kzalloc(sizeof(*data), GFP_KERNEL);
540 dev_dbg(dev, "Not enough memory\n");
545 dev_set_drvdata(dev, data);
546 data->nsfrs = pdev->num_resources / 2;
547 data->sfrbases = kmalloc(sizeof(*data->sfrbases) * data->nsfrs,
549 if (data->sfrbases == NULL) {
550 dev_dbg(dev, "Not enough memory\n");
555 for (i = 0; i < data->nsfrs; i++) {
556 struct resource *res;
557 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
559 dev_dbg(dev, "Unable to find IOMEM region\n");
564 data->sfrbases[i] = ioremap(res->start, resource_size(res));
565 if (!data->sfrbases[i]) {
566 dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n",
573 for (i = 0; i < data->nsfrs; i++) {
574 ret = platform_get_irq(pdev, i);
576 dev_dbg(dev, "Unable to find IRQ resource\n");
580 ret = request_irq(ret, exynos_sysmmu_irq, 0,
581 dev_name(dev), data);
583 dev_dbg(dev, "Unabled to register interrupt handler\n");
588 if (dev_get_platdata(dev)) {
590 struct sysmmu_platform_data *platdata = dev_get_platdata(dev);
592 beg = platdata->clockname;
594 for (deli = beg; (*deli != '\0') && (*deli != ','); deli++)
602 data->clk[0] = clk_get(dev, beg);
603 if (IS_ERR(data->clk[0])) {
605 dev_dbg(dev, "No clock descriptor registered\n");
608 if (data->clk[0] && deli) {
610 data->clk[1] = clk_get(dev, deli + 1);
611 if (IS_ERR(data->clk[1]))
615 data->dbgname = platdata->dbgname;
619 rwlock_init(&data->lock);
620 INIT_LIST_HEAD(&data->node);
622 __set_fault_handler(data, &default_fault_handler);
625 pm_runtime_enable(dev);
627 dev_dbg(dev, "(%s) Initialized\n", data->dbgname);
633 irq = platform_get_irq(pdev, i);
637 while (data->nsfrs-- > 0)
638 iounmap(data->sfrbases[data->nsfrs]);
639 kfree(data->sfrbases);
643 dev_err(dev, "Failed to initialize\n");
647 static struct platform_driver exynos_sysmmu_driver = {
648 .probe = exynos_sysmmu_probe,
650 .owner = THIS_MODULE,
651 .name = "exynos-sysmmu",
655 static inline void pgtable_flush(void *vastart, void *vaend)
657 dmac_flush_range(vastart, vaend);
658 outer_flush_range(virt_to_phys(vastart),
659 virt_to_phys(vaend));
662 static int exynos_iommu_domain_init(struct iommu_domain *domain)
664 struct exynos_iommu_domain *priv;
666 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
670 priv->pgtable = (unsigned long *)__get_free_pages(
671 GFP_KERNEL | __GFP_ZERO, 2);
675 priv->lv2entcnt = (short *)__get_free_pages(
676 GFP_KERNEL | __GFP_ZERO, 1);
677 if (!priv->lv2entcnt)
680 pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
682 spin_lock_init(&priv->lock);
683 spin_lock_init(&priv->pgtablelock);
684 INIT_LIST_HEAD(&priv->clients);
686 domain->geometry.aperture_start = 0;
687 domain->geometry.aperture_end = ~0UL;
688 domain->geometry.force_aperture = true;
694 free_pages((unsigned long)priv->pgtable, 2);
700 static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
702 struct exynos_iommu_domain *priv = domain->priv;
703 struct sysmmu_drvdata *data;
707 WARN_ON(!list_empty(&priv->clients));
709 spin_lock_irqsave(&priv->lock, flags);
711 list_for_each_entry(data, &priv->clients, node) {
712 while (!exynos_sysmmu_disable(data->dev))
713 ; /* until System MMU is actually disabled */
716 spin_unlock_irqrestore(&priv->lock, flags);
718 for (i = 0; i < NUM_LV1ENTRIES; i++)
719 if (lv1ent_page(priv->pgtable + i))
720 kfree(__va(lv2table_base(priv->pgtable + i)));
722 free_pages((unsigned long)priv->pgtable, 2);
723 free_pages((unsigned long)priv->lv2entcnt, 1);
728 static int exynos_iommu_attach_device(struct iommu_domain *domain,
731 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
732 struct exynos_iommu_domain *priv = domain->priv;
736 ret = pm_runtime_get_sync(data->sysmmu);
742 spin_lock_irqsave(&priv->lock, flags);
744 ret = __exynos_sysmmu_enable(data, __pa(priv->pgtable), domain);
747 /* 'data->node' must not be appeared in priv->clients */
748 BUG_ON(!list_empty(&data->node));
750 list_add_tail(&data->node, &priv->clients);
753 spin_unlock_irqrestore(&priv->lock, flags);
756 dev_err(dev, "%s: Failed to attach IOMMU with pgtable %#lx\n",
757 __func__, __pa(priv->pgtable));
758 pm_runtime_put(data->sysmmu);
759 } else if (ret > 0) {
760 dev_dbg(dev, "%s: IOMMU with pgtable 0x%lx already attached\n",
761 __func__, __pa(priv->pgtable));
763 dev_dbg(dev, "%s: Attached new IOMMU with pgtable 0x%lx\n",
764 __func__, __pa(priv->pgtable));
770 static void exynos_iommu_detach_device(struct iommu_domain *domain,
773 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
774 struct exynos_iommu_domain *priv = domain->priv;
775 struct list_head *pos;
779 spin_lock_irqsave(&priv->lock, flags);
781 list_for_each(pos, &priv->clients) {
782 if (list_entry(pos, struct sysmmu_drvdata, node) == data) {
791 if (__exynos_sysmmu_disable(data)) {
792 dev_dbg(dev, "%s: Detached IOMMU with pgtable %#lx\n",
793 __func__, __pa(priv->pgtable));
794 list_del_init(&data->node);
797 dev_dbg(dev, "%s: Detaching IOMMU with pgtable %#lx delayed",
798 __func__, __pa(priv->pgtable));
802 spin_unlock_irqrestore(&priv->lock, flags);
805 pm_runtime_put(data->sysmmu);
808 static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
811 if (lv1ent_fault(sent)) {
814 pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC);
815 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
819 *sent = mk_lv1ent_page(__pa(pent));
820 *pgcounter = NUM_LV2ENTRIES;
821 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
822 pgtable_flush(sent, sent + 1);
825 return page_entry(sent, iova);
828 static int lv1set_section(unsigned long *sent, phys_addr_t paddr, short *pgcnt)
830 if (lv1ent_section(sent))
833 if (lv1ent_page(sent)) {
834 if (*pgcnt != NUM_LV2ENTRIES)
837 kfree(page_entry(sent, 0));
842 *sent = mk_lv1ent_sect(paddr);
844 pgtable_flush(sent, sent + 1);
849 static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
852 if (size == SPAGE_SIZE) {
853 if (!lv2ent_fault(pent))
856 *pent = mk_lv2ent_spage(paddr);
857 pgtable_flush(pent, pent + 1);
859 } else { /* size == LPAGE_SIZE */
861 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
862 if (!lv2ent_fault(pent)) {
863 memset(pent, 0, sizeof(*pent) * i);
867 *pent = mk_lv2ent_lpage(paddr);
869 pgtable_flush(pent - SPAGES_PER_LPAGE, pent);
870 *pgcnt -= SPAGES_PER_LPAGE;
876 static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
877 phys_addr_t paddr, size_t size, int prot)
879 struct exynos_iommu_domain *priv = domain->priv;
880 unsigned long *entry;
884 BUG_ON(priv->pgtable == NULL);
886 spin_lock_irqsave(&priv->pgtablelock, flags);
888 entry = section_entry(priv->pgtable, iova);
890 if (size == SECT_SIZE) {
891 ret = lv1set_section(entry, paddr,
892 &priv->lv2entcnt[lv1ent_offset(iova)]);
896 pent = alloc_lv2entry(entry, iova,
897 &priv->lv2entcnt[lv1ent_offset(iova)]);
902 ret = lv2set_page(pent, paddr, size,
903 &priv->lv2entcnt[lv1ent_offset(iova)]);
907 pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",
908 __func__, iova, size);
911 spin_unlock_irqrestore(&priv->pgtablelock, flags);
916 static size_t exynos_iommu_unmap(struct iommu_domain *domain,
917 unsigned long iova, size_t size)
919 struct exynos_iommu_domain *priv = domain->priv;
920 struct sysmmu_drvdata *data;
924 BUG_ON(priv->pgtable == NULL);
926 spin_lock_irqsave(&priv->pgtablelock, flags);
928 ent = section_entry(priv->pgtable, iova);
930 if (lv1ent_section(ent)) {
931 BUG_ON(size < SECT_SIZE);
934 pgtable_flush(ent, ent + 1);
939 if (unlikely(lv1ent_fault(ent))) {
940 if (size > SECT_SIZE)
945 /* lv1ent_page(sent) == true here */
947 ent = page_entry(ent, iova);
949 if (unlikely(lv2ent_fault(ent))) {
954 if (lv2ent_small(ent)) {
957 priv->lv2entcnt[lv1ent_offset(iova)] += 1;
961 /* lv1ent_large(ent) == true here */
962 BUG_ON(size < LPAGE_SIZE);
964 memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
967 priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
969 spin_unlock_irqrestore(&priv->pgtablelock, flags);
971 spin_lock_irqsave(&priv->lock, flags);
972 list_for_each_entry(data, &priv->clients, node)
973 sysmmu_tlb_invalidate_entry(data->dev, iova);
974 spin_unlock_irqrestore(&priv->lock, flags);
980 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
983 struct exynos_iommu_domain *priv = domain->priv;
984 unsigned long *entry;
986 phys_addr_t phys = 0;
988 spin_lock_irqsave(&priv->pgtablelock, flags);
990 entry = section_entry(priv->pgtable, iova);
992 if (lv1ent_section(entry)) {
993 phys = section_phys(entry) + section_offs(iova);
994 } else if (lv1ent_page(entry)) {
995 entry = page_entry(entry, iova);
997 if (lv2ent_large(entry))
998 phys = lpage_phys(entry) + lpage_offs(iova);
999 else if (lv2ent_small(entry))
1000 phys = spage_phys(entry) + spage_offs(iova);
1003 spin_unlock_irqrestore(&priv->pgtablelock, flags);
1008 static struct iommu_ops exynos_iommu_ops = {
1009 .domain_init = exynos_iommu_domain_init,
1010 .domain_destroy = exynos_iommu_domain_destroy,
1011 .attach_dev = exynos_iommu_attach_device,
1012 .detach_dev = exynos_iommu_detach_device,
1013 .map = exynos_iommu_map,
1014 .unmap = exynos_iommu_unmap,
1015 .iova_to_phys = exynos_iommu_iova_to_phys,
1016 .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1019 static int __init exynos_iommu_init(void)
1023 ret = platform_driver_register(&exynos_sysmmu_driver);
1026 bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1030 subsys_initcall(exynos_iommu_init);