2 * Copyright © 2006-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * Authors: David Woodhouse <dwmw2@infradead.org>,
14 * Ashok Raj <ashok.raj@intel.com>,
15 * Shaohua Li <shaohua.li@intel.com>,
16 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
17 * Fenghua Yu <fenghua.yu@intel.com>
18 * Joerg Roedel <jroedel@suse.de>
21 #define pr_fmt(fmt) "DMAR: " fmt
23 #include <linux/init.h>
24 #include <linux/bitmap.h>
25 #include <linux/debugfs.h>
26 #include <linux/export.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/memory.h>
36 #include <linux/timer.h>
37 #include <linux/iova.h>
38 #include <linux/iommu.h>
39 #include <linux/intel-iommu.h>
40 #include <linux/syscore_ops.h>
41 #include <linux/tboot.h>
42 #include <linux/dmi.h>
43 #include <linux/pci-ats.h>
44 #include <linux/memblock.h>
45 #include <linux/dma-contiguous.h>
46 #include <linux/crash_dump.h>
47 #include <asm/irq_remapping.h>
48 #include <asm/cacheflush.h>
49 #include <asm/iommu.h>
51 #include "irq_remapping.h"
53 #define ROOT_SIZE VTD_PAGE_SIZE
54 #define CONTEXT_SIZE VTD_PAGE_SIZE
56 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
57 #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
58 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
59 #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
61 #define IOAPIC_RANGE_START (0xfee00000)
62 #define IOAPIC_RANGE_END (0xfeefffff)
63 #define IOVA_START_ADDR (0x1000)
65 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
67 #define MAX_AGAW_WIDTH 64
68 #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
70 #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
71 #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
73 /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
74 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
75 #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
76 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
77 #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
79 /* IO virtual address start page frame number */
80 #define IOVA_START_PFN (1)
82 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
83 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
84 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
86 /* page table handling */
87 #define LEVEL_STRIDE (9)
88 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
91 * This bitmap is used to advertise the page sizes our hardware support
92 * to the IOMMU core, which will then use this information to split
93 * physically contiguous memory regions it is mapping into page sizes
96 * Traditionally the IOMMU core just handed us the mappings directly,
97 * after making sure the size is an order of a 4KiB page and that the
98 * mapping has natural alignment.
100 * To retain this behavior, we currently advertise that we support
101 * all page sizes that are an order of 4KiB.
103 * If at some point we'd like to utilize the IOMMU core's new behavior,
104 * we could change this to advertise the real page sizes we support.
106 #define INTEL_IOMMU_PGSIZES (~0xFFFUL)
108 static inline int agaw_to_level(int agaw)
113 static inline int agaw_to_width(int agaw)
115 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
118 static inline int width_to_agaw(int width)
120 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
123 static inline unsigned int level_to_offset_bits(int level)
125 return (level - 1) * LEVEL_STRIDE;
128 static inline int pfn_level_offset(unsigned long pfn, int level)
130 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
133 static inline unsigned long level_mask(int level)
135 return -1UL << level_to_offset_bits(level);
138 static inline unsigned long level_size(int level)
140 return 1UL << level_to_offset_bits(level);
143 static inline unsigned long align_to_level(unsigned long pfn, int level)
145 return (pfn + level_size(level) - 1) & level_mask(level);
148 static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
150 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
153 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
154 are never going to work. */
155 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
157 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
160 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
162 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
164 static inline unsigned long page_to_dma_pfn(struct page *pg)
166 return mm_to_dma_pfn(page_to_pfn(pg));
168 static inline unsigned long virt_to_dma_pfn(void *p)
170 return page_to_dma_pfn(virt_to_page(p));
173 /* global iommu list, set NULL for ignored DMAR units */
174 static struct intel_iommu **g_iommus;
176 static void __init check_tylersburg_isoch(void);
177 static int rwbf_quirk;
180 * set to 1 to panic kernel if can't successfully enable VT-d
181 * (used when kernel is launched w/ TXT)
183 static int force_on = 0;
188 * 12-63: Context Ptr (12 - (haw-1))
195 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
198 * Take a root_entry and return the Lower Context Table Pointer (LCTP)
201 static phys_addr_t root_entry_lctp(struct root_entry *re)
206 return re->lo & VTD_PAGE_MASK;
210 * Take a root_entry and return the Upper Context Table Pointer (UCTP)
213 static phys_addr_t root_entry_uctp(struct root_entry *re)
218 return re->hi & VTD_PAGE_MASK;
223 * 1: fault processing disable
224 * 2-3: translation type
225 * 12-63: address space root
231 struct context_entry {
236 static inline void context_clear_pasid_enable(struct context_entry *context)
238 context->lo &= ~(1ULL << 11);
241 static inline bool context_pasid_enabled(struct context_entry *context)
243 return !!(context->lo & (1ULL << 11));
246 static inline void context_set_copied(struct context_entry *context)
248 context->hi |= (1ull << 3);
251 static inline bool context_copied(struct context_entry *context)
253 return !!(context->hi & (1ULL << 3));
256 static inline bool __context_present(struct context_entry *context)
258 return (context->lo & 1);
261 static inline bool context_present(struct context_entry *context)
263 return context_pasid_enabled(context) ?
264 __context_present(context) :
265 __context_present(context) && !context_copied(context);
268 static inline void context_set_present(struct context_entry *context)
273 static inline void context_set_fault_enable(struct context_entry *context)
275 context->lo &= (((u64)-1) << 2) | 1;
278 static inline void context_set_translation_type(struct context_entry *context,
281 context->lo &= (((u64)-1) << 4) | 3;
282 context->lo |= (value & 3) << 2;
285 static inline void context_set_address_root(struct context_entry *context,
288 context->lo &= ~VTD_PAGE_MASK;
289 context->lo |= value & VTD_PAGE_MASK;
292 static inline void context_set_address_width(struct context_entry *context,
295 context->hi |= value & 7;
298 static inline void context_set_domain_id(struct context_entry *context,
301 context->hi |= (value & ((1 << 16) - 1)) << 8;
304 static inline int context_domain_id(struct context_entry *c)
306 return((c->hi >> 8) & 0xffff);
309 static inline void context_clear_entry(struct context_entry *context)
322 * 12-63: Host physcial address
328 static inline void dma_clear_pte(struct dma_pte *pte)
333 static inline u64 dma_pte_addr(struct dma_pte *pte)
336 return pte->val & VTD_PAGE_MASK;
338 /* Must have a full atomic 64-bit read */
339 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
343 static inline bool dma_pte_present(struct dma_pte *pte)
345 return (pte->val & 3) != 0;
348 static inline bool dma_pte_superpage(struct dma_pte *pte)
350 return (pte->val & DMA_PTE_LARGE_PAGE);
353 static inline int first_pte_in_page(struct dma_pte *pte)
355 return !((unsigned long)pte & ~VTD_PAGE_MASK);
359 * This domain is a statically identity mapping domain.
360 * 1. This domain creats a static 1:1 mapping to all usable memory.
361 * 2. It maps to each iommu if successful.
362 * 3. Each iommu mapps to this domain if successful.
364 static struct dmar_domain *si_domain;
365 static int hw_pass_through = 1;
368 * Domain represents a virtual machine, more than one devices
369 * across iommus may be owned in one domain, e.g. kvm guest.
371 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 0)
373 /* si_domain contains mulitple devices */
374 #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 1)
376 #define for_each_domain_iommu(idx, domain) \
377 for (idx = 0; idx < g_num_of_iommus; idx++) \
378 if (domain->iommu_refcnt[idx])
381 int nid; /* node id */
383 unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED];
384 /* Refcount of devices per iommu */
387 u16 iommu_did[DMAR_UNITS_SUPPORTED];
388 /* Domain ids per IOMMU. Use u16 since
389 * domain ids are 16 bit wide according
390 * to VT-d spec, section 9.3 */
392 struct list_head devices; /* all devices' list */
393 struct iova_domain iovad; /* iova's that belong to this domain */
395 struct dma_pte *pgd; /* virtual address */
396 int gaw; /* max guest address width */
398 /* adjusted guest address width, 0 is level 2 30-bit */
401 int flags; /* flags to find out type of domain */
403 int iommu_coherency;/* indicate coherency of iommu access */
404 int iommu_snooping; /* indicate snooping control feature*/
405 int iommu_count; /* reference count of iommu */
406 int iommu_superpage;/* Level of superpages supported:
407 0 == 4KiB (no superpages), 1 == 2MiB,
408 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
409 u64 max_addr; /* maximum mapped address */
411 struct iommu_domain domain; /* generic domain data structure for
415 /* PCI domain-device relationship */
416 struct device_domain_info {
417 struct list_head link; /* link to domain siblings */
418 struct list_head global; /* link to global list */
419 u8 bus; /* PCI bus number */
420 u8 devfn; /* PCI devfn number */
424 } ats; /* ATS state */
425 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
426 struct intel_iommu *iommu; /* IOMMU used by this device */
427 struct dmar_domain *domain; /* pointer to domain */
430 struct dmar_rmrr_unit {
431 struct list_head list; /* list of rmrr units */
432 struct acpi_dmar_header *hdr; /* ACPI header */
433 u64 base_address; /* reserved base address*/
434 u64 end_address; /* reserved end address */
435 struct dmar_dev_scope *devices; /* target devices */
436 int devices_cnt; /* target device count */
439 struct dmar_atsr_unit {
440 struct list_head list; /* list of ATSR units */
441 struct acpi_dmar_header *hdr; /* ACPI header */
442 struct dmar_dev_scope *devices; /* target devices */
443 int devices_cnt; /* target device count */
444 u8 include_all:1; /* include all ports */
447 static LIST_HEAD(dmar_atsr_units);
448 static LIST_HEAD(dmar_rmrr_units);
450 #define for_each_rmrr_units(rmrr) \
451 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
453 static void flush_unmaps_timeout(unsigned long data);
455 static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
457 #define HIGH_WATER_MARK 250
458 struct deferred_flush_tables {
460 struct iova *iova[HIGH_WATER_MARK];
461 struct dmar_domain *domain[HIGH_WATER_MARK];
462 struct page *freelist[HIGH_WATER_MARK];
465 static struct deferred_flush_tables *deferred_flush;
467 /* bitmap for indexing intel_iommus */
468 static int g_num_of_iommus;
470 static DEFINE_SPINLOCK(async_umap_flush_lock);
471 static LIST_HEAD(unmaps_to_do);
474 static long list_size;
476 static void domain_exit(struct dmar_domain *domain);
477 static void domain_remove_dev_info(struct dmar_domain *domain);
478 static void dmar_remove_one_dev_info(struct dmar_domain *domain,
480 static void __dmar_remove_one_dev_info(struct device_domain_info *info);
481 static void domain_context_clear(struct intel_iommu *iommu,
483 static int domain_detach_iommu(struct dmar_domain *domain,
484 struct intel_iommu *iommu);
486 #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
487 int dmar_disabled = 0;
489 int dmar_disabled = 1;
490 #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
492 int intel_iommu_enabled = 0;
493 EXPORT_SYMBOL_GPL(intel_iommu_enabled);
495 static int dmar_map_gfx = 1;
496 static int dmar_forcedac;
497 static int intel_iommu_strict;
498 static int intel_iommu_superpage = 1;
499 static int intel_iommu_ecs = 1;
501 /* We only actually use ECS when PASID support (on the new bit 40)
502 * is also advertised. Some early implementations — the ones with
503 * PASID support on bit 28 — have issues even when we *only* use
504 * extended root/context tables. */
505 #define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \
506 ecap_pasid(iommu->ecap))
508 int intel_iommu_gfx_mapped;
509 EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
511 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
512 static DEFINE_SPINLOCK(device_domain_lock);
513 static LIST_HEAD(device_domain_list);
515 static const struct iommu_ops intel_iommu_ops;
517 static bool translation_pre_enabled(struct intel_iommu *iommu)
519 return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED);
522 static void clear_translation_pre_enabled(struct intel_iommu *iommu)
524 iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED;
527 static void init_translation_status(struct intel_iommu *iommu)
531 gsts = readl(iommu->reg + DMAR_GSTS_REG);
532 if (gsts & DMA_GSTS_TES)
533 iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED;
536 /* Convert generic 'struct iommu_domain to private struct dmar_domain */
537 static struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
539 return container_of(dom, struct dmar_domain, domain);
542 static int __init intel_iommu_setup(char *str)
547 if (!strncmp(str, "on", 2)) {
549 pr_info("IOMMU enabled\n");
550 } else if (!strncmp(str, "off", 3)) {
552 pr_info("IOMMU disabled\n");
553 } else if (!strncmp(str, "igfx_off", 8)) {
555 pr_info("Disable GFX device mapping\n");
556 } else if (!strncmp(str, "forcedac", 8)) {
557 pr_info("Forcing DAC for PCI devices\n");
559 } else if (!strncmp(str, "strict", 6)) {
560 pr_info("Disable batched IOTLB flush\n");
561 intel_iommu_strict = 1;
562 } else if (!strncmp(str, "sp_off", 6)) {
563 pr_info("Disable supported super page\n");
564 intel_iommu_superpage = 0;
565 } else if (!strncmp(str, "ecs_off", 7)) {
567 "Intel-IOMMU: disable extended context table support\n");
571 str += strcspn(str, ",");
577 __setup("intel_iommu=", intel_iommu_setup);
579 static struct kmem_cache *iommu_domain_cache;
580 static struct kmem_cache *iommu_devinfo_cache;
582 static struct dmar_domain* get_iommu_domain(struct intel_iommu *iommu, u16 did)
584 struct dmar_domain **domains;
587 domains = iommu->domains[idx];
591 return domains[did & 0xff];
594 static void set_iommu_domain(struct intel_iommu *iommu, u16 did,
595 struct dmar_domain *domain)
597 struct dmar_domain **domains;
600 if (!iommu->domains[idx]) {
601 size_t size = 256 * sizeof(struct dmar_domain *);
602 iommu->domains[idx] = kzalloc(size, GFP_ATOMIC);
605 domains = iommu->domains[idx];
606 if (WARN_ON(!domains))
609 domains[did & 0xff] = domain;
612 static inline void *alloc_pgtable_page(int node)
617 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
619 vaddr = page_address(page);
623 static inline void free_pgtable_page(void *vaddr)
625 free_page((unsigned long)vaddr);
628 static inline void *alloc_domain_mem(void)
630 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
633 static void free_domain_mem(void *vaddr)
635 kmem_cache_free(iommu_domain_cache, vaddr);
638 static inline void * alloc_devinfo_mem(void)
640 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
643 static inline void free_devinfo_mem(void *vaddr)
645 kmem_cache_free(iommu_devinfo_cache, vaddr);
648 static inline int domain_type_is_vm(struct dmar_domain *domain)
650 return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE;
653 static inline int domain_type_is_si(struct dmar_domain *domain)
655 return domain->flags & DOMAIN_FLAG_STATIC_IDENTITY;
658 static inline int domain_type_is_vm_or_si(struct dmar_domain *domain)
660 return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE |
661 DOMAIN_FLAG_STATIC_IDENTITY);
664 static inline int domain_pfn_supported(struct dmar_domain *domain,
667 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
669 return !(addr_width < BITS_PER_LONG && pfn >> addr_width);
672 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
677 sagaw = cap_sagaw(iommu->cap);
678 for (agaw = width_to_agaw(max_gaw);
680 if (test_bit(agaw, &sagaw))
688 * Calculate max SAGAW for each iommu.
690 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
692 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
696 * calculate agaw for each iommu.
697 * "SAGAW" may be different across iommus, use a default agaw, and
698 * get a supported less agaw for iommus that don't support the default agaw.
700 int iommu_calculate_agaw(struct intel_iommu *iommu)
702 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
705 /* This functionin only returns single iommu in a domain */
706 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
710 /* si_domain and vm domain should not get here. */
711 BUG_ON(domain_type_is_vm_or_si(domain));
712 for_each_domain_iommu(iommu_id, domain)
715 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
718 return g_iommus[iommu_id];
721 static void domain_update_iommu_coherency(struct dmar_domain *domain)
723 struct dmar_drhd_unit *drhd;
724 struct intel_iommu *iommu;
728 domain->iommu_coherency = 1;
730 for_each_domain_iommu(i, domain) {
732 if (!ecap_coherent(g_iommus[i]->ecap)) {
733 domain->iommu_coherency = 0;
740 /* No hardware attached; use lowest common denominator */
742 for_each_active_iommu(iommu, drhd) {
743 if (!ecap_coherent(iommu->ecap)) {
744 domain->iommu_coherency = 0;
751 static int domain_update_iommu_snooping(struct intel_iommu *skip)
753 struct dmar_drhd_unit *drhd;
754 struct intel_iommu *iommu;
758 for_each_active_iommu(iommu, drhd) {
760 if (!ecap_sc_support(iommu->ecap)) {
771 static int domain_update_iommu_superpage(struct intel_iommu *skip)
773 struct dmar_drhd_unit *drhd;
774 struct intel_iommu *iommu;
777 if (!intel_iommu_superpage) {
781 /* set iommu_superpage to the smallest common denominator */
783 for_each_active_iommu(iommu, drhd) {
785 mask &= cap_super_page_val(iommu->cap);
795 /* Some capabilities may be different across iommus */
796 static void domain_update_iommu_cap(struct dmar_domain *domain)
798 domain_update_iommu_coherency(domain);
799 domain->iommu_snooping = domain_update_iommu_snooping(NULL);
800 domain->iommu_superpage = domain_update_iommu_superpage(NULL);
803 static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu,
804 u8 bus, u8 devfn, int alloc)
806 struct root_entry *root = &iommu->root_entry[bus];
807 struct context_entry *context;
811 if (ecs_enabled(iommu)) {
819 context = phys_to_virt(*entry & VTD_PAGE_MASK);
821 unsigned long phy_addr;
825 context = alloc_pgtable_page(iommu->node);
829 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
830 phy_addr = virt_to_phys((void *)context);
831 *entry = phy_addr | 1;
832 __iommu_flush_cache(iommu, entry, sizeof(*entry));
834 return &context[devfn];
837 static int iommu_dummy(struct device *dev)
839 return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
842 static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
844 struct dmar_drhd_unit *drhd = NULL;
845 struct intel_iommu *iommu;
847 struct pci_dev *ptmp, *pdev = NULL;
851 if (iommu_dummy(dev))
854 if (dev_is_pci(dev)) {
855 pdev = to_pci_dev(dev);
856 segment = pci_domain_nr(pdev->bus);
857 } else if (has_acpi_companion(dev))
858 dev = &ACPI_COMPANION(dev)->dev;
861 for_each_active_iommu(iommu, drhd) {
862 if (pdev && segment != drhd->segment)
865 for_each_active_dev_scope(drhd->devices,
866 drhd->devices_cnt, i, tmp) {
868 *bus = drhd->devices[i].bus;
869 *devfn = drhd->devices[i].devfn;
873 if (!pdev || !dev_is_pci(tmp))
876 ptmp = to_pci_dev(tmp);
877 if (ptmp->subordinate &&
878 ptmp->subordinate->number <= pdev->bus->number &&
879 ptmp->subordinate->busn_res.end >= pdev->bus->number)
883 if (pdev && drhd->include_all) {
885 *bus = pdev->bus->number;
886 *devfn = pdev->devfn;
897 static void domain_flush_cache(struct dmar_domain *domain,
898 void *addr, int size)
900 if (!domain->iommu_coherency)
901 clflush_cache_range(addr, size);
904 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
906 struct context_entry *context;
910 spin_lock_irqsave(&iommu->lock, flags);
911 context = iommu_context_addr(iommu, bus, devfn, 0);
913 ret = context_present(context);
914 spin_unlock_irqrestore(&iommu->lock, flags);
918 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
920 struct context_entry *context;
923 spin_lock_irqsave(&iommu->lock, flags);
924 context = iommu_context_addr(iommu, bus, devfn, 0);
926 context_clear_entry(context);
927 __iommu_flush_cache(iommu, context, sizeof(*context));
929 spin_unlock_irqrestore(&iommu->lock, flags);
932 static void free_context_table(struct intel_iommu *iommu)
936 struct context_entry *context;
938 spin_lock_irqsave(&iommu->lock, flags);
939 if (!iommu->root_entry) {
942 for (i = 0; i < ROOT_ENTRY_NR; i++) {
943 context = iommu_context_addr(iommu, i, 0, 0);
945 free_pgtable_page(context);
947 if (!ecs_enabled(iommu))
950 context = iommu_context_addr(iommu, i, 0x80, 0);
952 free_pgtable_page(context);
955 free_pgtable_page(iommu->root_entry);
956 iommu->root_entry = NULL;
958 spin_unlock_irqrestore(&iommu->lock, flags);
961 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
962 unsigned long pfn, int *target_level)
964 struct dma_pte *parent, *pte = NULL;
965 int level = agaw_to_level(domain->agaw);
968 BUG_ON(!domain->pgd);
970 if (!domain_pfn_supported(domain, pfn))
971 /* Address beyond IOMMU's addressing capabilities. */
974 parent = domain->pgd;
979 offset = pfn_level_offset(pfn, level);
980 pte = &parent[offset];
981 if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
983 if (level == *target_level)
986 if (!dma_pte_present(pte)) {
989 tmp_page = alloc_pgtable_page(domain->nid);
994 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
995 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
996 if (cmpxchg64(&pte->val, 0ULL, pteval))
997 /* Someone else set it while we were thinking; use theirs. */
998 free_pgtable_page(tmp_page);
1000 domain_flush_cache(domain, pte, sizeof(*pte));
1005 parent = phys_to_virt(dma_pte_addr(pte));
1010 *target_level = level;
1016 /* return address's pte at specific level */
1017 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
1019 int level, int *large_page)
1021 struct dma_pte *parent, *pte = NULL;
1022 int total = agaw_to_level(domain->agaw);
1025 parent = domain->pgd;
1026 while (level <= total) {
1027 offset = pfn_level_offset(pfn, total);
1028 pte = &parent[offset];
1032 if (!dma_pte_present(pte)) {
1033 *large_page = total;
1037 if (dma_pte_superpage(pte)) {
1038 *large_page = total;
1042 parent = phys_to_virt(dma_pte_addr(pte));
1048 /* clear last level pte, a tlb flush should be followed */
1049 static void dma_pte_clear_range(struct dmar_domain *domain,
1050 unsigned long start_pfn,
1051 unsigned long last_pfn)
1053 unsigned int large_page = 1;
1054 struct dma_pte *first_pte, *pte;
1056 BUG_ON(!domain_pfn_supported(domain, start_pfn));
1057 BUG_ON(!domain_pfn_supported(domain, last_pfn));
1058 BUG_ON(start_pfn > last_pfn);
1060 /* we don't need lock here; nobody else touches the iova range */
1063 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
1065 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
1070 start_pfn += lvl_to_nr_pages(large_page);
1072 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
1074 domain_flush_cache(domain, first_pte,
1075 (void *)pte - (void *)first_pte);
1077 } while (start_pfn && start_pfn <= last_pfn);
1080 static void dma_pte_free_level(struct dmar_domain *domain, int level,
1081 struct dma_pte *pte, unsigned long pfn,
1082 unsigned long start_pfn, unsigned long last_pfn)
1084 pfn = max(start_pfn, pfn);
1085 pte = &pte[pfn_level_offset(pfn, level)];
1088 unsigned long level_pfn;
1089 struct dma_pte *level_pte;
1091 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
1094 level_pfn = pfn & level_mask(level - 1);
1095 level_pte = phys_to_virt(dma_pte_addr(pte));
1098 dma_pte_free_level(domain, level - 1, level_pte,
1099 level_pfn, start_pfn, last_pfn);
1101 /* If range covers entire pagetable, free it */
1102 if (!(start_pfn > level_pfn ||
1103 last_pfn < level_pfn + level_size(level) - 1)) {
1105 domain_flush_cache(domain, pte, sizeof(*pte));
1106 free_pgtable_page(level_pte);
1109 pfn += level_size(level);
1110 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1113 /* free page table pages. last level pte should already be cleared */
1114 static void dma_pte_free_pagetable(struct dmar_domain *domain,
1115 unsigned long start_pfn,
1116 unsigned long last_pfn)
1118 BUG_ON(!domain_pfn_supported(domain, start_pfn));
1119 BUG_ON(!domain_pfn_supported(domain, last_pfn));
1120 BUG_ON(start_pfn > last_pfn);
1122 dma_pte_clear_range(domain, start_pfn, last_pfn);
1124 /* We don't need lock here; nobody else touches the iova range */
1125 dma_pte_free_level(domain, agaw_to_level(domain->agaw),
1126 domain->pgd, 0, start_pfn, last_pfn);
1129 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1130 free_pgtable_page(domain->pgd);
1135 /* When a page at a given level is being unlinked from its parent, we don't
1136 need to *modify* it at all. All we need to do is make a list of all the
1137 pages which can be freed just as soon as we've flushed the IOTLB and we
1138 know the hardware page-walk will no longer touch them.
1139 The 'pte' argument is the *parent* PTE, pointing to the page that is to
1141 static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
1142 int level, struct dma_pte *pte,
1143 struct page *freelist)
1147 pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
1148 pg->freelist = freelist;
1154 pte = page_address(pg);
1156 if (dma_pte_present(pte) && !dma_pte_superpage(pte))
1157 freelist = dma_pte_list_pagetables(domain, level - 1,
1160 } while (!first_pte_in_page(pte));
1165 static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
1166 struct dma_pte *pte, unsigned long pfn,
1167 unsigned long start_pfn,
1168 unsigned long last_pfn,
1169 struct page *freelist)
1171 struct dma_pte *first_pte = NULL, *last_pte = NULL;
1173 pfn = max(start_pfn, pfn);
1174 pte = &pte[pfn_level_offset(pfn, level)];
1177 unsigned long level_pfn;
1179 if (!dma_pte_present(pte))
1182 level_pfn = pfn & level_mask(level);
1184 /* If range covers entire pagetable, free it */
1185 if (start_pfn <= level_pfn &&
1186 last_pfn >= level_pfn + level_size(level) - 1) {
1187 /* These suborbinate page tables are going away entirely. Don't
1188 bother to clear them; we're just going to *free* them. */
1189 if (level > 1 && !dma_pte_superpage(pte))
1190 freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
1196 } else if (level > 1) {
1197 /* Recurse down into a level that isn't *entirely* obsolete */
1198 freelist = dma_pte_clear_level(domain, level - 1,
1199 phys_to_virt(dma_pte_addr(pte)),
1200 level_pfn, start_pfn, last_pfn,
1204 pfn += level_size(level);
1205 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1208 domain_flush_cache(domain, first_pte,
1209 (void *)++last_pte - (void *)first_pte);
1214 /* We can't just free the pages because the IOMMU may still be walking
1215 the page tables, and may have cached the intermediate levels. The
1216 pages can only be freed after the IOTLB flush has been done. */
1217 static struct page *domain_unmap(struct dmar_domain *domain,
1218 unsigned long start_pfn,
1219 unsigned long last_pfn)
1221 struct page *freelist = NULL;
1223 BUG_ON(!domain_pfn_supported(domain, start_pfn));
1224 BUG_ON(!domain_pfn_supported(domain, last_pfn));
1225 BUG_ON(start_pfn > last_pfn);
1227 /* we don't need lock here; nobody else touches the iova range */
1228 freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
1229 domain->pgd, 0, start_pfn, last_pfn, NULL);
1232 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1233 struct page *pgd_page = virt_to_page(domain->pgd);
1234 pgd_page->freelist = freelist;
1235 freelist = pgd_page;
1243 static void dma_free_pagelist(struct page *freelist)
1247 while ((pg = freelist)) {
1248 freelist = pg->freelist;
1249 free_pgtable_page(page_address(pg));
1253 /* iommu handling */
1254 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
1256 struct root_entry *root;
1257 unsigned long flags;
1259 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
1261 pr_err("Allocating root entry for %s failed\n",
1266 __iommu_flush_cache(iommu, root, ROOT_SIZE);
1268 spin_lock_irqsave(&iommu->lock, flags);
1269 iommu->root_entry = root;
1270 spin_unlock_irqrestore(&iommu->lock, flags);
1275 static void iommu_set_root_entry(struct intel_iommu *iommu)
1281 addr = virt_to_phys(iommu->root_entry);
1282 if (ecs_enabled(iommu))
1283 addr |= DMA_RTADDR_RTT;
1285 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1286 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr);
1288 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
1290 /* Make sure hardware complete it */
1291 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1292 readl, (sts & DMA_GSTS_RTPS), sts);
1294 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1297 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
1302 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
1305 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1306 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
1308 /* Make sure hardware complete it */
1309 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1310 readl, (!(val & DMA_GSTS_WBFS)), val);
1312 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1315 /* return value determine if we need a write buffer flush */
1316 static void __iommu_flush_context(struct intel_iommu *iommu,
1317 u16 did, u16 source_id, u8 function_mask,
1324 case DMA_CCMD_GLOBAL_INVL:
1325 val = DMA_CCMD_GLOBAL_INVL;
1327 case DMA_CCMD_DOMAIN_INVL:
1328 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1330 case DMA_CCMD_DEVICE_INVL:
1331 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1332 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1337 val |= DMA_CCMD_ICC;
1339 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1340 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1342 /* Make sure hardware complete it */
1343 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1344 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1346 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1349 /* return value determine if we need a write buffer flush */
1350 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1351 u64 addr, unsigned int size_order, u64 type)
1353 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1354 u64 val = 0, val_iva = 0;
1358 case DMA_TLB_GLOBAL_FLUSH:
1359 /* global flush doesn't need set IVA_REG */
1360 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1362 case DMA_TLB_DSI_FLUSH:
1363 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1365 case DMA_TLB_PSI_FLUSH:
1366 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1367 /* IH bit is passed in as part of address */
1368 val_iva = size_order | addr;
1373 /* Note: set drain read/write */
1376 * This is probably to be super secure.. Looks like we can
1377 * ignore it without any impact.
1379 if (cap_read_drain(iommu->cap))
1380 val |= DMA_TLB_READ_DRAIN;
1382 if (cap_write_drain(iommu->cap))
1383 val |= DMA_TLB_WRITE_DRAIN;
1385 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1386 /* Note: Only uses first TLB reg currently */
1388 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1389 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1391 /* Make sure hardware complete it */
1392 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1393 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1395 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1397 /* check IOTLB invalidation granularity */
1398 if (DMA_TLB_IAIG(val) == 0)
1399 pr_err("Flush IOTLB failed\n");
1400 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1401 pr_debug("TLB flush request %Lx, actual %Lx\n",
1402 (unsigned long long)DMA_TLB_IIRG(type),
1403 (unsigned long long)DMA_TLB_IAIG(val));
1406 static struct device_domain_info *
1407 iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
1411 struct device_domain_info *info;
1412 struct pci_dev *pdev;
1414 assert_spin_locked(&device_domain_lock);
1416 if (!ecap_dev_iotlb_support(iommu->ecap))
1422 list_for_each_entry(info, &domain->devices, link)
1423 if (info->iommu == iommu && info->bus == bus &&
1424 info->devfn == devfn) {
1429 if (!found || !info->dev || !dev_is_pci(info->dev))
1432 pdev = to_pci_dev(info->dev);
1434 if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS))
1437 if (!dmar_find_matched_atsr_unit(pdev))
1443 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1445 struct pci_dev *pdev;
1447 if (!info || !dev_is_pci(info->dev))
1450 pdev = to_pci_dev(info->dev);
1451 if (pci_enable_ats(pdev, VTD_PAGE_SHIFT))
1454 info->ats.enabled = 1;
1455 info->ats.qdep = pci_ats_queue_depth(pdev);
1458 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1460 if (!info->ats.enabled)
1463 pci_disable_ats(to_pci_dev(info->dev));
1464 info->ats.enabled = 0;
1467 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1468 u64 addr, unsigned mask)
1471 unsigned long flags;
1472 struct device_domain_info *info;
1474 spin_lock_irqsave(&device_domain_lock, flags);
1475 list_for_each_entry(info, &domain->devices, link) {
1476 if (!info->ats.enabled)
1479 sid = info->bus << 8 | info->devfn;
1480 qdep = info->ats.qdep;
1481 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1483 spin_unlock_irqrestore(&device_domain_lock, flags);
1486 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu,
1487 struct dmar_domain *domain,
1488 unsigned long pfn, unsigned int pages,
1491 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1492 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1493 u16 did = domain->iommu_did[iommu->seq_id];
1500 * Fallback to domain selective flush if no PSI support or the size is
1502 * PSI requires page size to be 2 ^ x, and the base address is naturally
1503 * aligned to the size
1505 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1506 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1509 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
1513 * In caching mode, changes of pages from non-present to present require
1514 * flush. However, device IOTLB doesn't need to be flushed in this case.
1516 if (!cap_caching_mode(iommu->cap) || !map)
1517 iommu_flush_dev_iotlb(get_iommu_domain(iommu, did),
1521 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1524 unsigned long flags;
1526 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1527 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1528 pmen &= ~DMA_PMEN_EPM;
1529 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1531 /* wait for the protected region status bit to clear */
1532 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1533 readl, !(pmen & DMA_PMEN_PRS), pmen);
1535 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1538 static void iommu_enable_translation(struct intel_iommu *iommu)
1541 unsigned long flags;
1543 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1544 iommu->gcmd |= DMA_GCMD_TE;
1545 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1547 /* Make sure hardware complete it */
1548 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1549 readl, (sts & DMA_GSTS_TES), sts);
1551 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1554 static void iommu_disable_translation(struct intel_iommu *iommu)
1559 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1560 iommu->gcmd &= ~DMA_GCMD_TE;
1561 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1563 /* Make sure hardware complete it */
1564 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1565 readl, (!(sts & DMA_GSTS_TES)), sts);
1567 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1571 static int iommu_init_domains(struct intel_iommu *iommu)
1573 u32 ndomains, nlongs;
1576 ndomains = cap_ndoms(iommu->cap);
1577 pr_debug("%s: Number of Domains supported <%d>\n",
1578 iommu->name, ndomains);
1579 nlongs = BITS_TO_LONGS(ndomains);
1581 spin_lock_init(&iommu->lock);
1583 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1584 if (!iommu->domain_ids) {
1585 pr_err("%s: Allocating domain id array failed\n",
1590 size = ((ndomains >> 8) + 1) * sizeof(struct dmar_domain **);
1591 iommu->domains = kzalloc(size, GFP_KERNEL);
1593 if (iommu->domains) {
1594 size = 256 * sizeof(struct dmar_domain *);
1595 iommu->domains[0] = kzalloc(size, GFP_KERNEL);
1598 if (!iommu->domains || !iommu->domains[0]) {
1599 pr_err("%s: Allocating domain array failed\n",
1601 kfree(iommu->domain_ids);
1602 kfree(iommu->domains);
1603 iommu->domain_ids = NULL;
1604 iommu->domains = NULL;
1611 * If Caching mode is set, then invalid translations are tagged
1612 * with domain-id 0, hence we need to pre-allocate it. We also
1613 * use domain-id 0 as a marker for non-allocated domain-id, so
1614 * make sure it is not used for a real domain.
1616 set_bit(0, iommu->domain_ids);
1621 static void disable_dmar_iommu(struct intel_iommu *iommu)
1623 struct device_domain_info *info, *tmp;
1624 unsigned long flags;
1626 if (!iommu->domains || !iommu->domain_ids)
1629 spin_lock_irqsave(&device_domain_lock, flags);
1630 list_for_each_entry_safe(info, tmp, &device_domain_list, global) {
1631 struct dmar_domain *domain;
1633 if (info->iommu != iommu)
1636 if (!info->dev || !info->domain)
1639 domain = info->domain;
1641 dmar_remove_one_dev_info(domain, info->dev);
1643 if (!domain_type_is_vm_or_si(domain))
1644 domain_exit(domain);
1646 spin_unlock_irqrestore(&device_domain_lock, flags);
1648 if (iommu->gcmd & DMA_GCMD_TE)
1649 iommu_disable_translation(iommu);
1652 static void free_dmar_iommu(struct intel_iommu *iommu)
1654 if ((iommu->domains) && (iommu->domain_ids)) {
1655 int elems = (cap_ndoms(iommu->cap) >> 8) + 1;
1658 for (i = 0; i < elems; i++)
1659 kfree(iommu->domains[i]);
1660 kfree(iommu->domains);
1661 kfree(iommu->domain_ids);
1662 iommu->domains = NULL;
1663 iommu->domain_ids = NULL;
1666 g_iommus[iommu->seq_id] = NULL;
1668 /* free context mapping */
1669 free_context_table(iommu);
1672 static struct dmar_domain *alloc_domain(int flags)
1674 struct dmar_domain *domain;
1676 domain = alloc_domain_mem();
1680 memset(domain, 0, sizeof(*domain));
1682 domain->flags = flags;
1683 INIT_LIST_HEAD(&domain->devices);
1688 /* Must be called with iommu->lock */
1689 static int domain_attach_iommu(struct dmar_domain *domain,
1690 struct intel_iommu *iommu)
1692 unsigned long ndomains;
1695 assert_spin_locked(&device_domain_lock);
1696 assert_spin_locked(&iommu->lock);
1698 domain->iommu_refcnt[iommu->seq_id] += 1;
1699 domain->iommu_count += 1;
1700 if (domain->iommu_refcnt[iommu->seq_id] == 1) {
1701 ndomains = cap_ndoms(iommu->cap);
1702 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1704 if (num >= ndomains) {
1705 pr_err("%s: No free domain ids\n", iommu->name);
1706 domain->iommu_refcnt[iommu->seq_id] -= 1;
1707 domain->iommu_count -= 1;
1711 set_bit(num, iommu->domain_ids);
1712 set_iommu_domain(iommu, num, domain);
1714 domain->iommu_did[iommu->seq_id] = num;
1715 domain->nid = iommu->node;
1717 domain_update_iommu_cap(domain);
1723 static int domain_detach_iommu(struct dmar_domain *domain,
1724 struct intel_iommu *iommu)
1726 int num, count = INT_MAX;
1728 assert_spin_locked(&device_domain_lock);
1729 assert_spin_locked(&iommu->lock);
1731 domain->iommu_refcnt[iommu->seq_id] -= 1;
1732 count = --domain->iommu_count;
1733 if (domain->iommu_refcnt[iommu->seq_id] == 0) {
1734 num = domain->iommu_did[iommu->seq_id];
1735 clear_bit(num, iommu->domain_ids);
1736 set_iommu_domain(iommu, num, NULL);
1738 domain_update_iommu_cap(domain);
1739 domain->iommu_did[iommu->seq_id] = 0;
1745 static struct iova_domain reserved_iova_list;
1746 static struct lock_class_key reserved_rbtree_key;
1748 static int dmar_init_reserved_ranges(void)
1750 struct pci_dev *pdev = NULL;
1754 init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN,
1757 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1758 &reserved_rbtree_key);
1760 /* IOAPIC ranges shouldn't be accessed by DMA */
1761 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1762 IOVA_PFN(IOAPIC_RANGE_END));
1764 pr_err("Reserve IOAPIC range failed\n");
1768 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1769 for_each_pci_dev(pdev) {
1772 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1773 r = &pdev->resource[i];
1774 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1776 iova = reserve_iova(&reserved_iova_list,
1780 pr_err("Reserve iova failed\n");
1788 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1790 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1793 static inline int guestwidth_to_adjustwidth(int gaw)
1796 int r = (gaw - 12) % 9;
1807 static int domain_init(struct dmar_domain *domain, struct intel_iommu *iommu,
1810 int adjust_width, agaw;
1811 unsigned long sagaw;
1813 init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
1815 domain_reserve_special_ranges(domain);
1817 /* calculate AGAW */
1818 if (guest_width > cap_mgaw(iommu->cap))
1819 guest_width = cap_mgaw(iommu->cap);
1820 domain->gaw = guest_width;
1821 adjust_width = guestwidth_to_adjustwidth(guest_width);
1822 agaw = width_to_agaw(adjust_width);
1823 sagaw = cap_sagaw(iommu->cap);
1824 if (!test_bit(agaw, &sagaw)) {
1825 /* hardware doesn't support it, choose a bigger one */
1826 pr_debug("Hardware doesn't support agaw %d\n", agaw);
1827 agaw = find_next_bit(&sagaw, 5, agaw);
1831 domain->agaw = agaw;
1833 if (ecap_coherent(iommu->ecap))
1834 domain->iommu_coherency = 1;
1836 domain->iommu_coherency = 0;
1838 if (ecap_sc_support(iommu->ecap))
1839 domain->iommu_snooping = 1;
1841 domain->iommu_snooping = 0;
1843 if (intel_iommu_superpage)
1844 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1846 domain->iommu_superpage = 0;
1848 domain->nid = iommu->node;
1850 /* always allocate the top pgd */
1851 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
1854 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1858 static void domain_exit(struct dmar_domain *domain)
1860 struct page *freelist = NULL;
1862 /* Domain 0 is reserved, so dont process it */
1866 /* Flush any lazy unmaps that may reference this domain */
1867 if (!intel_iommu_strict)
1868 flush_unmaps_timeout(0);
1870 /* Remove associated devices and clear attached or cached domains */
1872 domain_remove_dev_info(domain);
1876 put_iova_domain(&domain->iovad);
1878 freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1880 dma_free_pagelist(freelist);
1882 free_domain_mem(domain);
1885 static int domain_context_mapping_one(struct dmar_domain *domain,
1886 struct intel_iommu *iommu,
1889 u16 did = domain->iommu_did[iommu->seq_id];
1890 int translation = CONTEXT_TT_MULTI_LEVEL;
1891 struct device_domain_info *info = NULL;
1892 struct context_entry *context;
1893 unsigned long flags;
1894 struct dma_pte *pgd;
1899 if (hw_pass_through && domain_type_is_si(domain))
1900 translation = CONTEXT_TT_PASS_THROUGH;
1902 pr_debug("Set context mapping for %02x:%02x.%d\n",
1903 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1905 BUG_ON(!domain->pgd);
1907 spin_lock_irqsave(&device_domain_lock, flags);
1908 spin_lock(&iommu->lock);
1911 context = iommu_context_addr(iommu, bus, devfn, 1);
1916 if (context_present(context))
1921 context_clear_entry(context);
1922 context_set_domain_id(context, did);
1925 * Skip top levels of page tables for iommu which has less agaw
1926 * than default. Unnecessary for PT mode.
1928 if (translation != CONTEXT_TT_PASS_THROUGH) {
1929 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1931 pgd = phys_to_virt(dma_pte_addr(pgd));
1932 if (!dma_pte_present(pgd))
1936 info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
1937 translation = info ? CONTEXT_TT_DEV_IOTLB :
1938 CONTEXT_TT_MULTI_LEVEL;
1940 context_set_address_root(context, virt_to_phys(pgd));
1941 context_set_address_width(context, iommu->agaw);
1944 * In pass through mode, AW must be programmed to
1945 * indicate the largest AGAW value supported by
1946 * hardware. And ASR is ignored by hardware.
1948 context_set_address_width(context, iommu->msagaw);
1951 context_set_translation_type(context, translation);
1952 context_set_fault_enable(context);
1953 context_set_present(context);
1954 domain_flush_cache(domain, context, sizeof(*context));
1957 * It's a non-present to present mapping. If hardware doesn't cache
1958 * non-present entry we only need to flush the write-buffer. If the
1959 * _does_ cache non-present entries, then it does so in the special
1960 * domain #0, which we have to flush:
1962 if (cap_caching_mode(iommu->cap)) {
1963 iommu->flush.flush_context(iommu, 0,
1964 (((u16)bus) << 8) | devfn,
1965 DMA_CCMD_MASK_NOBIT,
1966 DMA_CCMD_DEVICE_INVL);
1967 iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
1969 iommu_flush_write_buffer(iommu);
1971 iommu_enable_dev_iotlb(info);
1976 spin_unlock(&iommu->lock);
1977 spin_unlock_irqrestore(&device_domain_lock, flags);
1982 struct domain_context_mapping_data {
1983 struct dmar_domain *domain;
1984 struct intel_iommu *iommu;
1987 static int domain_context_mapping_cb(struct pci_dev *pdev,
1988 u16 alias, void *opaque)
1990 struct domain_context_mapping_data *data = opaque;
1992 return domain_context_mapping_one(data->domain, data->iommu,
1993 PCI_BUS_NUM(alias), alias & 0xff);
1997 domain_context_mapping(struct dmar_domain *domain, struct device *dev)
1999 struct intel_iommu *iommu;
2001 struct domain_context_mapping_data data;
2003 iommu = device_to_iommu(dev, &bus, &devfn);
2007 if (!dev_is_pci(dev))
2008 return domain_context_mapping_one(domain, iommu, bus, devfn);
2010 data.domain = domain;
2013 return pci_for_each_dma_alias(to_pci_dev(dev),
2014 &domain_context_mapping_cb, &data);
2017 static int domain_context_mapped_cb(struct pci_dev *pdev,
2018 u16 alias, void *opaque)
2020 struct intel_iommu *iommu = opaque;
2022 return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff);
2025 static int domain_context_mapped(struct device *dev)
2027 struct intel_iommu *iommu;
2030 iommu = device_to_iommu(dev, &bus, &devfn);
2034 if (!dev_is_pci(dev))
2035 return device_context_mapped(iommu, bus, devfn);
2037 return !pci_for_each_dma_alias(to_pci_dev(dev),
2038 domain_context_mapped_cb, iommu);
2041 /* Returns a number of VTD pages, but aligned to MM page size */
2042 static inline unsigned long aligned_nrpages(unsigned long host_addr,
2045 host_addr &= ~PAGE_MASK;
2046 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
2049 /* Return largest possible superpage level for a given mapping */
2050 static inline int hardware_largepage_caps(struct dmar_domain *domain,
2051 unsigned long iov_pfn,
2052 unsigned long phy_pfn,
2053 unsigned long pages)
2055 int support, level = 1;
2056 unsigned long pfnmerge;
2058 support = domain->iommu_superpage;
2060 /* To use a large page, the virtual *and* physical addresses
2061 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
2062 of them will mean we have to use smaller pages. So just
2063 merge them and check both at once. */
2064 pfnmerge = iov_pfn | phy_pfn;
2066 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
2067 pages >>= VTD_STRIDE_SHIFT;
2070 pfnmerge >>= VTD_STRIDE_SHIFT;
2077 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2078 struct scatterlist *sg, unsigned long phys_pfn,
2079 unsigned long nr_pages, int prot)
2081 struct dma_pte *first_pte = NULL, *pte = NULL;
2082 phys_addr_t uninitialized_var(pteval);
2083 unsigned long sg_res = 0;
2084 unsigned int largepage_lvl = 0;
2085 unsigned long lvl_pages = 0;
2087 BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1));
2089 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
2092 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
2096 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
2099 while (nr_pages > 0) {
2103 sg_res = aligned_nrpages(sg->offset, sg->length);
2104 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
2105 sg->dma_length = sg->length;
2106 pteval = (sg_phys(sg) & PAGE_MASK) | prot;
2107 phys_pfn = pteval >> VTD_PAGE_SHIFT;
2111 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
2113 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
2116 /* It is large page*/
2117 if (largepage_lvl > 1) {
2118 pteval |= DMA_PTE_LARGE_PAGE;
2119 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2121 * Ensure that old small page tables are
2122 * removed to make room for superpage,
2125 dma_pte_free_pagetable(domain, iov_pfn,
2126 iov_pfn + lvl_pages - 1);
2128 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
2132 /* We don't need lock here, nobody else
2133 * touches the iova range
2135 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
2137 static int dumps = 5;
2138 pr_crit("ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
2139 iov_pfn, tmp, (unsigned long long)pteval);
2142 debug_dma_dump_mappings(NULL);
2147 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2149 BUG_ON(nr_pages < lvl_pages);
2150 BUG_ON(sg_res < lvl_pages);
2152 nr_pages -= lvl_pages;
2153 iov_pfn += lvl_pages;
2154 phys_pfn += lvl_pages;
2155 pteval += lvl_pages * VTD_PAGE_SIZE;
2156 sg_res -= lvl_pages;
2158 /* If the next PTE would be the first in a new page, then we
2159 need to flush the cache on the entries we've just written.
2160 And then we'll need to recalculate 'pte', so clear it and
2161 let it get set again in the if (!pte) block above.
2163 If we're done (!nr_pages) we need to flush the cache too.
2165 Also if we've been setting superpages, we may need to
2166 recalculate 'pte' and switch back to smaller pages for the
2167 end of the mapping, if the trailing size is not enough to
2168 use another superpage (i.e. sg_res < lvl_pages). */
2170 if (!nr_pages || first_pte_in_page(pte) ||
2171 (largepage_lvl > 1 && sg_res < lvl_pages)) {
2172 domain_flush_cache(domain, first_pte,
2173 (void *)pte - (void *)first_pte);
2177 if (!sg_res && nr_pages)
2183 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2184 struct scatterlist *sg, unsigned long nr_pages,
2187 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
2190 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2191 unsigned long phys_pfn, unsigned long nr_pages,
2194 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
2197 static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn)
2202 clear_context_table(iommu, bus, devfn);
2203 iommu->flush.flush_context(iommu, 0, 0, 0,
2204 DMA_CCMD_GLOBAL_INVL);
2205 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2208 static inline void unlink_domain_info(struct device_domain_info *info)
2210 assert_spin_locked(&device_domain_lock);
2211 list_del(&info->link);
2212 list_del(&info->global);
2214 info->dev->archdata.iommu = NULL;
2217 static void domain_remove_dev_info(struct dmar_domain *domain)
2219 struct device_domain_info *info, *tmp;
2220 unsigned long flags;
2222 spin_lock_irqsave(&device_domain_lock, flags);
2223 list_for_each_entry_safe(info, tmp, &domain->devices, link)
2224 __dmar_remove_one_dev_info(info);
2225 spin_unlock_irqrestore(&device_domain_lock, flags);
2230 * Note: we use struct device->archdata.iommu stores the info
2232 static struct dmar_domain *find_domain(struct device *dev)
2234 struct device_domain_info *info;
2236 /* No lock here, assumes no domain exit in normal case */
2237 info = dev->archdata.iommu;
2239 return info->domain;
2243 static inline struct device_domain_info *
2244 dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
2246 struct device_domain_info *info;
2248 list_for_each_entry(info, &device_domain_list, global)
2249 if (info->iommu->segment == segment && info->bus == bus &&
2250 info->devfn == devfn)
2256 static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu,
2259 struct dmar_domain *domain)
2261 struct dmar_domain *found = NULL;
2262 struct device_domain_info *info;
2263 unsigned long flags;
2266 info = alloc_devinfo_mem();
2271 info->devfn = devfn;
2272 info->ats.enabled = 0;
2275 info->domain = domain;
2276 info->iommu = iommu;
2278 spin_lock_irqsave(&device_domain_lock, flags);
2280 found = find_domain(dev);
2283 struct device_domain_info *info2;
2284 info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn);
2286 found = info2->domain;
2292 spin_unlock_irqrestore(&device_domain_lock, flags);
2293 free_devinfo_mem(info);
2294 /* Caller must free the original domain */
2298 spin_lock(&iommu->lock);
2299 ret = domain_attach_iommu(domain, iommu);
2300 spin_unlock(&iommu->lock);
2303 spin_unlock_irqrestore(&device_domain_lock, flags);
2304 free_devinfo_mem(info);
2308 list_add(&info->link, &domain->devices);
2309 list_add(&info->global, &device_domain_list);
2311 dev->archdata.iommu = info;
2312 spin_unlock_irqrestore(&device_domain_lock, flags);
2314 if (dev && domain_context_mapping(domain, dev)) {
2315 pr_err("Domain context map for %s failed\n", dev_name(dev));
2316 dmar_remove_one_dev_info(domain, dev);
2323 static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque)
2325 *(u16 *)opaque = alias;
2329 /* domain is initialized */
2330 static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw)
2332 struct device_domain_info *info = NULL;
2333 struct dmar_domain *domain, *tmp;
2334 struct intel_iommu *iommu;
2335 u16 req_id, dma_alias;
2336 unsigned long flags;
2339 domain = find_domain(dev);
2343 iommu = device_to_iommu(dev, &bus, &devfn);
2347 req_id = ((u16)bus << 8) | devfn;
2349 if (dev_is_pci(dev)) {
2350 struct pci_dev *pdev = to_pci_dev(dev);
2352 pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias);
2354 spin_lock_irqsave(&device_domain_lock, flags);
2355 info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus),
2356 PCI_BUS_NUM(dma_alias),
2359 iommu = info->iommu;
2360 domain = info->domain;
2362 spin_unlock_irqrestore(&device_domain_lock, flags);
2364 /* DMA alias already has a domain, uses it */
2369 /* Allocate and initialize new domain for the device */
2370 domain = alloc_domain(0);
2373 if (domain_init(domain, iommu, gaw)) {
2374 domain_exit(domain);
2378 /* register PCI DMA alias device */
2379 if (req_id != dma_alias && dev_is_pci(dev)) {
2380 tmp = dmar_insert_one_dev_info(iommu, PCI_BUS_NUM(dma_alias),
2381 dma_alias & 0xff, NULL, domain);
2383 if (!tmp || tmp != domain) {
2384 domain_exit(domain);
2393 tmp = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain);
2395 if (!tmp || tmp != domain) {
2396 domain_exit(domain);
2403 static int iommu_identity_mapping;
2404 #define IDENTMAP_ALL 1
2405 #define IDENTMAP_GFX 2
2406 #define IDENTMAP_AZALIA 4
2408 static int iommu_domain_identity_map(struct dmar_domain *domain,
2409 unsigned long long start,
2410 unsigned long long end)
2412 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2413 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2415 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2416 dma_to_mm_pfn(last_vpfn))) {
2417 pr_err("Reserving iova failed\n");
2421 pr_debug("Mapping reserved region %llx-%llx\n", start, end);
2423 * RMRR range might have overlap with physical memory range,
2426 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
2428 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2429 last_vpfn - first_vpfn + 1,
2430 DMA_PTE_READ|DMA_PTE_WRITE);
2433 static int iommu_prepare_identity_map(struct device *dev,
2434 unsigned long long start,
2435 unsigned long long end)
2437 struct dmar_domain *domain;
2440 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2444 /* For _hardware_ passthrough, don't bother. But for software
2445 passthrough, we do it anyway -- it may indicate a memory
2446 range which is reserved in E820, so which didn't get set
2447 up to start with in si_domain */
2448 if (domain == si_domain && hw_pass_through) {
2449 pr_warn("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2450 dev_name(dev), start, end);
2454 pr_info("Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2455 dev_name(dev), start, end);
2458 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2459 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2460 dmi_get_system_info(DMI_BIOS_VENDOR),
2461 dmi_get_system_info(DMI_BIOS_VERSION),
2462 dmi_get_system_info(DMI_PRODUCT_VERSION));
2467 if (end >> agaw_to_width(domain->agaw)) {
2468 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2469 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2470 agaw_to_width(domain->agaw),
2471 dmi_get_system_info(DMI_BIOS_VENDOR),
2472 dmi_get_system_info(DMI_BIOS_VERSION),
2473 dmi_get_system_info(DMI_PRODUCT_VERSION));
2478 ret = iommu_domain_identity_map(domain, start, end);
2485 domain_exit(domain);
2489 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2492 if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2494 return iommu_prepare_identity_map(dev, rmrr->base_address,
2498 #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
2499 static inline void iommu_prepare_isa(void)
2501 struct pci_dev *pdev;
2504 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2508 pr_info("Prepare 0-16MiB unity mapping for LPC\n");
2509 ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
2512 pr_err("Failed to create 0-16MiB identity map - floppy might not work\n");
2517 static inline void iommu_prepare_isa(void)
2521 #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
2523 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2525 static int __init si_domain_init(int hw)
2529 si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY);
2533 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2534 domain_exit(si_domain);
2538 pr_debug("Identity mapping domain allocated\n");
2543 for_each_online_node(nid) {
2544 unsigned long start_pfn, end_pfn;
2547 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2548 ret = iommu_domain_identity_map(si_domain,
2549 PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2558 static int identity_mapping(struct device *dev)
2560 struct device_domain_info *info;
2562 if (likely(!iommu_identity_mapping))
2565 info = dev->archdata.iommu;
2566 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2567 return (info->domain == si_domain);
2572 static int domain_add_dev_info(struct dmar_domain *domain, struct device *dev)
2574 struct dmar_domain *ndomain;
2575 struct intel_iommu *iommu;
2578 iommu = device_to_iommu(dev, &bus, &devfn);
2582 ndomain = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain);
2583 if (ndomain != domain)
2589 static bool device_has_rmrr(struct device *dev)
2591 struct dmar_rmrr_unit *rmrr;
2596 for_each_rmrr_units(rmrr) {
2598 * Return TRUE if this RMRR contains the device that
2601 for_each_active_dev_scope(rmrr->devices,
2602 rmrr->devices_cnt, i, tmp)
2613 * There are a couple cases where we need to restrict the functionality of
2614 * devices associated with RMRRs. The first is when evaluating a device for
2615 * identity mapping because problems exist when devices are moved in and out
2616 * of domains and their respective RMRR information is lost. This means that
2617 * a device with associated RMRRs will never be in a "passthrough" domain.
2618 * The second is use of the device through the IOMMU API. This interface
2619 * expects to have full control of the IOVA space for the device. We cannot
2620 * satisfy both the requirement that RMRR access is maintained and have an
2621 * unencumbered IOVA space. We also have no ability to quiesce the device's
2622 * use of the RMRR space or even inform the IOMMU API user of the restriction.
2623 * We therefore prevent devices associated with an RMRR from participating in
2624 * the IOMMU API, which eliminates them from device assignment.
2626 * In both cases we assume that PCI USB devices with RMRRs have them largely
2627 * for historical reasons and that the RMRR space is not actively used post
2628 * boot. This exclusion may change if vendors begin to abuse it.
2630 * The same exception is made for graphics devices, with the requirement that
2631 * any use of the RMRR regions will be torn down before assigning the device
2634 static bool device_is_rmrr_locked(struct device *dev)
2636 if (!device_has_rmrr(dev))
2639 if (dev_is_pci(dev)) {
2640 struct pci_dev *pdev = to_pci_dev(dev);
2642 if (IS_USB_DEVICE(pdev) || IS_GFX_DEVICE(pdev))
2649 static int iommu_should_identity_map(struct device *dev, int startup)
2652 if (dev_is_pci(dev)) {
2653 struct pci_dev *pdev = to_pci_dev(dev);
2655 if (device_is_rmrr_locked(dev))
2658 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2661 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2664 if (!(iommu_identity_mapping & IDENTMAP_ALL))
2668 * We want to start off with all devices in the 1:1 domain, and
2669 * take them out later if we find they can't access all of memory.
2671 * However, we can't do this for PCI devices behind bridges,
2672 * because all PCI devices behind the same bridge will end up
2673 * with the same source-id on their transactions.
2675 * Practically speaking, we can't change things around for these
2676 * devices at run-time, because we can't be sure there'll be no
2677 * DMA transactions in flight for any of their siblings.
2679 * So PCI devices (unless they're on the root bus) as well as
2680 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2681 * the 1:1 domain, just in _case_ one of their siblings turns out
2682 * not to be able to map all of memory.
2684 if (!pci_is_pcie(pdev)) {
2685 if (!pci_is_root_bus(pdev->bus))
2687 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2689 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
2692 if (device_has_rmrr(dev))
2697 * At boot time, we don't yet know if devices will be 64-bit capable.
2698 * Assume that they will — if they turn out not to be, then we can
2699 * take them out of the 1:1 domain later.
2703 * If the device's dma_mask is less than the system's memory
2704 * size then this is not a candidate for identity mapping.
2706 u64 dma_mask = *dev->dma_mask;
2708 if (dev->coherent_dma_mask &&
2709 dev->coherent_dma_mask < dma_mask)
2710 dma_mask = dev->coherent_dma_mask;
2712 return dma_mask >= dma_get_required_mask(dev);
2718 static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw)
2722 if (!iommu_should_identity_map(dev, 1))
2725 ret = domain_add_dev_info(si_domain, dev);
2727 pr_info("%s identity mapping for device %s\n",
2728 hw ? "Hardware" : "Software", dev_name(dev));
2729 else if (ret == -ENODEV)
2730 /* device not associated with an iommu */
2737 static int __init iommu_prepare_static_identity_mapping(int hw)
2739 struct pci_dev *pdev = NULL;
2740 struct dmar_drhd_unit *drhd;
2741 struct intel_iommu *iommu;
2746 for_each_pci_dev(pdev) {
2747 ret = dev_prepare_static_identity_mapping(&pdev->dev, hw);
2752 for_each_active_iommu(iommu, drhd)
2753 for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) {
2754 struct acpi_device_physical_node *pn;
2755 struct acpi_device *adev;
2757 if (dev->bus != &acpi_bus_type)
2760 adev= to_acpi_device(dev);
2761 mutex_lock(&adev->physical_node_lock);
2762 list_for_each_entry(pn, &adev->physical_node_list, node) {
2763 ret = dev_prepare_static_identity_mapping(pn->dev, hw);
2767 mutex_unlock(&adev->physical_node_lock);
2775 static void intel_iommu_init_qi(struct intel_iommu *iommu)
2778 * Start from the sane iommu hardware state.
2779 * If the queued invalidation is already initialized by us
2780 * (for example, while enabling interrupt-remapping) then
2781 * we got the things already rolling from a sane state.
2785 * Clear any previous faults.
2787 dmar_fault(-1, iommu);
2789 * Disable queued invalidation if supported and already enabled
2790 * before OS handover.
2792 dmar_disable_qi(iommu);
2795 if (dmar_enable_qi(iommu)) {
2797 * Queued Invalidate not enabled, use Register Based Invalidate
2799 iommu->flush.flush_context = __iommu_flush_context;
2800 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2801 pr_info("%s: Using Register based invalidation\n",
2804 iommu->flush.flush_context = qi_flush_context;
2805 iommu->flush.flush_iotlb = qi_flush_iotlb;
2806 pr_info("%s: Using Queued invalidation\n", iommu->name);
2810 static int copy_context_table(struct intel_iommu *iommu,
2811 struct root_entry __iomem *old_re,
2812 struct context_entry **tbl,
2815 int tbl_idx, pos = 0, idx, devfn, ret = 0, did;
2816 struct context_entry __iomem *old_ce = NULL;
2817 struct context_entry *new_ce = NULL, ce;
2818 struct root_entry re;
2819 phys_addr_t old_ce_phys;
2821 tbl_idx = ext ? bus * 2 : bus;
2822 memcpy_fromio(&re, old_re, sizeof(re));
2824 for (devfn = 0; devfn < 256; devfn++) {
2825 /* First calculate the correct index */
2826 idx = (ext ? devfn * 2 : devfn) % 256;
2829 /* First save what we may have and clean up */
2831 tbl[tbl_idx] = new_ce;
2832 __iommu_flush_cache(iommu, new_ce,
2842 old_ce_phys = root_entry_lctp(&re);
2844 old_ce_phys = root_entry_uctp(&re);
2847 if (ext && devfn == 0) {
2848 /* No LCTP, try UCTP */
2857 old_ce = ioremap_cache(old_ce_phys, PAGE_SIZE);
2861 new_ce = alloc_pgtable_page(iommu->node);
2868 /* Now copy the context entry */
2869 memcpy_fromio(&ce, old_ce + idx, sizeof(ce));
2871 if (!__context_present(&ce))
2874 did = context_domain_id(&ce);
2875 if (did >= 0 && did < cap_ndoms(iommu->cap))
2876 set_bit(did, iommu->domain_ids);
2879 * We need a marker for copied context entries. This
2880 * marker needs to work for the old format as well as
2881 * for extended context entries.
2883 * Bit 67 of the context entry is used. In the old
2884 * format this bit is available to software, in the
2885 * extended format it is the PGE bit, but PGE is ignored
2886 * by HW if PASIDs are disabled (and thus still
2889 * So disable PASIDs first and then mark the entry
2890 * copied. This means that we don't copy PASID
2891 * translations from the old kernel, but this is fine as
2892 * faults there are not fatal.
2894 context_clear_pasid_enable(&ce);
2895 context_set_copied(&ce);
2900 tbl[tbl_idx + pos] = new_ce;
2902 __iommu_flush_cache(iommu, new_ce, VTD_PAGE_SIZE);
2911 static int copy_translation_tables(struct intel_iommu *iommu)
2913 struct root_entry __iomem *old_rt;
2914 struct context_entry **ctxt_tbls;
2915 phys_addr_t old_rt_phys;
2916 int ctxt_table_entries;
2917 unsigned long flags;
2922 rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG);
2923 ext = !!(rtaddr_reg & DMA_RTADDR_RTT);
2924 new_ext = !!ecap_ecs(iommu->ecap);
2927 * The RTT bit can only be changed when translation is disabled,
2928 * but disabling translation means to open a window for data
2929 * corruption. So bail out and don't copy anything if we would
2930 * have to change the bit.
2935 old_rt_phys = rtaddr_reg & VTD_PAGE_MASK;
2939 old_rt = ioremap_cache(old_rt_phys, PAGE_SIZE);
2943 /* This is too big for the stack - allocate it from slab */
2944 ctxt_table_entries = ext ? 512 : 256;
2946 ctxt_tbls = kzalloc(ctxt_table_entries * sizeof(void *), GFP_KERNEL);
2950 for (bus = 0; bus < 256; bus++) {
2951 ret = copy_context_table(iommu, &old_rt[bus],
2952 ctxt_tbls, bus, ext);
2954 pr_err("%s: Failed to copy context table for bus %d\n",
2960 spin_lock_irqsave(&iommu->lock, flags);
2962 /* Context tables are copied, now write them to the root_entry table */
2963 for (bus = 0; bus < 256; bus++) {
2964 int idx = ext ? bus * 2 : bus;
2967 if (ctxt_tbls[idx]) {
2968 val = virt_to_phys(ctxt_tbls[idx]) | 1;
2969 iommu->root_entry[bus].lo = val;
2972 if (!ext || !ctxt_tbls[idx + 1])
2975 val = virt_to_phys(ctxt_tbls[idx + 1]) | 1;
2976 iommu->root_entry[bus].hi = val;
2979 spin_unlock_irqrestore(&iommu->lock, flags);
2983 __iommu_flush_cache(iommu, iommu->root_entry, PAGE_SIZE);
2993 static int __init init_dmars(void)
2995 struct dmar_drhd_unit *drhd;
2996 struct dmar_rmrr_unit *rmrr;
2997 bool copied_tables = false;
2999 struct intel_iommu *iommu;
3005 * initialize and program root entry to not present
3008 for_each_drhd_unit(drhd) {
3010 * lock not needed as this is only incremented in the single
3011 * threaded kernel __init code path all other access are read
3014 if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) {
3018 pr_err_once("Exceeded %d IOMMUs\n", DMAR_UNITS_SUPPORTED);
3021 /* Preallocate enough resources for IOMMU hot-addition */
3022 if (g_num_of_iommus < DMAR_UNITS_SUPPORTED)
3023 g_num_of_iommus = DMAR_UNITS_SUPPORTED;
3025 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
3028 pr_err("Allocating global iommu array failed\n");
3033 deferred_flush = kzalloc(g_num_of_iommus *
3034 sizeof(struct deferred_flush_tables), GFP_KERNEL);
3035 if (!deferred_flush) {
3040 for_each_active_iommu(iommu, drhd) {
3041 g_iommus[iommu->seq_id] = iommu;
3043 intel_iommu_init_qi(iommu);
3045 ret = iommu_init_domains(iommu);
3049 init_translation_status(iommu);
3051 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
3052 iommu_disable_translation(iommu);
3053 clear_translation_pre_enabled(iommu);
3054 pr_warn("Translation was enabled for %s but we are not in kdump mode\n",
3060 * we could share the same root & context tables
3061 * among all IOMMU's. Need to Split it later.
3063 ret = iommu_alloc_root_entry(iommu);
3067 if (translation_pre_enabled(iommu)) {
3068 pr_info("Translation already enabled - trying to copy translation structures\n");
3070 ret = copy_translation_tables(iommu);
3073 * We found the IOMMU with translation
3074 * enabled - but failed to copy over the
3075 * old root-entry table. Try to proceed
3076 * by disabling translation now and
3077 * allocating a clean root-entry table.
3078 * This might cause DMAR faults, but
3079 * probably the dump will still succeed.
3081 pr_err("Failed to copy translation tables from previous kernel for %s\n",
3083 iommu_disable_translation(iommu);
3084 clear_translation_pre_enabled(iommu);
3086 pr_info("Copied translation tables from previous kernel for %s\n",
3088 copied_tables = true;
3092 iommu_flush_write_buffer(iommu);
3093 iommu_set_root_entry(iommu);
3094 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
3095 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3097 if (!ecap_pass_through(iommu->ecap))
3098 hw_pass_through = 0;
3101 if (iommu_pass_through)
3102 iommu_identity_mapping |= IDENTMAP_ALL;
3104 #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
3105 iommu_identity_mapping |= IDENTMAP_GFX;
3108 if (iommu_identity_mapping) {
3109 ret = si_domain_init(hw_pass_through);
3114 check_tylersburg_isoch();
3117 * If we copied translations from a previous kernel in the kdump
3118 * case, we can not assign the devices to domains now, as that
3119 * would eliminate the old mappings. So skip this part and defer
3120 * the assignment to device driver initialization time.
3126 * If pass through is not set or not enabled, setup context entries for
3127 * identity mappings for rmrr, gfx, and isa and may fall back to static
3128 * identity mapping if iommu_identity_mapping is set.
3130 if (iommu_identity_mapping) {
3131 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
3133 pr_crit("Failed to setup IOMMU pass-through\n");
3139 * for each dev attached to rmrr
3141 * locate drhd for dev, alloc domain for dev
3142 * allocate free domain
3143 * allocate page table entries for rmrr
3144 * if context not allocated for bus
3145 * allocate and init context
3146 * set present in root table for this bus
3147 * init context with domain, translation etc
3151 pr_info("Setting RMRR:\n");
3152 for_each_rmrr_units(rmrr) {
3153 /* some BIOS lists non-exist devices in DMAR table. */
3154 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
3156 ret = iommu_prepare_rmrr_dev(rmrr, dev);
3158 pr_err("Mapping reserved region failed\n");
3162 iommu_prepare_isa();
3169 * global invalidate context cache
3170 * global invalidate iotlb
3171 * enable translation
3173 for_each_iommu(iommu, drhd) {
3174 if (drhd->ignored) {
3176 * we always have to disable PMRs or DMA may fail on
3180 iommu_disable_protect_mem_regions(iommu);
3184 iommu_flush_write_buffer(iommu);
3186 ret = dmar_set_interrupt(iommu);
3190 if (!translation_pre_enabled(iommu))
3191 iommu_enable_translation(iommu);
3193 iommu_disable_protect_mem_regions(iommu);
3199 for_each_active_iommu(iommu, drhd) {
3200 disable_dmar_iommu(iommu);
3201 free_dmar_iommu(iommu);
3203 kfree(deferred_flush);
3210 /* This takes a number of _MM_ pages, not VTD pages */
3211 static struct iova *intel_alloc_iova(struct device *dev,
3212 struct dmar_domain *domain,
3213 unsigned long nrpages, uint64_t dma_mask)
3215 struct iova *iova = NULL;
3217 /* Restrict dma_mask to the width that the iommu can handle */
3218 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
3219 /* Ensure we reserve the whole size-aligned region */
3220 nrpages = __roundup_pow_of_two(nrpages);
3222 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
3224 * First try to allocate an io virtual address in
3225 * DMA_BIT_MASK(32) and if that fails then try allocating
3228 iova = alloc_iova(&domain->iovad, nrpages,
3229 IOVA_PFN(DMA_BIT_MASK(32)), 1);
3233 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
3234 if (unlikely(!iova)) {
3235 pr_err("Allocating %ld-page iova for %s failed",
3236 nrpages, dev_name(dev));
3243 static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
3245 struct dmar_domain *domain;
3247 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
3249 pr_err("Allocating domain for %s failed\n",
3257 static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
3259 struct device_domain_info *info;
3261 /* No lock here, assumes no domain exit in normal case */
3262 info = dev->archdata.iommu;
3264 return info->domain;
3266 return __get_valid_domain_for_dev(dev);
3269 /* Check if the dev needs to go through non-identity map and unmap process.*/
3270 static int iommu_no_mapping(struct device *dev)
3274 if (iommu_dummy(dev))
3277 if (!iommu_identity_mapping)
3280 found = identity_mapping(dev);
3282 if (iommu_should_identity_map(dev, 0))
3286 * 32 bit DMA is removed from si_domain and fall back
3287 * to non-identity mapping.
3289 dmar_remove_one_dev_info(si_domain, dev);
3290 pr_info("32bit %s uses non-identity mapping\n",
3296 * In case of a detached 64 bit DMA device from vm, the device
3297 * is put into si_domain for identity mapping.
3299 if (iommu_should_identity_map(dev, 0)) {
3301 ret = domain_add_dev_info(si_domain, dev);
3303 pr_info("64bit %s uses identity mapping\n",
3313 static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
3314 size_t size, int dir, u64 dma_mask)
3316 struct dmar_domain *domain;
3317 phys_addr_t start_paddr;
3321 struct intel_iommu *iommu;
3322 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
3324 BUG_ON(dir == DMA_NONE);
3326 if (iommu_no_mapping(dev))
3329 domain = get_valid_domain_for_dev(dev);
3333 iommu = domain_get_iommu(domain);
3334 size = aligned_nrpages(paddr, size);
3336 iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask);
3341 * Check if DMAR supports zero-length reads on write only
3344 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3345 !cap_zlr(iommu->cap))
3346 prot |= DMA_PTE_READ;
3347 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3348 prot |= DMA_PTE_WRITE;
3350 * paddr - (paddr + size) might be partial page, we should map the whole
3351 * page. Note: if two part of one page are separately mapped, we
3352 * might have two guest_addr mapping to the same host paddr, but this
3353 * is not a big problem
3355 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
3356 mm_to_dma_pfn(paddr_pfn), size, prot);
3360 /* it's a non-present to present mapping. Only flush if caching mode */
3361 if (cap_caching_mode(iommu->cap))
3362 iommu_flush_iotlb_psi(iommu, domain,
3363 mm_to_dma_pfn(iova->pfn_lo),
3366 iommu_flush_write_buffer(iommu);
3368 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
3369 start_paddr += paddr & ~PAGE_MASK;
3374 __free_iova(&domain->iovad, iova);
3375 pr_err("Device %s request: %zx@%llx dir %d --- failed\n",
3376 dev_name(dev), size, (unsigned long long)paddr, dir);
3380 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
3381 unsigned long offset, size_t size,
3382 enum dma_data_direction dir,
3383 struct dma_attrs *attrs)
3385 return __intel_map_single(dev, page_to_phys(page) + offset, size,
3386 dir, *dev->dma_mask);
3389 static void flush_unmaps(void)
3395 /* just flush them all */
3396 for (i = 0; i < g_num_of_iommus; i++) {
3397 struct intel_iommu *iommu = g_iommus[i];
3401 if (!deferred_flush[i].next)
3404 /* In caching mode, global flushes turn emulation expensive */
3405 if (!cap_caching_mode(iommu->cap))
3406 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3407 DMA_TLB_GLOBAL_FLUSH);
3408 for (j = 0; j < deferred_flush[i].next; j++) {
3410 struct iova *iova = deferred_flush[i].iova[j];
3411 struct dmar_domain *domain = deferred_flush[i].domain[j];
3413 /* On real hardware multiple invalidations are expensive */
3414 if (cap_caching_mode(iommu->cap))
3415 iommu_flush_iotlb_psi(iommu, domain,
3416 iova->pfn_lo, iova_size(iova),
3417 !deferred_flush[i].freelist[j], 0);
3419 mask = ilog2(mm_to_dma_pfn(iova_size(iova)));
3420 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
3421 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
3423 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
3424 if (deferred_flush[i].freelist[j])
3425 dma_free_pagelist(deferred_flush[i].freelist[j]);
3427 deferred_flush[i].next = 0;
3433 static void flush_unmaps_timeout(unsigned long data)
3435 unsigned long flags;
3437 spin_lock_irqsave(&async_umap_flush_lock, flags);
3439 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3442 static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
3444 unsigned long flags;
3446 struct intel_iommu *iommu;
3448 spin_lock_irqsave(&async_umap_flush_lock, flags);
3449 if (list_size == HIGH_WATER_MARK)
3452 iommu = domain_get_iommu(dom);
3453 iommu_id = iommu->seq_id;
3455 next = deferred_flush[iommu_id].next;
3456 deferred_flush[iommu_id].domain[next] = dom;
3457 deferred_flush[iommu_id].iova[next] = iova;
3458 deferred_flush[iommu_id].freelist[next] = freelist;
3459 deferred_flush[iommu_id].next++;
3462 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
3466 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3469 static void intel_unmap(struct device *dev, dma_addr_t dev_addr)
3471 struct dmar_domain *domain;
3472 unsigned long start_pfn, last_pfn;
3474 struct intel_iommu *iommu;
3475 struct page *freelist;
3477 if (iommu_no_mapping(dev))
3480 domain = find_domain(dev);
3483 iommu = domain_get_iommu(domain);
3485 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
3486 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
3487 (unsigned long long)dev_addr))
3490 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3491 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
3493 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
3494 dev_name(dev), start_pfn, last_pfn);
3496 freelist = domain_unmap(domain, start_pfn, last_pfn);
3498 if (intel_iommu_strict) {
3499 iommu_flush_iotlb_psi(iommu, domain, start_pfn,
3500 last_pfn - start_pfn + 1, !freelist, 0);
3502 __free_iova(&domain->iovad, iova);
3503 dma_free_pagelist(freelist);
3505 add_unmap(domain, iova, freelist);
3507 * queue up the release of the unmap to save the 1/6th of the
3508 * cpu used up by the iotlb flush operation...
3513 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
3514 size_t size, enum dma_data_direction dir,
3515 struct dma_attrs *attrs)
3517 intel_unmap(dev, dev_addr);
3520 static void *intel_alloc_coherent(struct device *dev, size_t size,
3521 dma_addr_t *dma_handle, gfp_t flags,
3522 struct dma_attrs *attrs)
3524 struct page *page = NULL;
3527 size = PAGE_ALIGN(size);
3528 order = get_order(size);
3530 if (!iommu_no_mapping(dev))
3531 flags &= ~(GFP_DMA | GFP_DMA32);
3532 else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) {
3533 if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
3539 if (flags & __GFP_WAIT) {
3540 unsigned int count = size >> PAGE_SHIFT;
3542 page = dma_alloc_from_contiguous(dev, count, order);
3543 if (page && iommu_no_mapping(dev) &&
3544 page_to_phys(page) + size > dev->coherent_dma_mask) {
3545 dma_release_from_contiguous(dev, page, count);
3551 page = alloc_pages(flags, order);
3554 memset(page_address(page), 0, size);
3556 *dma_handle = __intel_map_single(dev, page_to_phys(page), size,
3558 dev->coherent_dma_mask);
3560 return page_address(page);
3561 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3562 __free_pages(page, order);
3567 static void intel_free_coherent(struct device *dev, size_t size, void *vaddr,
3568 dma_addr_t dma_handle, struct dma_attrs *attrs)
3571 struct page *page = virt_to_page(vaddr);
3573 size = PAGE_ALIGN(size);
3574 order = get_order(size);
3576 intel_unmap(dev, dma_handle);
3577 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3578 __free_pages(page, order);
3581 static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist,
3582 int nelems, enum dma_data_direction dir,
3583 struct dma_attrs *attrs)
3585 intel_unmap(dev, sglist[0].dma_address);
3588 static int intel_nontranslate_map_sg(struct device *hddev,
3589 struct scatterlist *sglist, int nelems, int dir)
3592 struct scatterlist *sg;
3594 for_each_sg(sglist, sg, nelems, i) {
3595 BUG_ON(!sg_page(sg));
3596 sg->dma_address = sg_phys(sg);
3597 sg->dma_length = sg->length;
3602 static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems,
3603 enum dma_data_direction dir, struct dma_attrs *attrs)
3606 struct dmar_domain *domain;
3609 struct iova *iova = NULL;
3611 struct scatterlist *sg;
3612 unsigned long start_vpfn;
3613 struct intel_iommu *iommu;
3615 BUG_ON(dir == DMA_NONE);
3616 if (iommu_no_mapping(dev))
3617 return intel_nontranslate_map_sg(dev, sglist, nelems, dir);
3619 domain = get_valid_domain_for_dev(dev);
3623 iommu = domain_get_iommu(domain);
3625 for_each_sg(sglist, sg, nelems, i)
3626 size += aligned_nrpages(sg->offset, sg->length);
3628 iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size),
3631 sglist->dma_length = 0;
3636 * Check if DMAR supports zero-length reads on write only
3639 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3640 !cap_zlr(iommu->cap))
3641 prot |= DMA_PTE_READ;
3642 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3643 prot |= DMA_PTE_WRITE;
3645 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
3647 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
3648 if (unlikely(ret)) {
3649 dma_pte_free_pagetable(domain, start_vpfn,
3650 start_vpfn + size - 1);
3651 __free_iova(&domain->iovad, iova);
3655 /* it's a non-present to present mapping. Only flush if caching mode */
3656 if (cap_caching_mode(iommu->cap))
3657 iommu_flush_iotlb_psi(iommu, domain, start_vpfn, size, 0, 1);
3659 iommu_flush_write_buffer(iommu);
3664 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3669 struct dma_map_ops intel_dma_ops = {
3670 .alloc = intel_alloc_coherent,
3671 .free = intel_free_coherent,
3672 .map_sg = intel_map_sg,
3673 .unmap_sg = intel_unmap_sg,
3674 .map_page = intel_map_page,
3675 .unmap_page = intel_unmap_page,
3676 .mapping_error = intel_mapping_error,
3679 static inline int iommu_domain_cache_init(void)
3683 iommu_domain_cache = kmem_cache_create("iommu_domain",
3684 sizeof(struct dmar_domain),
3689 if (!iommu_domain_cache) {
3690 pr_err("Couldn't create iommu_domain cache\n");
3697 static inline int iommu_devinfo_cache_init(void)
3701 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3702 sizeof(struct device_domain_info),
3706 if (!iommu_devinfo_cache) {
3707 pr_err("Couldn't create devinfo cache\n");
3714 static int __init iommu_init_mempool(void)
3717 ret = iova_cache_get();
3721 ret = iommu_domain_cache_init();
3725 ret = iommu_devinfo_cache_init();
3729 kmem_cache_destroy(iommu_domain_cache);
3736 static void __init iommu_exit_mempool(void)
3738 kmem_cache_destroy(iommu_devinfo_cache);
3739 kmem_cache_destroy(iommu_domain_cache);
3743 static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3745 struct dmar_drhd_unit *drhd;
3749 /* We know that this device on this chipset has its own IOMMU.
3750 * If we find it under a different IOMMU, then the BIOS is lying
3751 * to us. Hope that the IOMMU for this device is actually
3752 * disabled, and it needs no translation...
3754 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3756 /* "can't" happen */
3757 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3760 vtbar &= 0xffff0000;
3762 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3763 drhd = dmar_find_matched_drhd_unit(pdev);
3764 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3765 TAINT_FIRMWARE_WORKAROUND,
3766 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3767 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3769 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3771 static void __init init_no_remapping_devices(void)
3773 struct dmar_drhd_unit *drhd;
3777 for_each_drhd_unit(drhd) {
3778 if (!drhd->include_all) {
3779 for_each_active_dev_scope(drhd->devices,
3780 drhd->devices_cnt, i, dev)
3782 /* ignore DMAR unit if no devices exist */
3783 if (i == drhd->devices_cnt)
3788 for_each_active_drhd_unit(drhd) {
3789 if (drhd->include_all)
3792 for_each_active_dev_scope(drhd->devices,
3793 drhd->devices_cnt, i, dev)
3794 if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
3796 if (i < drhd->devices_cnt)
3799 /* This IOMMU has *only* gfx devices. Either bypass it or
3800 set the gfx_mapped flag, as appropriate */
3802 intel_iommu_gfx_mapped = 1;
3805 for_each_active_dev_scope(drhd->devices,
3806 drhd->devices_cnt, i, dev)
3807 dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3812 #ifdef CONFIG_SUSPEND
3813 static int init_iommu_hw(void)
3815 struct dmar_drhd_unit *drhd;
3816 struct intel_iommu *iommu = NULL;
3818 for_each_active_iommu(iommu, drhd)
3820 dmar_reenable_qi(iommu);
3822 for_each_iommu(iommu, drhd) {
3823 if (drhd->ignored) {
3825 * we always have to disable PMRs or DMA may fail on
3829 iommu_disable_protect_mem_regions(iommu);
3833 iommu_flush_write_buffer(iommu);
3835 iommu_set_root_entry(iommu);
3837 iommu->flush.flush_context(iommu, 0, 0, 0,
3838 DMA_CCMD_GLOBAL_INVL);
3839 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3840 iommu_enable_translation(iommu);
3841 iommu_disable_protect_mem_regions(iommu);
3847 static void iommu_flush_all(void)
3849 struct dmar_drhd_unit *drhd;
3850 struct intel_iommu *iommu;
3852 for_each_active_iommu(iommu, drhd) {
3853 iommu->flush.flush_context(iommu, 0, 0, 0,
3854 DMA_CCMD_GLOBAL_INVL);
3855 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3856 DMA_TLB_GLOBAL_FLUSH);
3860 static int iommu_suspend(void)
3862 struct dmar_drhd_unit *drhd;
3863 struct intel_iommu *iommu = NULL;
3866 for_each_active_iommu(iommu, drhd) {
3867 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3869 if (!iommu->iommu_state)
3875 for_each_active_iommu(iommu, drhd) {
3876 iommu_disable_translation(iommu);
3878 raw_spin_lock_irqsave(&iommu->register_lock, flag);
3880 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3881 readl(iommu->reg + DMAR_FECTL_REG);
3882 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3883 readl(iommu->reg + DMAR_FEDATA_REG);
3884 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3885 readl(iommu->reg + DMAR_FEADDR_REG);
3886 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3887 readl(iommu->reg + DMAR_FEUADDR_REG);
3889 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3894 for_each_active_iommu(iommu, drhd)
3895 kfree(iommu->iommu_state);
3900 static void iommu_resume(void)
3902 struct dmar_drhd_unit *drhd;
3903 struct intel_iommu *iommu = NULL;
3906 if (init_iommu_hw()) {
3908 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3910 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3914 for_each_active_iommu(iommu, drhd) {
3916 raw_spin_lock_irqsave(&iommu->register_lock, flag);
3918 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3919 iommu->reg + DMAR_FECTL_REG);
3920 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3921 iommu->reg + DMAR_FEDATA_REG);
3922 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3923 iommu->reg + DMAR_FEADDR_REG);
3924 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3925 iommu->reg + DMAR_FEUADDR_REG);
3927 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3930 for_each_active_iommu(iommu, drhd)
3931 kfree(iommu->iommu_state);
3934 static struct syscore_ops iommu_syscore_ops = {
3935 .resume = iommu_resume,
3936 .suspend = iommu_suspend,
3939 static void __init init_iommu_pm_ops(void)
3941 register_syscore_ops(&iommu_syscore_ops);
3945 static inline void init_iommu_pm_ops(void) {}
3946 #endif /* CONFIG_PM */
3949 int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg)
3951 struct acpi_dmar_reserved_memory *rmrr;
3952 struct dmar_rmrr_unit *rmrru;
3954 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3958 rmrru->hdr = header;
3959 rmrr = (struct acpi_dmar_reserved_memory *)header;
3960 rmrru->base_address = rmrr->base_address;
3961 rmrru->end_address = rmrr->end_address;
3962 rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
3963 ((void *)rmrr) + rmrr->header.length,
3964 &rmrru->devices_cnt);
3965 if (rmrru->devices_cnt && rmrru->devices == NULL) {
3970 list_add(&rmrru->list, &dmar_rmrr_units);
3975 static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr)
3977 struct dmar_atsr_unit *atsru;
3978 struct acpi_dmar_atsr *tmp;
3980 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
3981 tmp = (struct acpi_dmar_atsr *)atsru->hdr;
3982 if (atsr->segment != tmp->segment)
3984 if (atsr->header.length != tmp->header.length)
3986 if (memcmp(atsr, tmp, atsr->header.length) == 0)
3993 int dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg)
3995 struct acpi_dmar_atsr *atsr;
3996 struct dmar_atsr_unit *atsru;
3998 if (system_state != SYSTEM_BOOTING && !intel_iommu_enabled)
4001 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
4002 atsru = dmar_find_atsr(atsr);
4006 atsru = kzalloc(sizeof(*atsru) + hdr->length, GFP_KERNEL);
4011 * If memory is allocated from slab by ACPI _DSM method, we need to
4012 * copy the memory content because the memory buffer will be freed
4015 atsru->hdr = (void *)(atsru + 1);
4016 memcpy(atsru->hdr, hdr, hdr->length);
4017 atsru->include_all = atsr->flags & 0x1;
4018 if (!atsru->include_all) {
4019 atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
4020 (void *)atsr + atsr->header.length,
4021 &atsru->devices_cnt);
4022 if (atsru->devices_cnt && atsru->devices == NULL) {
4028 list_add_rcu(&atsru->list, &dmar_atsr_units);
4033 static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
4035 dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
4039 int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg)
4041 struct acpi_dmar_atsr *atsr;
4042 struct dmar_atsr_unit *atsru;
4044 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
4045 atsru = dmar_find_atsr(atsr);
4047 list_del_rcu(&atsru->list);
4049 intel_iommu_free_atsr(atsru);
4055 int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg)
4059 struct acpi_dmar_atsr *atsr;
4060 struct dmar_atsr_unit *atsru;
4062 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
4063 atsru = dmar_find_atsr(atsr);
4067 if (!atsru->include_all && atsru->devices && atsru->devices_cnt)
4068 for_each_active_dev_scope(atsru->devices, atsru->devices_cnt,
4075 static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
4078 struct intel_iommu *iommu = dmaru->iommu;
4080 if (g_iommus[iommu->seq_id])
4083 if (hw_pass_through && !ecap_pass_through(iommu->ecap)) {
4084 pr_warn("%s: Doesn't support hardware pass through.\n",
4088 if (!ecap_sc_support(iommu->ecap) &&
4089 domain_update_iommu_snooping(iommu)) {
4090 pr_warn("%s: Doesn't support snooping.\n",
4094 sp = domain_update_iommu_superpage(iommu) - 1;
4095 if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) {
4096 pr_warn("%s: Doesn't support large page.\n",
4102 * Disable translation if already enabled prior to OS handover.
4104 if (iommu->gcmd & DMA_GCMD_TE)
4105 iommu_disable_translation(iommu);
4107 g_iommus[iommu->seq_id] = iommu;
4108 ret = iommu_init_domains(iommu);
4110 ret = iommu_alloc_root_entry(iommu);
4114 if (dmaru->ignored) {
4116 * we always have to disable PMRs or DMA may fail on this device
4119 iommu_disable_protect_mem_regions(iommu);
4123 intel_iommu_init_qi(iommu);
4124 iommu_flush_write_buffer(iommu);
4125 ret = dmar_set_interrupt(iommu);
4129 iommu_set_root_entry(iommu);
4130 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
4131 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
4132 iommu_enable_translation(iommu);
4134 iommu_disable_protect_mem_regions(iommu);
4138 disable_dmar_iommu(iommu);
4140 free_dmar_iommu(iommu);
4144 int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
4147 struct intel_iommu *iommu = dmaru->iommu;
4149 if (!intel_iommu_enabled)
4155 ret = intel_iommu_add(dmaru);
4157 disable_dmar_iommu(iommu);
4158 free_dmar_iommu(iommu);
4164 static void intel_iommu_free_dmars(void)
4166 struct dmar_rmrr_unit *rmrru, *rmrr_n;
4167 struct dmar_atsr_unit *atsru, *atsr_n;
4169 list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
4170 list_del(&rmrru->list);
4171 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
4175 list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
4176 list_del(&atsru->list);
4177 intel_iommu_free_atsr(atsru);
4181 int dmar_find_matched_atsr_unit(struct pci_dev *dev)
4184 struct pci_bus *bus;
4185 struct pci_dev *bridge = NULL;
4187 struct acpi_dmar_atsr *atsr;
4188 struct dmar_atsr_unit *atsru;
4190 dev = pci_physfn(dev);
4191 for (bus = dev->bus; bus; bus = bus->parent) {
4193 if (!bridge || !pci_is_pcie(bridge) ||
4194 pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
4196 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
4203 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
4204 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
4205 if (atsr->segment != pci_domain_nr(dev->bus))
4208 for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
4209 if (tmp == &bridge->dev)
4212 if (atsru->include_all)
4222 int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
4225 struct dmar_rmrr_unit *rmrru;
4226 struct dmar_atsr_unit *atsru;
4227 struct acpi_dmar_atsr *atsr;
4228 struct acpi_dmar_reserved_memory *rmrr;
4230 if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
4233 list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
4234 rmrr = container_of(rmrru->hdr,
4235 struct acpi_dmar_reserved_memory, header);
4236 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
4237 ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
4238 ((void *)rmrr) + rmrr->header.length,
4239 rmrr->segment, rmrru->devices,
4240 rmrru->devices_cnt);
4243 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
4244 dmar_remove_dev_scope(info, rmrr->segment,
4245 rmrru->devices, rmrru->devices_cnt);
4249 list_for_each_entry(atsru, &dmar_atsr_units, list) {
4250 if (atsru->include_all)
4253 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
4254 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
4255 ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
4256 (void *)atsr + atsr->header.length,
4257 atsr->segment, atsru->devices,
4258 atsru->devices_cnt);
4263 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
4264 if (dmar_remove_dev_scope(info, atsr->segment,
4265 atsru->devices, atsru->devices_cnt))
4274 * Here we only respond to action of unbound device from driver.
4276 * Added device is not attached to its DMAR domain here yet. That will happen
4277 * when mapping the device to iova.
4279 static int device_notifier(struct notifier_block *nb,
4280 unsigned long action, void *data)
4282 struct device *dev = data;
4283 struct dmar_domain *domain;
4285 if (iommu_dummy(dev))
4288 if (action != BUS_NOTIFY_REMOVED_DEVICE)
4291 domain = find_domain(dev);
4295 dmar_remove_one_dev_info(domain, dev);
4296 if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices))
4297 domain_exit(domain);
4302 static struct notifier_block device_nb = {
4303 .notifier_call = device_notifier,
4306 static int intel_iommu_memory_notifier(struct notifier_block *nb,
4307 unsigned long val, void *v)
4309 struct memory_notify *mhp = v;
4310 unsigned long long start, end;
4311 unsigned long start_vpfn, last_vpfn;
4314 case MEM_GOING_ONLINE:
4315 start = mhp->start_pfn << PAGE_SHIFT;
4316 end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
4317 if (iommu_domain_identity_map(si_domain, start, end)) {
4318 pr_warn("Failed to build identity map for [%llx-%llx]\n",
4325 case MEM_CANCEL_ONLINE:
4326 start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
4327 last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
4328 while (start_vpfn <= last_vpfn) {
4330 struct dmar_drhd_unit *drhd;
4331 struct intel_iommu *iommu;
4332 struct page *freelist;
4334 iova = find_iova(&si_domain->iovad, start_vpfn);
4336 pr_debug("Failed get IOVA for PFN %lx\n",
4341 iova = split_and_remove_iova(&si_domain->iovad, iova,
4342 start_vpfn, last_vpfn);
4344 pr_warn("Failed to split IOVA PFN [%lx-%lx]\n",
4345 start_vpfn, last_vpfn);
4349 freelist = domain_unmap(si_domain, iova->pfn_lo,
4353 for_each_active_iommu(iommu, drhd)
4354 iommu_flush_iotlb_psi(iommu, si_domain,
4355 iova->pfn_lo, iova_size(iova),
4358 dma_free_pagelist(freelist);
4360 start_vpfn = iova->pfn_hi + 1;
4361 free_iova_mem(iova);
4369 static struct notifier_block intel_iommu_memory_nb = {
4370 .notifier_call = intel_iommu_memory_notifier,
4375 static ssize_t intel_iommu_show_version(struct device *dev,
4376 struct device_attribute *attr,
4379 struct intel_iommu *iommu = dev_get_drvdata(dev);
4380 u32 ver = readl(iommu->reg + DMAR_VER_REG);
4381 return sprintf(buf, "%d:%d\n",
4382 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver));
4384 static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL);
4386 static ssize_t intel_iommu_show_address(struct device *dev,
4387 struct device_attribute *attr,
4390 struct intel_iommu *iommu = dev_get_drvdata(dev);
4391 return sprintf(buf, "%llx\n", iommu->reg_phys);
4393 static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL);
4395 static ssize_t intel_iommu_show_cap(struct device *dev,
4396 struct device_attribute *attr,
4399 struct intel_iommu *iommu = dev_get_drvdata(dev);
4400 return sprintf(buf, "%llx\n", iommu->cap);
4402 static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL);
4404 static ssize_t intel_iommu_show_ecap(struct device *dev,
4405 struct device_attribute *attr,
4408 struct intel_iommu *iommu = dev_get_drvdata(dev);
4409 return sprintf(buf, "%llx\n", iommu->ecap);
4411 static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL);
4413 static ssize_t intel_iommu_show_ndoms(struct device *dev,
4414 struct device_attribute *attr,
4417 struct intel_iommu *iommu = dev_get_drvdata(dev);
4418 return sprintf(buf, "%ld\n", cap_ndoms(iommu->cap));
4420 static DEVICE_ATTR(domains_supported, S_IRUGO, intel_iommu_show_ndoms, NULL);
4422 static ssize_t intel_iommu_show_ndoms_used(struct device *dev,
4423 struct device_attribute *attr,
4426 struct intel_iommu *iommu = dev_get_drvdata(dev);
4427 return sprintf(buf, "%d\n", bitmap_weight(iommu->domain_ids,
4428 cap_ndoms(iommu->cap)));
4430 static DEVICE_ATTR(domains_used, S_IRUGO, intel_iommu_show_ndoms_used, NULL);
4432 static struct attribute *intel_iommu_attrs[] = {
4433 &dev_attr_version.attr,
4434 &dev_attr_address.attr,
4436 &dev_attr_ecap.attr,
4437 &dev_attr_domains_supported.attr,
4438 &dev_attr_domains_used.attr,
4442 static struct attribute_group intel_iommu_group = {
4443 .name = "intel-iommu",
4444 .attrs = intel_iommu_attrs,
4447 const struct attribute_group *intel_iommu_groups[] = {
4452 int __init intel_iommu_init(void)
4455 struct dmar_drhd_unit *drhd;
4456 struct intel_iommu *iommu;
4458 /* VT-d is required for a TXT/tboot launch, so enforce that */
4459 force_on = tboot_force_iommu();
4461 if (iommu_init_mempool()) {
4463 panic("tboot: Failed to initialize iommu memory\n");
4467 down_write(&dmar_global_lock);
4468 if (dmar_table_init()) {
4470 panic("tboot: Failed to initialize DMAR table\n");
4474 if (dmar_dev_scope_init() < 0) {
4476 panic("tboot: Failed to initialize DMAR device scope\n");
4480 if (no_iommu || dmar_disabled)
4483 if (list_empty(&dmar_rmrr_units))
4484 pr_info("No RMRR found\n");
4486 if (list_empty(&dmar_atsr_units))
4487 pr_info("No ATSR found\n");
4489 if (dmar_init_reserved_ranges()) {
4491 panic("tboot: Failed to reserve iommu ranges\n");
4492 goto out_free_reserved_range;
4495 init_no_remapping_devices();
4500 panic("tboot: Failed to initialize DMARs\n");
4501 pr_err("Initialization failed\n");
4502 goto out_free_reserved_range;
4504 up_write(&dmar_global_lock);
4505 pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
4507 init_timer(&unmap_timer);
4508 #ifdef CONFIG_SWIOTLB
4511 dma_ops = &intel_dma_ops;
4513 init_iommu_pm_ops();
4515 for_each_active_iommu(iommu, drhd)
4516 iommu->iommu_dev = iommu_device_create(NULL, iommu,
4520 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
4521 bus_register_notifier(&pci_bus_type, &device_nb);
4522 if (si_domain && !hw_pass_through)
4523 register_memory_notifier(&intel_iommu_memory_nb);
4525 intel_iommu_enabled = 1;
4529 out_free_reserved_range:
4530 put_iova_domain(&reserved_iova_list);
4532 intel_iommu_free_dmars();
4533 up_write(&dmar_global_lock);
4534 iommu_exit_mempool();
4538 static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *opaque)
4540 struct intel_iommu *iommu = opaque;
4542 domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff);
4547 * NB - intel-iommu lacks any sort of reference counting for the users of
4548 * dependent devices. If multiple endpoints have intersecting dependent
4549 * devices, unbinding the driver from any one of them will possibly leave
4550 * the others unable to operate.
4552 static void domain_context_clear(struct intel_iommu *iommu, struct device *dev)
4554 if (!iommu || !dev || !dev_is_pci(dev))
4557 pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu);
4560 static void __dmar_remove_one_dev_info(struct device_domain_info *info)
4562 struct intel_iommu *iommu;
4563 unsigned long flags;
4565 assert_spin_locked(&device_domain_lock);
4570 iommu = info->iommu;
4573 iommu_disable_dev_iotlb(info);
4574 domain_context_clear(iommu, info->dev);
4577 unlink_domain_info(info);
4579 spin_lock_irqsave(&iommu->lock, flags);
4580 domain_detach_iommu(info->domain, iommu);
4581 spin_unlock_irqrestore(&iommu->lock, flags);
4583 free_devinfo_mem(info);
4586 static void dmar_remove_one_dev_info(struct dmar_domain *domain,
4589 struct device_domain_info *info;
4590 unsigned long flags;
4592 spin_lock_irqsave(&device_domain_lock, flags);
4593 info = dev->archdata.iommu;
4594 __dmar_remove_one_dev_info(info);
4595 spin_unlock_irqrestore(&device_domain_lock, flags);
4598 static int md_domain_init(struct dmar_domain *domain, int guest_width)
4602 init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
4604 domain_reserve_special_ranges(domain);
4606 /* calculate AGAW */
4607 domain->gaw = guest_width;
4608 adjust_width = guestwidth_to_adjustwidth(guest_width);
4609 domain->agaw = width_to_agaw(adjust_width);
4611 domain->iommu_coherency = 0;
4612 domain->iommu_snooping = 0;
4613 domain->iommu_superpage = 0;
4614 domain->max_addr = 0;
4616 /* always allocate the top pgd */
4617 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
4620 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
4624 static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
4626 struct dmar_domain *dmar_domain;
4627 struct iommu_domain *domain;
4629 if (type != IOMMU_DOMAIN_UNMANAGED)
4632 dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE);
4634 pr_err("Can't allocate dmar_domain\n");
4637 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
4638 pr_err("Domain initialization failed\n");
4639 domain_exit(dmar_domain);
4642 domain_update_iommu_cap(dmar_domain);
4644 domain = &dmar_domain->domain;
4645 domain->geometry.aperture_start = 0;
4646 domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
4647 domain->geometry.force_aperture = true;
4652 static void intel_iommu_domain_free(struct iommu_domain *domain)
4654 domain_exit(to_dmar_domain(domain));
4657 static int intel_iommu_attach_device(struct iommu_domain *domain,
4660 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4661 struct intel_iommu *iommu;
4665 if (device_is_rmrr_locked(dev)) {
4666 dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement. Contact your platform vendor.\n");
4670 /* normally dev is not mapped */
4671 if (unlikely(domain_context_mapped(dev))) {
4672 struct dmar_domain *old_domain;
4674 old_domain = find_domain(dev);
4677 dmar_remove_one_dev_info(old_domain, dev);
4680 if (!domain_type_is_vm_or_si(old_domain) &&
4681 list_empty(&old_domain->devices))
4682 domain_exit(old_domain);
4686 iommu = device_to_iommu(dev, &bus, &devfn);
4690 /* check if this iommu agaw is sufficient for max mapped address */
4691 addr_width = agaw_to_width(iommu->agaw);
4692 if (addr_width > cap_mgaw(iommu->cap))
4693 addr_width = cap_mgaw(iommu->cap);
4695 if (dmar_domain->max_addr > (1LL << addr_width)) {
4696 pr_err("%s: iommu width (%d) is not "
4697 "sufficient for the mapped address (%llx)\n",
4698 __func__, addr_width, dmar_domain->max_addr);
4701 dmar_domain->gaw = addr_width;
4704 * Knock out extra levels of page tables if necessary
4706 while (iommu->agaw < dmar_domain->agaw) {
4707 struct dma_pte *pte;
4709 pte = dmar_domain->pgd;
4710 if (dma_pte_present(pte)) {
4711 dmar_domain->pgd = (struct dma_pte *)
4712 phys_to_virt(dma_pte_addr(pte));
4713 free_pgtable_page(pte);
4715 dmar_domain->agaw--;
4718 return domain_add_dev_info(dmar_domain, dev);
4721 static void intel_iommu_detach_device(struct iommu_domain *domain,
4724 dmar_remove_one_dev_info(to_dmar_domain(domain), dev);
4727 static int intel_iommu_map(struct iommu_domain *domain,
4728 unsigned long iova, phys_addr_t hpa,
4729 size_t size, int iommu_prot)
4731 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4736 if (iommu_prot & IOMMU_READ)
4737 prot |= DMA_PTE_READ;
4738 if (iommu_prot & IOMMU_WRITE)
4739 prot |= DMA_PTE_WRITE;
4740 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4741 prot |= DMA_PTE_SNP;
4743 max_addr = iova + size;
4744 if (dmar_domain->max_addr < max_addr) {
4747 /* check if minimum agaw is sufficient for mapped address */
4748 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
4749 if (end < max_addr) {
4750 pr_err("%s: iommu width (%d) is not "
4751 "sufficient for the mapped address (%llx)\n",
4752 __func__, dmar_domain->gaw, max_addr);
4755 dmar_domain->max_addr = max_addr;
4757 /* Round up size to next multiple of PAGE_SIZE, if it and
4758 the low bits of hpa would take us onto the next page */
4759 size = aligned_nrpages(hpa, size);
4760 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4761 hpa >> VTD_PAGE_SHIFT, size, prot);
4765 static size_t intel_iommu_unmap(struct iommu_domain *domain,
4766 unsigned long iova, size_t size)
4768 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4769 struct page *freelist = NULL;
4770 struct intel_iommu *iommu;
4771 unsigned long start_pfn, last_pfn;
4772 unsigned int npages;
4773 int iommu_id, level = 0;
4775 /* Cope with horrid API which requires us to unmap more than the
4776 size argument if it happens to be a large-page mapping. */
4777 BUG_ON(!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level));
4779 if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
4780 size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4782 start_pfn = iova >> VTD_PAGE_SHIFT;
4783 last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
4785 freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
4787 npages = last_pfn - start_pfn + 1;
4789 for_each_domain_iommu(iommu_id, dmar_domain) {
4790 iommu = g_iommus[iommu_id];
4792 iommu_flush_iotlb_psi(g_iommus[iommu_id], dmar_domain,
4793 start_pfn, npages, !freelist, 0);
4796 dma_free_pagelist(freelist);
4798 if (dmar_domain->max_addr == iova + size)
4799 dmar_domain->max_addr = iova;
4804 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
4807 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4808 struct dma_pte *pte;
4812 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
4814 phys = dma_pte_addr(pte);
4819 static bool intel_iommu_capable(enum iommu_cap cap)
4821 if (cap == IOMMU_CAP_CACHE_COHERENCY)
4822 return domain_update_iommu_snooping(NULL) == 1;
4823 if (cap == IOMMU_CAP_INTR_REMAP)
4824 return irq_remapping_enabled == 1;
4829 static int intel_iommu_add_device(struct device *dev)
4831 struct intel_iommu *iommu;
4832 struct iommu_group *group;
4835 iommu = device_to_iommu(dev, &bus, &devfn);
4839 iommu_device_link(iommu->iommu_dev, dev);
4841 group = iommu_group_get_for_dev(dev);
4844 return PTR_ERR(group);
4846 iommu_group_put(group);
4850 static void intel_iommu_remove_device(struct device *dev)
4852 struct intel_iommu *iommu;
4855 iommu = device_to_iommu(dev, &bus, &devfn);
4859 iommu_group_remove_device(dev);
4861 iommu_device_unlink(iommu->iommu_dev, dev);
4864 static const struct iommu_ops intel_iommu_ops = {
4865 .capable = intel_iommu_capable,
4866 .domain_alloc = intel_iommu_domain_alloc,
4867 .domain_free = intel_iommu_domain_free,
4868 .attach_dev = intel_iommu_attach_device,
4869 .detach_dev = intel_iommu_detach_device,
4870 .map = intel_iommu_map,
4871 .unmap = intel_iommu_unmap,
4872 .map_sg = default_iommu_map_sg,
4873 .iova_to_phys = intel_iommu_iova_to_phys,
4874 .add_device = intel_iommu_add_device,
4875 .remove_device = intel_iommu_remove_device,
4876 .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
4879 static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4881 /* G4x/GM45 integrated gfx dmar support is totally busted. */
4882 pr_info("Disabling IOMMU for graphics on this chipset\n");
4886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4894 static void quirk_iommu_rwbf(struct pci_dev *dev)
4897 * Mobile 4 Series Chipset neglects to set RWBF capability,
4898 * but needs it. Same seems to hold for the desktop versions.
4900 pr_info("Forcing write-buffer flush capability\n");
4904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
4905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
4913 #define GGC_MEMORY_SIZE_MASK (0xf << 8)
4914 #define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4915 #define GGC_MEMORY_SIZE_1M (0x1 << 8)
4916 #define GGC_MEMORY_SIZE_2M (0x3 << 8)
4917 #define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4918 #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4919 #define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4920 #define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4922 static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
4926 if (pci_read_config_word(dev, GGC, &ggc))
4929 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
4930 pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4932 } else if (dmar_map_gfx) {
4933 /* we have to ensure the gfx device is idle before we flush */
4934 pr_info("Disabling batched IOTLB flush on Ironlake\n");
4935 intel_iommu_strict = 1;
4938 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4940 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4941 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4943 /* On Tylersburg chipsets, some BIOSes have been known to enable the
4944 ISOCH DMAR unit for the Azalia sound device, but not give it any
4945 TLB entries, which causes it to deadlock. Check for that. We do
4946 this in a function called from init_dmars(), instead of in a PCI
4947 quirk, because we don't want to print the obnoxious "BIOS broken"
4948 message if VT-d is actually disabled.
4950 static void __init check_tylersburg_isoch(void)
4952 struct pci_dev *pdev;
4953 uint32_t vtisochctrl;
4955 /* If there's no Azalia in the system anyway, forget it. */
4956 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4961 /* System Management Registers. Might be hidden, in which case
4962 we can't do the sanity check. But that's OK, because the
4963 known-broken BIOSes _don't_ actually hide it, so far. */
4964 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4968 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4975 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4976 if (vtisochctrl & 1)
4979 /* Drop all bits other than the number of TLB entries */
4980 vtisochctrl &= 0x1c;
4982 /* If we have the recommended number of TLB entries (16), fine. */
4983 if (vtisochctrl == 0x10)
4986 /* Zero TLB entries? You get to ride the short bus to school. */
4988 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4989 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4990 dmi_get_system_info(DMI_BIOS_VENDOR),
4991 dmi_get_system_info(DMI_BIOS_VERSION),
4992 dmi_get_system_info(DMI_PRODUCT_VERSION));
4993 iommu_identity_mapping |= IDENTMAP_AZALIA;
4997 pr_warn("Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",