1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/slab.h>
5 #include <linux/jiffies.h>
6 #include <linux/hpet.h>
9 #include <linux/intel-iommu.h>
10 #include <linux/acpi.h>
11 #include <linux/irqdomain.h>
12 #include <asm/io_apic.h>
15 #include <asm/irq_remapping.h>
16 #include <asm/pci-direct.h>
17 #include <asm/msidef.h>
19 #include "irq_remapping.h"
22 struct intel_iommu *iommu;
24 unsigned int bus; /* PCI bus number */
25 unsigned int devfn; /* PCI devfn number */
29 struct intel_iommu *iommu;
36 struct intel_iommu *iommu;
42 struct intel_ir_data {
43 struct irq_2_iommu irq_2_iommu;
44 struct irte irte_entry;
46 struct msi_msg msi_entry;
50 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
51 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
53 static int __read_mostly eim_mode;
54 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
55 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
62 * ->iommu->register_lock
64 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
65 * in single-threaded environment with interrupt disabled, so no need to tabke
66 * the dmar_global_lock.
68 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
69 static struct irq_domain_ops intel_ir_domain_ops;
71 static int __init parse_ioapics_under_ir(void);
73 static int alloc_irte(struct intel_iommu *iommu, int irq,
74 struct irq_2_iommu *irq_iommu, u16 count)
76 struct ir_table *table = iommu->ir_table;
77 unsigned int mask = 0;
81 if (!count || !irq_iommu)
85 count = __roundup_pow_of_two(count);
89 if (mask > ecap_max_handle_mask(iommu->ecap)) {
91 "Requested mask %x exceeds the max invalidation handle"
92 " mask value %Lx\n", mask,
93 ecap_max_handle_mask(iommu->ecap));
97 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
98 index = bitmap_find_free_region(table->bitmap,
99 INTR_REMAP_TABLE_ENTRIES, mask);
101 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
103 irq_iommu->iommu = iommu;
104 irq_iommu->irte_index = index;
105 irq_iommu->sub_handle = 0;
106 irq_iommu->irte_mask = mask;
108 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
113 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
117 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
121 return qi_submit_sync(&desc, iommu);
124 static int modify_irte(struct irq_2_iommu *irq_iommu,
125 struct irte *irte_modified)
127 struct intel_iommu *iommu;
135 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
137 iommu = irq_iommu->iommu;
139 index = irq_iommu->irte_index + irq_iommu->sub_handle;
140 irte = &iommu->ir_table->base[index];
142 set_64bit(&irte->low, irte_modified->low);
143 set_64bit(&irte->high, irte_modified->high);
144 __iommu_flush_cache(iommu, irte, sizeof(*irte));
146 rc = qi_flush_iec(iommu, index, 0);
147 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
152 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
156 for (i = 0; i < MAX_HPET_TBS; i++)
157 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
158 return ir_hpet[i].iommu;
162 static struct intel_iommu *map_ioapic_to_ir(int apic)
166 for (i = 0; i < MAX_IO_APICS; i++)
167 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
168 return ir_ioapic[i].iommu;
172 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
174 struct dmar_drhd_unit *drhd;
176 drhd = dmar_find_matched_drhd_unit(dev);
183 static int clear_entries(struct irq_2_iommu *irq_iommu)
185 struct irte *start, *entry, *end;
186 struct intel_iommu *iommu;
189 if (irq_iommu->sub_handle)
192 iommu = irq_iommu->iommu;
193 index = irq_iommu->irte_index;
195 start = iommu->ir_table->base + index;
196 end = start + (1 << irq_iommu->irte_mask);
198 for (entry = start; entry < end; entry++) {
199 set_64bit(&entry->low, 0);
200 set_64bit(&entry->high, 0);
202 bitmap_release_region(iommu->ir_table->bitmap, index,
203 irq_iommu->irte_mask);
205 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
209 * source validation type
211 #define SVT_NO_VERIFY 0x0 /* no verification is required */
212 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
213 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
216 * source-id qualifier
218 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
219 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
220 * the third least significant bit
222 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
223 * the second and third least significant bits
225 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
226 * the least three significant bits
230 * set SVT, SQ and SID fields of irte to verify
231 * source ids of interrupt requests
233 static void set_irte_sid(struct irte *irte, unsigned int svt,
234 unsigned int sq, unsigned int sid)
236 if (disable_sourceid_checking)
243 static int set_ioapic_sid(struct irte *irte, int apic)
251 down_read(&dmar_global_lock);
252 for (i = 0; i < MAX_IO_APICS; i++) {
253 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
254 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
258 up_read(&dmar_global_lock);
261 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
265 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
270 static int set_hpet_sid(struct irte *irte, u8 id)
278 down_read(&dmar_global_lock);
279 for (i = 0; i < MAX_HPET_TBS; i++) {
280 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
281 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
285 up_read(&dmar_global_lock);
288 pr_warning("Failed to set source-id of HPET block (%d)\n", id);
293 * Should really use SQ_ALL_16. Some platforms are broken.
294 * While we figure out the right quirks for these broken platforms, use
295 * SQ_13_IGNORE_3 for now.
297 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
302 struct set_msi_sid_data {
303 struct pci_dev *pdev;
307 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
309 struct set_msi_sid_data *data = opaque;
317 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
319 struct set_msi_sid_data data;
324 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
327 * DMA alias provides us with a PCI device and alias. The only case
328 * where the it will return an alias on a different bus than the
329 * device is the case of a PCIe-to-PCI bridge, where the alias is for
330 * the subordinate bus. In this case we can only verify the bus.
332 * If the alias device is on a different bus than our source device
333 * then we have a topology based alias, use it.
335 * Otherwise, the alias is for a device DMA quirk and we cannot
336 * assume that MSI uses the same requester ID. Therefore use the
339 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
340 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
341 PCI_DEVID(PCI_BUS_NUM(data.alias),
343 else if (data.pdev->bus->number != dev->bus->number)
344 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
346 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
347 PCI_DEVID(dev->bus->number, dev->devfn));
352 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
358 addr = virt_to_phys((void *)iommu->ir_table->base);
360 raw_spin_lock_irqsave(&iommu->register_lock, flags);
362 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
363 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
365 /* Set interrupt-remapping table pointer */
366 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
368 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
369 readl, (sts & DMA_GSTS_IRTPS), sts);
370 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
373 * global invalidation of interrupt entry cache before enabling
374 * interrupt-remapping.
376 qi_global_iec(iommu);
378 raw_spin_lock_irqsave(&iommu->register_lock, flags);
380 /* Enable interrupt-remapping */
381 iommu->gcmd |= DMA_GCMD_IRE;
382 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
383 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
385 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
386 readl, (sts & DMA_GSTS_IRES), sts);
389 * With CFI clear in the Global Command register, we should be
390 * protected from dangerous (i.e. compatibility) interrupts
391 * regardless of x2apic status. Check just to be sure.
393 if (sts & DMA_GSTS_CFIS)
395 "Compatibility-format IRQs enabled despite intr remapping;\n"
396 "you are vulnerable to IRQ injection.\n");
398 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
401 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
403 struct ir_table *ir_table;
405 unsigned long *bitmap;
410 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
414 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
415 INTR_REMAP_PAGE_ORDER);
417 pr_err("IR%d: failed to allocate pages of order %d\n",
418 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
422 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
423 sizeof(long), GFP_ATOMIC);
424 if (bitmap == NULL) {
425 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
429 iommu->ir_domain = irq_domain_add_hierarchy(arch_get_ir_parent_domain(),
430 0, INTR_REMAP_TABLE_ENTRIES,
431 NULL, &intel_ir_domain_ops,
433 if (!iommu->ir_domain) {
434 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
435 goto out_free_bitmap;
437 iommu->ir_msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
439 ir_table->base = page_address(pages);
440 ir_table->bitmap = bitmap;
441 iommu->ir_table = ir_table;
447 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
453 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
455 if (iommu && iommu->ir_table) {
456 if (iommu->ir_msi_domain) {
457 irq_domain_remove(iommu->ir_msi_domain);
458 iommu->ir_msi_domain = NULL;
460 if (iommu->ir_domain) {
461 irq_domain_remove(iommu->ir_domain);
462 iommu->ir_domain = NULL;
464 free_pages((unsigned long)iommu->ir_table->base,
465 INTR_REMAP_PAGE_ORDER);
466 kfree(iommu->ir_table->bitmap);
467 kfree(iommu->ir_table);
468 iommu->ir_table = NULL;
473 * Disable Interrupt Remapping.
475 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
480 if (!ecap_ir_support(iommu->ecap))
484 * global invalidation of interrupt entry cache before disabling
485 * interrupt-remapping.
487 qi_global_iec(iommu);
489 raw_spin_lock_irqsave(&iommu->register_lock, flags);
491 sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
492 if (!(sts & DMA_GSTS_IRES))
495 iommu->gcmd &= ~DMA_GCMD_IRE;
496 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
498 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
499 readl, !(sts & DMA_GSTS_IRES), sts);
502 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
505 static int __init dmar_x2apic_optout(void)
507 struct acpi_table_dmar *dmar;
508 dmar = (struct acpi_table_dmar *)dmar_tbl;
509 if (!dmar || no_x2apic_optout)
511 return dmar->flags & DMAR_X2APIC_OPT_OUT;
514 static void __init intel_cleanup_irq_remapping(void)
516 struct dmar_drhd_unit *drhd;
517 struct intel_iommu *iommu;
519 for_each_iommu(iommu, drhd) {
520 if (ecap_ir_support(iommu->ecap)) {
521 iommu_disable_irq_remapping(iommu);
522 intel_teardown_irq_remapping(iommu);
526 if (x2apic_supported())
527 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
530 static int __init intel_prepare_irq_remapping(void)
532 struct dmar_drhd_unit *drhd;
533 struct intel_iommu *iommu;
535 if (irq_remap_broken) {
537 "This system BIOS has enabled interrupt remapping\n"
538 "on a chipset that contains an erratum making that\n"
539 "feature unstable. To maintain system stability\n"
540 "interrupt remapping is being disabled. Please\n"
541 "contact your BIOS vendor for an update\n");
542 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
546 if (dmar_table_init() < 0)
549 if (!dmar_ir_support())
552 if (parse_ioapics_under_ir() != 1) {
553 printk(KERN_INFO "Not enabling interrupt remapping\n");
557 /* First make sure all IOMMUs support IRQ remapping */
558 for_each_iommu(iommu, drhd)
559 if (!ecap_ir_support(iommu->ecap))
562 /* Do the allocations early */
563 for_each_iommu(iommu, drhd)
564 if (intel_setup_irq_remapping(iommu))
570 intel_cleanup_irq_remapping();
574 static int __init intel_enable_irq_remapping(void)
576 struct dmar_drhd_unit *drhd;
577 struct intel_iommu *iommu;
581 if (x2apic_supported()) {
582 eim = !dmar_x2apic_optout();
584 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit. You can use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
587 for_each_iommu(iommu, drhd) {
589 * If the queued invalidation is already initialized,
590 * shouldn't disable it.
596 * Clear previous faults.
598 dmar_fault(-1, iommu);
601 * Disable intr remapping and queued invalidation, if already
602 * enabled prior to OS handover.
604 iommu_disable_irq_remapping(iommu);
606 dmar_disable_qi(iommu);
610 * check for the Interrupt-remapping support
612 for_each_iommu(iommu, drhd)
613 if (eim && !ecap_eim_support(iommu->ecap)) {
614 printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
615 " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
620 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
623 * Enable queued invalidation for all the DRHD's.
625 for_each_iommu(iommu, drhd) {
626 int ret = dmar_enable_qi(iommu);
629 printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
630 " invalidation, ecap %Lx, ret %d\n",
631 drhd->reg_base_addr, iommu->ecap, ret);
637 * Setup Interrupt-remapping for all the DRHD's now.
639 for_each_iommu(iommu, drhd) {
640 iommu_set_irq_remapping(iommu, eim);
647 irq_remapping_enabled = 1;
649 pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic");
651 return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
654 intel_cleanup_irq_remapping();
658 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
659 struct intel_iommu *iommu,
660 struct acpi_dmar_hardware_unit *drhd)
662 struct acpi_dmar_pci_path *path;
664 int count, free = -1;
667 path = (struct acpi_dmar_pci_path *)(scope + 1);
668 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
669 / sizeof(struct acpi_dmar_pci_path);
671 while (--count > 0) {
673 * Access PCI directly due to the PCI
674 * subsystem isn't initialized yet.
676 bus = read_pci_config_byte(bus, path->device, path->function,
681 for (count = 0; count < MAX_HPET_TBS; count++) {
682 if (ir_hpet[count].iommu == iommu &&
683 ir_hpet[count].id == scope->enumeration_id)
685 else if (ir_hpet[count].iommu == NULL && free == -1)
689 pr_warn("Exceeded Max HPET blocks\n");
693 ir_hpet[free].iommu = iommu;
694 ir_hpet[free].id = scope->enumeration_id;
695 ir_hpet[free].bus = bus;
696 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
697 pr_info("HPET id %d under DRHD base 0x%Lx\n",
698 scope->enumeration_id, drhd->address);
703 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
704 struct intel_iommu *iommu,
705 struct acpi_dmar_hardware_unit *drhd)
707 struct acpi_dmar_pci_path *path;
709 int count, free = -1;
712 path = (struct acpi_dmar_pci_path *)(scope + 1);
713 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
714 / sizeof(struct acpi_dmar_pci_path);
716 while (--count > 0) {
718 * Access PCI directly due to the PCI
719 * subsystem isn't initialized yet.
721 bus = read_pci_config_byte(bus, path->device, path->function,
726 for (count = 0; count < MAX_IO_APICS; count++) {
727 if (ir_ioapic[count].iommu == iommu &&
728 ir_ioapic[count].id == scope->enumeration_id)
730 else if (ir_ioapic[count].iommu == NULL && free == -1)
734 pr_warn("Exceeded Max IO APICS\n");
738 ir_ioapic[free].bus = bus;
739 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
740 ir_ioapic[free].iommu = iommu;
741 ir_ioapic[free].id = scope->enumeration_id;
742 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
743 scope->enumeration_id, drhd->address, iommu->seq_id);
748 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
749 struct intel_iommu *iommu)
752 struct acpi_dmar_hardware_unit *drhd;
753 struct acpi_dmar_device_scope *scope;
756 drhd = (struct acpi_dmar_hardware_unit *)header;
757 start = (void *)(drhd + 1);
758 end = ((void *)drhd) + header->length;
760 while (start < end && ret == 0) {
762 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
763 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
764 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
765 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
766 start += scope->length;
772 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
776 for (i = 0; i < MAX_HPET_TBS; i++)
777 if (ir_hpet[i].iommu == iommu)
778 ir_hpet[i].iommu = NULL;
780 for (i = 0; i < MAX_IO_APICS; i++)
781 if (ir_ioapic[i].iommu == iommu)
782 ir_ioapic[i].iommu = NULL;
786 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
789 static int __init parse_ioapics_under_ir(void)
791 struct dmar_drhd_unit *drhd;
792 struct intel_iommu *iommu;
793 bool ir_supported = false;
796 for_each_iommu(iommu, drhd)
797 if (ecap_ir_support(iommu->ecap)) {
798 if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
807 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
808 int ioapic_id = mpc_ioapic_id(ioapic_idx);
809 if (!map_ioapic_to_ir(ioapic_id)) {
810 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
811 "interrupt remapping will be disabled\n",
820 static int __init ir_dev_scope_init(void)
824 if (!irq_remapping_enabled)
827 down_write(&dmar_global_lock);
828 ret = dmar_dev_scope_init();
829 up_write(&dmar_global_lock);
833 rootfs_initcall(ir_dev_scope_init);
835 static void disable_irq_remapping(void)
837 struct dmar_drhd_unit *drhd;
838 struct intel_iommu *iommu = NULL;
841 * Disable Interrupt-remapping for all the DRHD's now.
843 for_each_iommu(iommu, drhd) {
844 if (!ecap_ir_support(iommu->ecap))
847 iommu_disable_irq_remapping(iommu);
851 static int reenable_irq_remapping(int eim)
853 struct dmar_drhd_unit *drhd;
855 struct intel_iommu *iommu = NULL;
857 for_each_iommu(iommu, drhd)
859 dmar_reenable_qi(iommu);
862 * Setup Interrupt-remapping for all the DRHD's now.
864 for_each_iommu(iommu, drhd) {
865 if (!ecap_ir_support(iommu->ecap))
868 /* Set up interrupt remapping for iommu.*/
869 iommu_set_irq_remapping(iommu, eim);
880 * handle error condition gracefully here!
885 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
887 memset(irte, 0, sizeof(*irte));
890 irte->dst_mode = apic->irq_dest_mode;
892 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
893 * actual level or edge trigger will be setup in the IO-APIC
894 * RTE. This will help simplify level triggered irq migration.
895 * For more details, see the comments (in io_apic.c) explainig IO-APIC
896 * irq migration in the presence of interrupt-remapping.
898 irte->trigger_mode = 0;
899 irte->dlvry_mode = apic->irq_delivery_mode;
900 irte->vector = vector;
901 irte->dest_id = IRTE_DEST(dest);
902 irte->redir_hint = 1;
905 static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
907 struct intel_iommu *iommu = NULL;
912 switch (info->type) {
913 case X86_IRQ_ALLOC_TYPE_IOAPIC:
914 iommu = map_ioapic_to_ir(info->ioapic_id);
916 case X86_IRQ_ALLOC_TYPE_HPET:
917 iommu = map_hpet_to_ir(info->hpet_id);
919 case X86_IRQ_ALLOC_TYPE_MSI:
920 case X86_IRQ_ALLOC_TYPE_MSIX:
921 iommu = map_dev_to_ir(info->msi_dev);
928 return iommu ? iommu->ir_domain : NULL;
931 static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
933 struct intel_iommu *iommu;
938 switch (info->type) {
939 case X86_IRQ_ALLOC_TYPE_MSI:
940 case X86_IRQ_ALLOC_TYPE_MSIX:
941 iommu = map_dev_to_ir(info->msi_dev);
943 return iommu->ir_msi_domain;
952 struct irq_remap_ops intel_irq_remap_ops = {
953 .prepare = intel_prepare_irq_remapping,
954 .enable = intel_enable_irq_remapping,
955 .disable = disable_irq_remapping,
956 .reenable = reenable_irq_remapping,
957 .enable_faulting = enable_drhd_fault_handling,
958 .get_ir_irq_domain = intel_get_ir_irq_domain,
959 .get_irq_domain = intel_get_irq_domain,
963 * Migrate the IO-APIC irq in the presence of intr-remapping.
965 * For both level and edge triggered, irq migration is a simple atomic
966 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
968 * For level triggered, we eliminate the io-apic RTE modification (with the
969 * updated vector information), by using a virtual vector (io-apic pin number).
970 * Real vector that is used for interrupting cpu will be coming from
971 * the interrupt-remapping table entry.
973 * As the migration is a simple atomic update of IRTE, the same mechanism
974 * is used to migrate MSI irq's in the presence of interrupt-remapping.
977 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
980 struct intel_ir_data *ir_data = data->chip_data;
981 struct irte *irte = &ir_data->irte_entry;
982 struct irq_cfg *cfg = irqd_cfg(data);
983 struct irq_data *parent = data->parent_data;
986 ret = parent->chip->irq_set_affinity(parent, mask, force);
987 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
991 * Atomically updates the IRTE with the new destination, vector
992 * and flushes the interrupt entry cache.
994 irte->vector = cfg->vector;
995 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
996 modify_irte(&ir_data->irq_2_iommu, irte);
999 * After this point, all the interrupts will start arriving
1000 * at the new destination. So, time to cleanup the previous
1001 * vector allocation.
1003 send_cleanup_vector(cfg);
1005 return IRQ_SET_MASK_OK_DONE;
1008 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1009 struct msi_msg *msg)
1011 struct intel_ir_data *ir_data = irq_data->chip_data;
1013 *msg = ir_data->msi_entry;
1016 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1018 struct intel_ir_data *ir_data = data->chip_data;
1019 struct vcpu_data *vcpu_pi_info = info;
1021 /* stop posting interrupts, back to remapping mode */
1022 if (!vcpu_pi_info) {
1023 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1025 struct irte irte_pi;
1028 * We are not caching the posted interrupt entry. We
1029 * copy the data from the remapped entry and modify
1030 * the fields which are relevant for posted mode. The
1031 * cached remapped entry is used for switching back to
1034 memset(&irte_pi, 0, sizeof(irte_pi));
1035 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1037 /* Update the posted mode fields */
1039 irte_pi.p_urgent = 0;
1040 irte_pi.p_vector = vcpu_pi_info->vector;
1041 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1042 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1043 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1044 ~(-1UL << PDA_HIGH_BIT);
1046 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1052 static struct irq_chip intel_ir_chip = {
1053 .irq_ack = ir_ack_apic_edge,
1054 .irq_set_affinity = intel_ir_set_affinity,
1055 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1056 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1059 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1060 struct irq_cfg *irq_cfg,
1061 struct irq_alloc_info *info,
1062 int index, int sub_handle)
1064 struct IR_IO_APIC_route_entry *entry;
1065 struct irte *irte = &data->irte_entry;
1066 struct msi_msg *msg = &data->msi_entry;
1068 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1069 switch (info->type) {
1070 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1071 /* Set source-id of interrupt request */
1072 set_ioapic_sid(irte, info->ioapic_id);
1073 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1074 info->ioapic_id, irte->present, irte->fpd,
1075 irte->dst_mode, irte->redir_hint,
1076 irte->trigger_mode, irte->dlvry_mode,
1077 irte->avail, irte->vector, irte->dest_id,
1078 irte->sid, irte->sq, irte->svt);
1080 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1081 info->ioapic_entry = NULL;
1082 memset(entry, 0, sizeof(*entry));
1083 entry->index2 = (index >> 15) & 0x1;
1086 entry->index = (index & 0x7fff);
1088 * IO-APIC RTE will be configured with virtual vector.
1089 * irq handler will do the explicit EOI to the io-apic.
1091 entry->vector = info->ioapic_pin;
1092 entry->mask = 0; /* enable IRQ */
1093 entry->trigger = info->ioapic_trigger;
1094 entry->polarity = info->ioapic_polarity;
1095 if (info->ioapic_trigger)
1096 entry->mask = 1; /* Mask level triggered irqs. */
1099 case X86_IRQ_ALLOC_TYPE_HPET:
1100 case X86_IRQ_ALLOC_TYPE_MSI:
1101 case X86_IRQ_ALLOC_TYPE_MSIX:
1102 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1103 set_hpet_sid(irte, info->hpet_id);
1105 set_msi_sid(irte, info->msi_dev);
1107 msg->address_hi = MSI_ADDR_BASE_HI;
1108 msg->data = sub_handle;
1109 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1111 MSI_ADDR_IR_INDEX1(index) |
1112 MSI_ADDR_IR_INDEX2(index);
1121 static void intel_free_irq_resources(struct irq_domain *domain,
1122 unsigned int virq, unsigned int nr_irqs)
1124 struct irq_data *irq_data;
1125 struct intel_ir_data *data;
1126 struct irq_2_iommu *irq_iommu;
1127 unsigned long flags;
1130 for (i = 0; i < nr_irqs; i++) {
1131 irq_data = irq_domain_get_irq_data(domain, virq + i);
1132 if (irq_data && irq_data->chip_data) {
1133 data = irq_data->chip_data;
1134 irq_iommu = &data->irq_2_iommu;
1135 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1136 clear_entries(irq_iommu);
1137 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1138 irq_domain_reset_irq_data(irq_data);
1144 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1145 unsigned int virq, unsigned int nr_irqs,
1148 struct intel_iommu *iommu = domain->host_data;
1149 struct irq_alloc_info *info = arg;
1150 struct intel_ir_data *data, *ird;
1151 struct irq_data *irq_data;
1152 struct irq_cfg *irq_cfg;
1155 if (!info || !iommu)
1157 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1158 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1162 * With IRQ remapping enabled, don't need contiguous CPU vectors
1163 * to support multiple MSI interrupts.
1165 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1166 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1168 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1173 data = kzalloc(sizeof(*data), GFP_KERNEL);
1175 goto out_free_parent;
1177 down_read(&dmar_global_lock);
1178 index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
1179 up_read(&dmar_global_lock);
1181 pr_warn("Failed to allocate IRTE\n");
1183 goto out_free_parent;
1186 for (i = 0; i < nr_irqs; i++) {
1187 irq_data = irq_domain_get_irq_data(domain, virq + i);
1188 irq_cfg = irqd_cfg(irq_data);
1189 if (!irq_data || !irq_cfg) {
1195 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1198 /* Initialize the common data */
1199 ird->irq_2_iommu = data->irq_2_iommu;
1200 ird->irq_2_iommu.sub_handle = i;
1205 irq_data->hwirq = (index << 16) + i;
1206 irq_data->chip_data = ird;
1207 irq_data->chip = &intel_ir_chip;
1208 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1209 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1214 intel_free_irq_resources(domain, virq, i);
1216 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1220 static void intel_irq_remapping_free(struct irq_domain *domain,
1221 unsigned int virq, unsigned int nr_irqs)
1223 intel_free_irq_resources(domain, virq, nr_irqs);
1224 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1227 static void intel_irq_remapping_activate(struct irq_domain *domain,
1228 struct irq_data *irq_data)
1230 struct intel_ir_data *data = irq_data->chip_data;
1232 modify_irte(&data->irq_2_iommu, &data->irte_entry);
1235 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1236 struct irq_data *irq_data)
1238 struct intel_ir_data *data = irq_data->chip_data;
1241 memset(&entry, 0, sizeof(entry));
1242 modify_irte(&data->irq_2_iommu, &entry);
1245 static struct irq_domain_ops intel_ir_domain_ops = {
1246 .alloc = intel_irq_remapping_alloc,
1247 .free = intel_irq_remapping_free,
1248 .activate = intel_irq_remapping_activate,
1249 .deactivate = intel_irq_remapping_deactivate,
1253 * Support of Interrupt Remapping Unit Hotplug
1255 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1258 int eim = x2apic_enabled();
1260 if (eim && !ecap_eim_support(iommu->ecap)) {
1261 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1262 iommu->reg_phys, iommu->ecap);
1266 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1267 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1272 /* TODO: check all IOAPICs are covered by IOMMU */
1274 /* Setup Interrupt-remapping now. */
1275 ret = intel_setup_irq_remapping(iommu);
1277 pr_err("DRHD %Lx: failed to allocate resource\n",
1279 ir_remove_ioapic_hpet_scope(iommu);
1284 /* Clear previous faults. */
1285 dmar_fault(-1, iommu);
1286 iommu_disable_irq_remapping(iommu);
1287 dmar_disable_qi(iommu);
1290 /* Enable queued invalidation */
1291 ret = dmar_enable_qi(iommu);
1293 iommu_set_irq_remapping(iommu, eim);
1295 pr_err("DRHD %Lx: failed to enable queued invalidation, ecap %Lx, ret %d\n",
1296 iommu->reg_phys, iommu->ecap, ret);
1297 intel_teardown_irq_remapping(iommu);
1298 ir_remove_ioapic_hpet_scope(iommu);
1304 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1307 struct intel_iommu *iommu = dmaru->iommu;
1309 if (!irq_remapping_enabled)
1313 if (!ecap_ir_support(iommu->ecap))
1317 if (!iommu->ir_table)
1318 ret = dmar_ir_add(dmaru, iommu);
1320 if (iommu->ir_table) {
1321 if (!bitmap_empty(iommu->ir_table->bitmap,
1322 INTR_REMAP_TABLE_ENTRIES)) {
1325 iommu_disable_irq_remapping(iommu);
1326 intel_teardown_irq_remapping(iommu);
1327 ir_remove_ioapic_hpet_scope(iommu);